arch/cris/arch-v32/mach-fs/dram_init.S

   1 /*
   2  * DRAM/SDRAM initialization - alter with care
   3  * This file is intended to be included from other assembler files
   4  *
   5  * Note: This file may not modify r8 or r9 because they are used to
   6  * carry information from the decompressor to the kernel
   7  *
   8  * Copyright (C) 2000-2007 Axis Communications AB
   9  *
  10  * Authors:  Mikael Starvik <starvik@axis.com>
  11  */
  12
  13 /* Just to be certain the config file is included, we include it here
  14  * explicitly instead of depending on it being included in the file that
  15  * uses this code.
  16  */
  17
  18 #include <hwregs/asm/reg_map_asm.h>
  19 #include <hwregs/asm/bif_core_defs_asm.h>
  20
  21         ;; WARNING! The registers r8 and r9 are used as parameters carrying
  22         ;; information from the decompressor (if the kernel was compressed).
  23         ;; They should not be used in the code below.
  24
  25         ; Refer to BIF MDS for a description of SDRAM initialization
  26
  27         ; Bank configuration
  28         move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0), $r0
  29         move.d   CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
  30         move.d   $r1, [$r0]
  31         move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1), $r0
  32         move.d   CONFIG_ETRAX_SDRAM_GRP1_CONFIG, $r1
  33         move.d   $r1, [$r0]
  34
  35         ; Calculate value of mrs_data
  36         ; CAS latency = 2 && bus_width = 32 => 0x40
  37         ; CAS latency = 3 && bus_width = 32 => 0x60
  38         ; CAS latency = 2 && bus_width = 16 => 0x20
  39         ; CAS latency = 3 && bus_width = 16 => 0x30
  40
  41         ; Check if value is already supplied in kernel config
  42         move.d   CONFIG_ETRAX_SDRAM_COMMAND, $r2
  43         bne      _set_timing
  44         nop
  45
  46         move.d   0x40, $r4       ; Assume 32 bits and CAS latency = 2
  47         move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
  48         and.d    0x07, $r1       ; Get CAS latency
  49         cmpq     2, $r1          ; CL = 2 ?
  50         beq      _bw_check
  51         nop
  52         move.d   0x60, $r4
  53
  54 _bw_check:
  55         ; Assume that group 0 width is equal to group 1. This assumption
  56         ; is wrong for a group 1 only hardware (such as the grand old
  57         ; StorPoint+).
  58         move.d   CONFIG_ETRAX_SDRAM_GRP0_CONFIG, $r1
  59         and.d    0x200, $r1     ; DRAM width is bit 9
  60         beq      _set_timing
  61         lslq     2, $r4         ;  mrs_data starts at bit 2
  62         lsrq     1, $r4         ;  16 bits. Shift down value.
  63
  64         ; Set timing parameters (refresh off to avoid Guinness TR 83)
  65 _set_timing:
  66         move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
  67         and.d    ~(3 << reg_bif_core_rw_sdram_timing___ref___lsb), $r1
  68         move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
  69         move.d   $r1, [$r0]
  70
  71         ; Issue NOP command
  72         move.d REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd), $r5
  73         moveq regk_bif_core_nop, $r1
  74         move.d $r1, [$r5]
  75
  76         ; Wait 200us
  77         move.d   10000, $r2
  78 1:      bne      1b
  79         subq     1, $r2
  80
  81         ; Issue initialization command sequence
  82         lapc     _sdram_commands_start, $r2
  83         lapc     _sdram_commands_end,  $r3
  84 1:      clear.d  $r6
  85         move.b   [$r2+], $r6    ; Load command
  86         or.d     $r4, $r6       ; Add calculated mrs
  87         move.d   $r6, [$r5]     ; Write rw_sdram_cmd
  88         ; Wait 80 ns between each command
  89         move.d   4000, $r7
  90 2:      bne      2b
  91         subq     1, $r7
  92         cmp.d    $r2, $r3       ; Last command?
  93         bne      1b
  94         nop
  95
  96         ; Start refresh
  97         move.d   CONFIG_ETRAX_SDRAM_TIMING, $r1
  98         move.d   REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing), $r0
  99         move.d   $r1, [$r0]
 100
 101         ; Initialization finished
 102         ba       _sdram_commands_end
 103         nop
 104
 105 _sdram_commands_start:
 106         .byte   regk_bif_core_pre ; Precharge
 107         .byte   regk_bif_core_ref ; refresh
 108         .byte   regk_bif_core_ref ; refresh
 109         .byte   regk_bif_core_ref ; refresh
 110         .byte   regk_bif_core_ref ; refresh
 111         .byte   regk_bif_core_ref ; refresh
 112         .byte   regk_bif_core_ref ; refresh
 113         .byte   regk_bif_core_ref ; refresh
 114         .byte   regk_bif_core_ref ; refresh
 115         .byte   regk_bif_core_mrs ; mrs
 116 _sdram_commands_end: