arch/cris/include/arch-v32/arch/hwregs/bif_dma_defs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __bif_dma_defs_h
   3 #define __bif_dma_defs_h
   4
   5 /*
   6  * This file is autogenerated from
   7  *   file:           ../../inst/bif/rtl/bif_dma_regs.r
   8  *     id:           bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
   9  *     last modfied: Mon Apr 11 16:06:33 2005
  10  *
  11  *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
  12  *      id: $Id: bif_dma_defs.h,v 1.2 2005/04/24 18:30:58 starvik Exp $
  13  * Any changes here will be lost.
  14  *
  15  * -*- buffer-read-only: t -*-
  16  */
  17 /* Main access macros */
  18 #ifndef REG_RD
  19 #define REG_RD( scope, inst, reg ) \
  20   REG_READ( reg_##scope##_##reg, \
  21             (inst) + REG_RD_ADDR_##scope##_##reg )
  22 #endif
  23
  24 #ifndef REG_WR
  25 #define REG_WR( scope, inst, reg, val ) \
  26   REG_WRITE( reg_##scope##_##reg, \
  27              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  28 #endif
  29
  30 #ifndef REG_RD_VECT
  31 #define REG_RD_VECT( scope, inst, reg, index ) \
  32   REG_READ( reg_##scope##_##reg, \
  33             (inst) + REG_RD_ADDR_##scope##_##reg + \
  34             (index) * STRIDE_##scope##_##reg )
  35 #endif
  36
  37 #ifndef REG_WR_VECT
  38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
  39   REG_WRITE( reg_##scope##_##reg, \
  40              (inst) + REG_WR_ADDR_##scope##_##reg + \
  41              (index) * STRIDE_##scope##_##reg, (val) )
  42 #endif
  43
  44 #ifndef REG_RD_INT
  45 #define REG_RD_INT( scope, inst, reg ) \
  46   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  47 #endif
  48
  49 #ifndef REG_WR_INT
  50 #define REG_WR_INT( scope, inst, reg, val ) \
  51   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  52 #endif
  53
  54 #ifndef REG_RD_INT_VECT
  55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
  56   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  57             (index) * STRIDE_##scope##_##reg )
  58 #endif
  59
  60 #ifndef REG_WR_INT_VECT
  61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  62   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  63              (index) * STRIDE_##scope##_##reg, (val) )
  64 #endif
  65
  66 #ifndef REG_TYPE_CONV
  67 #define REG_TYPE_CONV( type, orgtype, val ) \
  68   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  69 #endif
  70
  71 #ifndef reg_page_size
  72 #define reg_page_size 8192
  73 #endif
  74
  75 #ifndef REG_ADDR
  76 #define REG_ADDR( scope, inst, reg ) \
  77   ( (inst) + REG_RD_ADDR_##scope##_##reg )
  78 #endif
  79
  80 #ifndef REG_ADDR_VECT
  81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  82   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  83     (index) * STRIDE_##scope##_##reg )
  84 #endif
  85
  86 /* C-code for register scope bif_dma */
  87
  88 /* Register rw_ch0_ctrl, scope bif_dma, type rw */
  89 typedef struct {
  90   unsigned int bw         : 2;
  91   unsigned int burst_len  : 1;
  92   unsigned int cont       : 1;
  93   unsigned int end_pad    : 1;
  94   unsigned int cnt        : 1;
  95   unsigned int dreq_pin   : 3;
  96   unsigned int dreq_mode  : 2;
  97   unsigned int tc_in_pin  : 3;
  98   unsigned int tc_in_mode : 2;
  99   unsigned int bus_mode   : 2;
 100   unsigned int rate_en    : 1;
 101   unsigned int wr_all     : 1;
 102   unsigned int dummy1     : 12;
 103 } reg_bif_dma_rw_ch0_ctrl;
 104 #define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0
 105 #define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0
 106
 107 /* Register rw_ch0_addr, scope bif_dma, type rw */
 108 typedef struct {
 109   unsigned int addr : 32;
 110 } reg_bif_dma_rw_ch0_addr;
 111 #define REG_RD_ADDR_bif_dma_rw_ch0_addr 4
 112 #define REG_WR_ADDR_bif_dma_rw_ch0_addr 4
 113
 114 /* Register rw_ch0_start, scope bif_dma, type rw */
 115 typedef struct {
 116   unsigned int run : 1;
 117   unsigned int dummy1 : 31;
 118 } reg_bif_dma_rw_ch0_start;
 119 #define REG_RD_ADDR_bif_dma_rw_ch0_start 8
 120 #define REG_WR_ADDR_bif_dma_rw_ch0_start 8
 121
 122 /* Register rw_ch0_cnt, scope bif_dma, type rw */
 123 typedef struct {
 124   unsigned int start_cnt : 16;
 125   unsigned int dummy1    : 16;
 126 } reg_bif_dma_rw_ch0_cnt;
 127 #define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12
 128 #define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12
 129
 130 /* Register r_ch0_stat, scope bif_dma, type r */
 131 typedef struct {
 132   unsigned int cnt : 16;
 133   unsigned int dummy1 : 15;
 134   unsigned int run : 1;
 135 } reg_bif_dma_r_ch0_stat;
 136 #define REG_RD_ADDR_bif_dma_r_ch0_stat 16
 137
 138 /* Register rw_ch1_ctrl, scope bif_dma, type rw */
 139 typedef struct {
 140   unsigned int bw          : 2;
 141   unsigned int burst_len   : 1;
 142   unsigned int cont        : 1;
 143   unsigned int end_discard : 1;
 144   unsigned int cnt         : 1;
 145   unsigned int dreq_pin    : 3;
 146   unsigned int dreq_mode   : 2;
 147   unsigned int tc_in_pin   : 3;
 148   unsigned int tc_in_mode  : 2;
 149   unsigned int bus_mode    : 2;
 150   unsigned int rate_en     : 1;
 151   unsigned int dummy1      : 13;
 152 } reg_bif_dma_rw_ch1_ctrl;
 153 #define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32
 154 #define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32
 155
 156 /* Register rw_ch1_addr, scope bif_dma, type rw */
 157 typedef struct {
 158   unsigned int addr : 32;
 159 } reg_bif_dma_rw_ch1_addr;
 160 #define REG_RD_ADDR_bif_dma_rw_ch1_addr 36
 161 #define REG_WR_ADDR_bif_dma_rw_ch1_addr 36
 162
 163 /* Register rw_ch1_start, scope bif_dma, type rw */
 164 typedef struct {
 165   unsigned int run : 1;
 166   unsigned int dummy1 : 31;
 167 } reg_bif_dma_rw_ch1_start;
 168 #define REG_RD_ADDR_bif_dma_rw_ch1_start 40
 169 #define REG_WR_ADDR_bif_dma_rw_ch1_start 40
 170
 171 /* Register rw_ch1_cnt, scope bif_dma, type rw */
 172 typedef struct {
 173   unsigned int start_cnt : 16;
 174   unsigned int dummy1    : 16;
 175 } reg_bif_dma_rw_ch1_cnt;
 176 #define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44
 177 #define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44
 178
 179 /* Register r_ch1_stat, scope bif_dma, type r */
 180 typedef struct {
 181   unsigned int cnt : 16;
 182   unsigned int dummy1 : 15;
 183   unsigned int run : 1;
 184 } reg_bif_dma_r_ch1_stat;
 185 #define REG_RD_ADDR_bif_dma_r_ch1_stat 48
 186
 187 /* Register rw_ch2_ctrl, scope bif_dma, type rw */
 188 typedef struct {
 189   unsigned int bw         : 2;
 190   unsigned int burst_len  : 1;
 191   unsigned int cont       : 1;
 192   unsigned int end_pad    : 1;
 193   unsigned int cnt        : 1;
 194   unsigned int dreq_pin   : 3;
 195   unsigned int dreq_mode  : 2;
 196   unsigned int tc_in_pin  : 3;
 197   unsigned int tc_in_mode : 2;
 198   unsigned int bus_mode   : 2;
 199   unsigned int rate_en    : 1;
 200   unsigned int wr_all     : 1;
 201   unsigned int dummy1     : 12;
 202 } reg_bif_dma_rw_ch2_ctrl;
 203 #define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64
 204 #define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64
 205
 206 /* Register rw_ch2_addr, scope bif_dma, type rw */
 207 typedef struct {
 208   unsigned int addr : 32;
 209 } reg_bif_dma_rw_ch2_addr;
 210 #define REG_RD_ADDR_bif_dma_rw_ch2_addr 68
 211 #define REG_WR_ADDR_bif_dma_rw_ch2_addr 68
 212
 213 /* Register rw_ch2_start, scope bif_dma, type rw */
 214 typedef struct {
 215   unsigned int run : 1;
 216   unsigned int dummy1 : 31;
 217 } reg_bif_dma_rw_ch2_start;
 218 #define REG_RD_ADDR_bif_dma_rw_ch2_start 72
 219 #define REG_WR_ADDR_bif_dma_rw_ch2_start 72
 220
 221 /* Register rw_ch2_cnt, scope bif_dma, type rw */
 222 typedef struct {
 223   unsigned int start_cnt : 16;
 224   unsigned int dummy1    : 16;
 225 } reg_bif_dma_rw_ch2_cnt;
 226 #define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76
 227 #define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76
 228
 229 /* Register r_ch2_stat, scope bif_dma, type r */
 230 typedef struct {
 231   unsigned int cnt : 16;
 232   unsigned int dummy1 : 15;
 233   unsigned int run : 1;
 234 } reg_bif_dma_r_ch2_stat;
 235 #define REG_RD_ADDR_bif_dma_r_ch2_stat 80
 236
 237 /* Register rw_ch3_ctrl, scope bif_dma, type rw */
 238 typedef struct {
 239   unsigned int bw          : 2;
 240   unsigned int burst_len   : 1;
 241   unsigned int cont        : 1;
 242   unsigned int end_discard : 1;
 243   unsigned int cnt         : 1;
 244   unsigned int dreq_pin    : 3;
 245   unsigned int dreq_mode   : 2;
 246   unsigned int tc_in_pin   : 3;
 247   unsigned int tc_in_mode  : 2;
 248   unsigned int bus_mode    : 2;
 249   unsigned int rate_en     : 1;
 250   unsigned int dummy1      : 13;
 251 } reg_bif_dma_rw_ch3_ctrl;
 252 #define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96
 253 #define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96
 254
 255 /* Register rw_ch3_addr, scope bif_dma, type rw */
 256 typedef struct {
 257   unsigned int addr : 32;
 258 } reg_bif_dma_rw_ch3_addr;
 259 #define REG_RD_ADDR_bif_dma_rw_ch3_addr 100
 260 #define REG_WR_ADDR_bif_dma_rw_ch3_addr 100
 261
 262 /* Register rw_ch3_start, scope bif_dma, type rw */
 263 typedef struct {
 264   unsigned int run : 1;
 265   unsigned int dummy1 : 31;
 266 } reg_bif_dma_rw_ch3_start;
 267 #define REG_RD_ADDR_bif_dma_rw_ch3_start 104
 268 #define REG_WR_ADDR_bif_dma_rw_ch3_start 104
 269
 270 /* Register rw_ch3_cnt, scope bif_dma, type rw */
 271 typedef struct {
 272   unsigned int start_cnt : 16;
 273   unsigned int dummy1    : 16;
 274 } reg_bif_dma_rw_ch3_cnt;
 275 #define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108
 276 #define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108
 277
 278 /* Register r_ch3_stat, scope bif_dma, type r */
 279 typedef struct {
 280   unsigned int cnt : 16;
 281   unsigned int dummy1 : 15;
 282   unsigned int run : 1;
 283 } reg_bif_dma_r_ch3_stat;
 284 #define REG_RD_ADDR_bif_dma_r_ch3_stat 112
 285
 286 /* Register rw_intr_mask, scope bif_dma, type rw */
 287 typedef struct {
 288   unsigned int ext_dma0 : 1;
 289   unsigned int ext_dma1 : 1;
 290   unsigned int ext_dma2 : 1;
 291   unsigned int ext_dma3 : 1;
 292   unsigned int dummy1   : 28;
 293 } reg_bif_dma_rw_intr_mask;
 294 #define REG_RD_ADDR_bif_dma_rw_intr_mask 128
 295 #define REG_WR_ADDR_bif_dma_rw_intr_mask 128
 296
 297 /* Register rw_ack_intr, scope bif_dma, type rw */
 298 typedef struct {
 299   unsigned int ext_dma0 : 1;
 300   unsigned int ext_dma1 : 1;
 301   unsigned int ext_dma2 : 1;
 302   unsigned int ext_dma3 : 1;
 303   unsigned int dummy1   : 28;
 304 } reg_bif_dma_rw_ack_intr;
 305 #define REG_RD_ADDR_bif_dma_rw_ack_intr 132
 306 #define REG_WR_ADDR_bif_dma_rw_ack_intr 132
 307
 308 /* Register r_intr, scope bif_dma, type r */
 309 typedef struct {
 310   unsigned int ext_dma0 : 1;
 311   unsigned int ext_dma1 : 1;
 312   unsigned int ext_dma2 : 1;
 313   unsigned int ext_dma3 : 1;
 314   unsigned int dummy1   : 28;
 315 } reg_bif_dma_r_intr;
 316 #define REG_RD_ADDR_bif_dma_r_intr 136
 317
 318 /* Register r_masked_intr, scope bif_dma, type r */
 319 typedef struct {
 320   unsigned int ext_dma0 : 1;
 321   unsigned int ext_dma1 : 1;
 322   unsigned int ext_dma2 : 1;
 323   unsigned int ext_dma3 : 1;
 324   unsigned int dummy1   : 28;
 325 } reg_bif_dma_r_masked_intr;
 326 #define REG_RD_ADDR_bif_dma_r_masked_intr 140
 327
 328 /* Register rw_pin0_cfg, scope bif_dma, type rw */
 329 typedef struct {
 330   unsigned int master_ch   : 2;
 331   unsigned int master_mode : 3;
 332   unsigned int slave_ch    : 2;
 333   unsigned int slave_mode  : 3;
 334   unsigned int dummy1      : 22;
 335 } reg_bif_dma_rw_pin0_cfg;
 336 #define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160
 337 #define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160
 338
 339 /* Register rw_pin1_cfg, scope bif_dma, type rw */
 340 typedef struct {
 341   unsigned int master_ch   : 2;
 342   unsigned int master_mode : 3;
 343   unsigned int slave_ch    : 2;
 344   unsigned int slave_mode  : 3;
 345   unsigned int dummy1      : 22;
 346 } reg_bif_dma_rw_pin1_cfg;
 347 #define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164
 348 #define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164
 349
 350 /* Register rw_pin2_cfg, scope bif_dma, type rw */
 351 typedef struct {
 352   unsigned int master_ch   : 2;
 353   unsigned int master_mode : 3;
 354   unsigned int slave_ch    : 2;
 355   unsigned int slave_mode  : 3;
 356   unsigned int dummy1      : 22;
 357 } reg_bif_dma_rw_pin2_cfg;
 358 #define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168
 359 #define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168
 360
 361 /* Register rw_pin3_cfg, scope bif_dma, type rw */
 362 typedef struct {
 363   unsigned int master_ch   : 2;
 364   unsigned int master_mode : 3;
 365   unsigned int slave_ch    : 2;
 366   unsigned int slave_mode  : 3;
 367   unsigned int dummy1      : 22;
 368 } reg_bif_dma_rw_pin3_cfg;
 369 #define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172
 370 #define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172
 371
 372 /* Register rw_pin4_cfg, scope bif_dma, type rw */
 373 typedef struct {
 374   unsigned int master_ch   : 2;
 375   unsigned int master_mode : 3;
 376   unsigned int slave_ch    : 2;
 377   unsigned int slave_mode  : 3;
 378   unsigned int dummy1      : 22;
 379 } reg_bif_dma_rw_pin4_cfg;
 380 #define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176
 381 #define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176
 382
 383 /* Register rw_pin5_cfg, scope bif_dma, type rw */
 384 typedef struct {
 385   unsigned int master_ch   : 2;
 386   unsigned int master_mode : 3;
 387   unsigned int slave_ch    : 2;
 388   unsigned int slave_mode  : 3;
 389   unsigned int dummy1      : 22;
 390 } reg_bif_dma_rw_pin5_cfg;
 391 #define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180
 392 #define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180
 393
 394 /* Register rw_pin6_cfg, scope bif_dma, type rw */
 395 typedef struct {
 396   unsigned int master_ch   : 2;
 397   unsigned int master_mode : 3;
 398   unsigned int slave_ch    : 2;
 399   unsigned int slave_mode  : 3;
 400   unsigned int dummy1      : 22;
 401 } reg_bif_dma_rw_pin6_cfg;
 402 #define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184
 403 #define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184
 404
 405 /* Register rw_pin7_cfg, scope bif_dma, type rw */
 406 typedef struct {
 407   unsigned int master_ch   : 2;
 408   unsigned int master_mode : 3;
 409   unsigned int slave_ch    : 2;
 410   unsigned int slave_mode  : 3;
 411   unsigned int dummy1      : 22;
 412 } reg_bif_dma_rw_pin7_cfg;
 413 #define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188
 414 #define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188
 415
 416 /* Register r_pin_stat, scope bif_dma, type r */
 417 typedef struct {
 418   unsigned int pin0 : 1;
 419   unsigned int pin1 : 1;
 420   unsigned int pin2 : 1;
 421   unsigned int pin3 : 1;
 422   unsigned int pin4 : 1;
 423   unsigned int pin5 : 1;
 424   unsigned int pin6 : 1;
 425   unsigned int pin7 : 1;
 426   unsigned int dummy1 : 24;
 427 } reg_bif_dma_r_pin_stat;
 428 #define REG_RD_ADDR_bif_dma_r_pin_stat 192
 429
 430
 431 /* Constants */
 432 enum {
 433   regk_bif_dma_as_master                   = 0x00000001,
 434   regk_bif_dma_as_slave                    = 0x00000001,
 435   regk_bif_dma_burst1                      = 0x00000000,
 436   regk_bif_dma_burst8                      = 0x00000001,
 437   regk_bif_dma_bw16                        = 0x00000001,
 438   regk_bif_dma_bw32                        = 0x00000002,
 439   regk_bif_dma_bw8                         = 0x00000000,
 440   regk_bif_dma_dack                        = 0x00000006,
 441   regk_bif_dma_dack_inv                    = 0x00000007,
 442   regk_bif_dma_force                       = 0x00000001,
 443   regk_bif_dma_hi                          = 0x00000003,
 444   regk_bif_dma_inv                         = 0x00000003,
 445   regk_bif_dma_lo                          = 0x00000002,
 446   regk_bif_dma_master                      = 0x00000001,
 447   regk_bif_dma_no                          = 0x00000000,
 448   regk_bif_dma_norm                        = 0x00000002,
 449   regk_bif_dma_off                         = 0x00000000,
 450   regk_bif_dma_rw_ch0_ctrl_default         = 0x00000000,
 451   regk_bif_dma_rw_ch0_start_default        = 0x00000000,
 452   regk_bif_dma_rw_ch1_ctrl_default         = 0x00000000,
 453   regk_bif_dma_rw_ch1_start_default        = 0x00000000,
 454   regk_bif_dma_rw_ch2_ctrl_default         = 0x00000000,
 455   regk_bif_dma_rw_ch2_start_default        = 0x00000000,
 456   regk_bif_dma_rw_ch3_ctrl_default         = 0x00000000,
 457   regk_bif_dma_rw_ch3_start_default        = 0x00000000,
 458   regk_bif_dma_rw_intr_mask_default        = 0x00000000,
 459   regk_bif_dma_rw_pin0_cfg_default         = 0x00000000,
 460   regk_bif_dma_rw_pin1_cfg_default         = 0x00000000,
 461   regk_bif_dma_rw_pin2_cfg_default         = 0x00000000,
 462   regk_bif_dma_rw_pin3_cfg_default         = 0x00000000,
 463   regk_bif_dma_rw_pin4_cfg_default         = 0x00000000,
 464   regk_bif_dma_rw_pin5_cfg_default         = 0x00000000,
 465   regk_bif_dma_rw_pin6_cfg_default         = 0x00000000,
 466   regk_bif_dma_rw_pin7_cfg_default         = 0x00000000,
 467   regk_bif_dma_slave                       = 0x00000002,
 468   regk_bif_dma_sreq                        = 0x00000006,
 469   regk_bif_dma_sreq_inv                    = 0x00000007,
 470   regk_bif_dma_tc                          = 0x00000004,
 471   regk_bif_dma_tc_inv                      = 0x00000005,
 472   regk_bif_dma_yes                         = 0x00000001
 473 };
 474 #endif /* __bif_dma_defs_h */