arch/cris/include/arch-v32/arch/hwregs/cpu_vect.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
   3  from ../../inst/crisp/doc/cpu_vect.r
   4 version . */
   5
   6 #ifndef _______INST_CRISP_DOC_CPU_VECT_R
   7 #define _______INST_CRISP_DOC_CPU_VECT_R
   8 #define NMI_INTR_VECT   0x00
   9 #define RESERVED_1_INTR_VECT    0x01
  10 #define RESERVED_2_INTR_VECT    0x02
  11 #define SINGLE_STEP_INTR_VECT   0x03
  12 #define INSTR_TLB_REFILL_INTR_VECT      0x04
  13 #define INSTR_TLB_INV_INTR_VECT 0x05
  14 #define INSTR_TLB_ACC_INTR_VECT 0x06
  15 #define TLB_EX_INTR_VECT        0x07
  16 #define DATA_TLB_REFILL_INTR_VECT       0x08
  17 #define DATA_TLB_INV_INTR_VECT  0x09
  18 #define DATA_TLB_ACC_INTR_VECT  0x0a
  19 #define DATA_TLB_WE_INTR_VECT   0x0b
  20 #define HW_BP_INTR_VECT 0x0c
  21 #define RESERVED_D_INTR_VECT    0x0d
  22 #define RESERVED_E_INTR_VECT    0x0e
  23 #define RESERVED_F_INTR_VECT    0x0f
  24 #define BREAK_0_INTR_VECT       0x10
  25 #define BREAK_1_INTR_VECT       0x11
  26 #define BREAK_2_INTR_VECT       0x12
  27 #define BREAK_3_INTR_VECT       0x13
  28 #define BREAK_4_INTR_VECT       0x14
  29 #define BREAK_5_INTR_VECT       0x15
  30 #define BREAK_6_INTR_VECT       0x16
  31 #define BREAK_7_INTR_VECT       0x17
  32 #define BREAK_8_INTR_VECT       0x18
  33 #define BREAK_9_INTR_VECT       0x19
  34 #define BREAK_10_INTR_VECT      0x1a
  35 #define BREAK_11_INTR_VECT      0x1b
  36 #define BREAK_12_INTR_VECT      0x1c
  37 #define BREAK_13_INTR_VECT      0x1d
  38 #define BREAK_14_INTR_VECT      0x1e
  39 #define BREAK_15_INTR_VECT      0x1f
  40 #define MULTIPLE_INTR_VECT      0x30
  41
  42 #endif