arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __iop_fifo_out_defs_asm_h
   3 #define __iop_fifo_out_defs_asm_h
   4
   5 /*
   6  * This file is autogenerated from
   7  *   file:           ../../inst/io_proc/rtl/iop_fifo_out.r
   8  *     id:           <not found>
   9  *     last modfied: Mon Apr 11 16:10:09 2005
  10  *
  11  *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r
  12  *      id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
  13  * Any changes here will be lost.
  14  *
  15  * -*- buffer-read-only: t -*-
  16  */
  17
  18 #ifndef REG_FIELD
  19 #define REG_FIELD( scope, reg, field, value ) \
  20   REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
  21 #define REG_FIELD_X_( value, shift ) ((value) << shift)
  22 #endif
  23
  24 #ifndef REG_STATE
  25 #define REG_STATE( scope, reg, field, symbolic_value ) \
  26   REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
  27 #define REG_STATE_X_( k, shift ) (k << shift)
  28 #endif
  29
  30 #ifndef REG_MASK
  31 #define REG_MASK( scope, reg, field ) \
  32   REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
  33 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
  34 #endif
  35
  36 #ifndef REG_LSB
  37 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
  38 #endif
  39
  40 #ifndef REG_BIT
  41 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
  42 #endif
  43
  44 #ifndef REG_ADDR
  45 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
  46 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
  47 #endif
  48
  49 #ifndef REG_ADDR_VECT
  50 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  51          REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
  52                          STRIDE_##scope##_##reg )
  53 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
  54                           ((inst) + offs + (index) * stride)
  55 #endif
  56
  57 /* Register rw_cfg, scope iop_fifo_out, type rw */
  58 #define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0
  59 #define reg_iop_fifo_out_rw_cfg___free_lim___width 3
  60 #define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3
  61 #define reg_iop_fifo_out_rw_cfg___byte_order___width 2
  62 #define reg_iop_fifo_out_rw_cfg___trig___lsb 5
  63 #define reg_iop_fifo_out_rw_cfg___trig___width 2
  64 #define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7
  65 #define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1
  66 #define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7
  67 #define reg_iop_fifo_out_rw_cfg___mode___lsb 8
  68 #define reg_iop_fifo_out_rw_cfg___mode___width 2
  69 #define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10
  70 #define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1
  71 #define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10
  72 #define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11
  73 #define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1
  74 #define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11
  75 #define reg_iop_fifo_out_rw_cfg_offset 0
  76
  77 /* Register rw_ctrl, scope iop_fifo_out, type rw */
  78 #define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0
  79 #define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1
  80 #define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0
  81 #define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1
  82 #define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1
  83 #define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1
  84 #define reg_iop_fifo_out_rw_ctrl_offset 4
  85
  86 /* Register r_stat, scope iop_fifo_out, type r */
  87 #define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0
  88 #define reg_iop_fifo_out_r_stat___avail_bytes___width 4
  89 #define reg_iop_fifo_out_r_stat___last___lsb 4
  90 #define reg_iop_fifo_out_r_stat___last___width 8
  91 #define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12
  92 #define reg_iop_fifo_out_r_stat___dif_in_en___width 1
  93 #define reg_iop_fifo_out_r_stat___dif_in_en___bit 12
  94 #define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13
  95 #define reg_iop_fifo_out_r_stat___dif_out_en___width 1
  96 #define reg_iop_fifo_out_r_stat___dif_out_en___bit 13
  97 #define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14
  98 #define reg_iop_fifo_out_r_stat___zero_data_last___width 1
  99 #define reg_iop_fifo_out_r_stat___zero_data_last___bit 14
 100 #define reg_iop_fifo_out_r_stat_offset 8
 101
 102 /* Register rw_wr1byte, scope iop_fifo_out, type rw */
 103 #define reg_iop_fifo_out_rw_wr1byte___data___lsb 0
 104 #define reg_iop_fifo_out_rw_wr1byte___data___width 8
 105 #define reg_iop_fifo_out_rw_wr1byte_offset 12
 106
 107 /* Register rw_wr2byte, scope iop_fifo_out, type rw */
 108 #define reg_iop_fifo_out_rw_wr2byte___data___lsb 0
 109 #define reg_iop_fifo_out_rw_wr2byte___data___width 16
 110 #define reg_iop_fifo_out_rw_wr2byte_offset 16
 111
 112 /* Register rw_wr3byte, scope iop_fifo_out, type rw */
 113 #define reg_iop_fifo_out_rw_wr3byte___data___lsb 0
 114 #define reg_iop_fifo_out_rw_wr3byte___data___width 24
 115 #define reg_iop_fifo_out_rw_wr3byte_offset 20
 116
 117 /* Register rw_wr4byte, scope iop_fifo_out, type rw */
 118 #define reg_iop_fifo_out_rw_wr4byte___data___lsb 0
 119 #define reg_iop_fifo_out_rw_wr4byte___data___width 32
 120 #define reg_iop_fifo_out_rw_wr4byte_offset 24
 121
 122 /* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
 123 #define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0
 124 #define reg_iop_fifo_out_rw_wr1byte_last___data___width 8
 125 #define reg_iop_fifo_out_rw_wr1byte_last_offset 28
 126
 127 /* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
 128 #define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0
 129 #define reg_iop_fifo_out_rw_wr2byte_last___data___width 16
 130 #define reg_iop_fifo_out_rw_wr2byte_last_offset 32
 131
 132 /* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
 133 #define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0
 134 #define reg_iop_fifo_out_rw_wr3byte_last___data___width 24
 135 #define reg_iop_fifo_out_rw_wr3byte_last_offset 36
 136
 137 /* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
 138 #define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0
 139 #define reg_iop_fifo_out_rw_wr4byte_last___data___width 32
 140 #define reg_iop_fifo_out_rw_wr4byte_last_offset 40
 141
 142 /* Register rw_set_last, scope iop_fifo_out, type rw */
 143 #define reg_iop_fifo_out_rw_set_last_offset 44
 144
 145 /* Register rs_rd_data, scope iop_fifo_out, type rs */
 146 #define reg_iop_fifo_out_rs_rd_data_offset 48
 147
 148 /* Register r_rd_data, scope iop_fifo_out, type r */
 149 #define reg_iop_fifo_out_r_rd_data_offset 52
 150
 151 /* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
 152 #define reg_iop_fifo_out_rw_strb_dif_out_offset 56
 153
 154 /* Register rw_intr_mask, scope iop_fifo_out, type rw */
 155 #define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0
 156 #define reg_iop_fifo_out_rw_intr_mask___urun___width 1
 157 #define reg_iop_fifo_out_rw_intr_mask___urun___bit 0
 158 #define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1
 159 #define reg_iop_fifo_out_rw_intr_mask___last_data___width 1
 160 #define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1
 161 #define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2
 162 #define reg_iop_fifo_out_rw_intr_mask___dav___width 1
 163 #define reg_iop_fifo_out_rw_intr_mask___dav___bit 2
 164 #define reg_iop_fifo_out_rw_intr_mask___free___lsb 3
 165 #define reg_iop_fifo_out_rw_intr_mask___free___width 1
 166 #define reg_iop_fifo_out_rw_intr_mask___free___bit 3
 167 #define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4
 168 #define reg_iop_fifo_out_rw_intr_mask___orun___width 1
 169 #define reg_iop_fifo_out_rw_intr_mask___orun___bit 4
 170 #define reg_iop_fifo_out_rw_intr_mask_offset 60
 171
 172 /* Register rw_ack_intr, scope iop_fifo_out, type rw */
 173 #define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0
 174 #define reg_iop_fifo_out_rw_ack_intr___urun___width 1
 175 #define reg_iop_fifo_out_rw_ack_intr___urun___bit 0
 176 #define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1
 177 #define reg_iop_fifo_out_rw_ack_intr___last_data___width 1
 178 #define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1
 179 #define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2
 180 #define reg_iop_fifo_out_rw_ack_intr___dav___width 1
 181 #define reg_iop_fifo_out_rw_ack_intr___dav___bit 2
 182 #define reg_iop_fifo_out_rw_ack_intr___free___lsb 3
 183 #define reg_iop_fifo_out_rw_ack_intr___free___width 1
 184 #define reg_iop_fifo_out_rw_ack_intr___free___bit 3
 185 #define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4
 186 #define reg_iop_fifo_out_rw_ack_intr___orun___width 1
 187 #define reg_iop_fifo_out_rw_ack_intr___orun___bit 4
 188 #define reg_iop_fifo_out_rw_ack_intr_offset 64
 189
 190 /* Register r_intr, scope iop_fifo_out, type r */
 191 #define reg_iop_fifo_out_r_intr___urun___lsb 0
 192 #define reg_iop_fifo_out_r_intr___urun___width 1
 193 #define reg_iop_fifo_out_r_intr___urun___bit 0
 194 #define reg_iop_fifo_out_r_intr___last_data___lsb 1
 195 #define reg_iop_fifo_out_r_intr___last_data___width 1
 196 #define reg_iop_fifo_out_r_intr___last_data___bit 1
 197 #define reg_iop_fifo_out_r_intr___dav___lsb 2
 198 #define reg_iop_fifo_out_r_intr___dav___width 1
 199 #define reg_iop_fifo_out_r_intr___dav___bit 2
 200 #define reg_iop_fifo_out_r_intr___free___lsb 3
 201 #define reg_iop_fifo_out_r_intr___free___width 1
 202 #define reg_iop_fifo_out_r_intr___free___bit 3
 203 #define reg_iop_fifo_out_r_intr___orun___lsb 4
 204 #define reg_iop_fifo_out_r_intr___orun___width 1
 205 #define reg_iop_fifo_out_r_intr___orun___bit 4
 206 #define reg_iop_fifo_out_r_intr_offset 68
 207
 208 /* Register r_masked_intr, scope iop_fifo_out, type r */
 209 #define reg_iop_fifo_out_r_masked_intr___urun___lsb 0
 210 #define reg_iop_fifo_out_r_masked_intr___urun___width 1
 211 #define reg_iop_fifo_out_r_masked_intr___urun___bit 0
 212 #define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1
 213 #define reg_iop_fifo_out_r_masked_intr___last_data___width 1
 214 #define reg_iop_fifo_out_r_masked_intr___last_data___bit 1
 215 #define reg_iop_fifo_out_r_masked_intr___dav___lsb 2
 216 #define reg_iop_fifo_out_r_masked_intr___dav___width 1
 217 #define reg_iop_fifo_out_r_masked_intr___dav___bit 2
 218 #define reg_iop_fifo_out_r_masked_intr___free___lsb 3
 219 #define reg_iop_fifo_out_r_masked_intr___free___width 1
 220 #define reg_iop_fifo_out_r_masked_intr___free___bit 3
 221 #define reg_iop_fifo_out_r_masked_intr___orun___lsb 4
 222 #define reg_iop_fifo_out_r_masked_intr___orun___width 1
 223 #define reg_iop_fifo_out_r_masked_intr___orun___bit 4
 224 #define reg_iop_fifo_out_r_masked_intr_offset 72
 225
 226
 227 /* Constants */
 228 #define regk_iop_fifo_out_hi                      0x00000000
 229 #define regk_iop_fifo_out_neg                     0x00000002
 230 #define regk_iop_fifo_out_no                      0x00000000
 231 #define regk_iop_fifo_out_order16                 0x00000001
 232 #define regk_iop_fifo_out_order24                 0x00000002
 233 #define regk_iop_fifo_out_order32                 0x00000003
 234 #define regk_iop_fifo_out_order8                  0x00000000
 235 #define regk_iop_fifo_out_pos                     0x00000001
 236 #define regk_iop_fifo_out_pos_neg                 0x00000003
 237 #define regk_iop_fifo_out_rw_cfg_default          0x00000024
 238 #define regk_iop_fifo_out_rw_ctrl_default         0x00000000
 239 #define regk_iop_fifo_out_rw_intr_mask_default    0x00000000
 240 #define regk_iop_fifo_out_rw_set_last_default     0x00000000
 241 #define regk_iop_fifo_out_rw_strb_dif_out_default  0x00000000
 242 #define regk_iop_fifo_out_rw_wr1byte_default      0x00000000
 243 #define regk_iop_fifo_out_rw_wr1byte_last_default  0x00000000
 244 #define regk_iop_fifo_out_rw_wr2byte_default      0x00000000
 245 #define regk_iop_fifo_out_rw_wr2byte_last_default  0x00000000
 246 #define regk_iop_fifo_out_rw_wr3byte_default      0x00000000
 247 #define regk_iop_fifo_out_rw_wr3byte_last_default  0x00000000
 248 #define regk_iop_fifo_out_rw_wr4byte_default      0x00000000
 249 #define regk_iop_fifo_out_rw_wr4byte_last_default  0x00000000
 250 #define regk_iop_fifo_out_size16                  0x00000002
 251 #define regk_iop_fifo_out_size24                  0x00000001
 252 #define regk_iop_fifo_out_size32                  0x00000000
 253 #define regk_iop_fifo_out_size8                   0x00000003
 254 #define regk_iop_fifo_out_yes                     0x00000001
 255 #endif /* __iop_fifo_out_defs_asm_h */