arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __iop_timer_grp_defs_asm_h
   3 #define __iop_timer_grp_defs_asm_h
   4
   5 /*
   6  * This file is autogenerated from
   7  *   file:           ../../inst/io_proc/rtl/iop_timer_grp.r
   8  *     id:           iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
   9  *     last modfied: Mon Apr 11 16:08:46 2005
  10  *
  11  *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r
  12  *      id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
  13  * Any changes here will be lost.
  14  *
  15  * -*- buffer-read-only: t -*-
  16  */
  17
  18 #ifndef REG_FIELD
  19 #define REG_FIELD( scope, reg, field, value ) \
  20   REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
  21 #define REG_FIELD_X_( value, shift ) ((value) << shift)
  22 #endif
  23
  24 #ifndef REG_STATE
  25 #define REG_STATE( scope, reg, field, symbolic_value ) \
  26   REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
  27 #define REG_STATE_X_( k, shift ) (k << shift)
  28 #endif
  29
  30 #ifndef REG_MASK
  31 #define REG_MASK( scope, reg, field ) \
  32   REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
  33 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
  34 #endif
  35
  36 #ifndef REG_LSB
  37 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
  38 #endif
  39
  40 #ifndef REG_BIT
  41 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
  42 #endif
  43
  44 #ifndef REG_ADDR
  45 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
  46 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
  47 #endif
  48
  49 #ifndef REG_ADDR_VECT
  50 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  51          REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
  52                          STRIDE_##scope##_##reg )
  53 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
  54                           ((inst) + offs + (index) * stride)
  55 #endif
  56
  57 /* Register rw_cfg, scope iop_timer_grp, type rw */
  58 #define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0
  59 #define reg_iop_timer_grp_rw_cfg___clk_src___width 1
  60 #define reg_iop_timer_grp_rw_cfg___clk_src___bit 0
  61 #define reg_iop_timer_grp_rw_cfg___trig___lsb 1
  62 #define reg_iop_timer_grp_rw_cfg___trig___width 2
  63 #define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3
  64 #define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8
  65 #define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11
  66 #define reg_iop_timer_grp_rw_cfg___clk_div___width 8
  67 #define reg_iop_timer_grp_rw_cfg_offset 0
  68
  69 /* Register rw_half_period, scope iop_timer_grp, type rw */
  70 #define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0
  71 #define reg_iop_timer_grp_rw_half_period___quota_lo___width 15
  72 #define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15
  73 #define reg_iop_timer_grp_rw_half_period___quota_hi___width 15
  74 #define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30
  75 #define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1
  76 #define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30
  77 #define reg_iop_timer_grp_rw_half_period_offset 4
  78
  79 /* Register rw_half_period_len, scope iop_timer_grp, type rw */
  80 #define reg_iop_timer_grp_rw_half_period_len_offset 8
  81
  82 #define STRIDE_iop_timer_grp_rw_tmr_cfg 4
  83 /* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
  84 #define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0
  85 #define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3
  86 #define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3
  87 #define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2
  88 #define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5
  89 #define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2
  90 #define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7
  91 #define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1
  92 #define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7
  93 #define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8
  94 #define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2
  95 #define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10
  96 #define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1
  97 #define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10
  98 #define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11
  99 #define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2
 100 #define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13
 101 #define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2
 102 #define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15
 103 #define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1
 104 #define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15
 105 #define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16
 106 #define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1
 107 #define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16
 108 #define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17
 109 #define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1
 110 #define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17
 111 #define reg_iop_timer_grp_rw_tmr_cfg_offset 12
 112
 113 #define STRIDE_iop_timer_grp_rw_tmr_len 4
 114 /* Register rw_tmr_len, scope iop_timer_grp, type rw */
 115 #define reg_iop_timer_grp_rw_tmr_len___val___lsb 0
 116 #define reg_iop_timer_grp_rw_tmr_len___val___width 16
 117 #define reg_iop_timer_grp_rw_tmr_len_offset 44
 118
 119 /* Register rw_cmd, scope iop_timer_grp, type rw */
 120 #define reg_iop_timer_grp_rw_cmd___rst___lsb 0
 121 #define reg_iop_timer_grp_rw_cmd___rst___width 4
 122 #define reg_iop_timer_grp_rw_cmd___en___lsb 4
 123 #define reg_iop_timer_grp_rw_cmd___en___width 4
 124 #define reg_iop_timer_grp_rw_cmd___dis___lsb 8
 125 #define reg_iop_timer_grp_rw_cmd___dis___width 4
 126 #define reg_iop_timer_grp_rw_cmd___strb___lsb 12
 127 #define reg_iop_timer_grp_rw_cmd___strb___width 4
 128 #define reg_iop_timer_grp_rw_cmd_offset 60
 129
 130 /* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
 131 #define reg_iop_timer_grp_r_clk_gen_cnt_offset 64
 132
 133 #define STRIDE_iop_timer_grp_rs_tmr_cnt 8
 134 /* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
 135 #define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0
 136 #define reg_iop_timer_grp_rs_tmr_cnt___val___width 16
 137 #define reg_iop_timer_grp_rs_tmr_cnt_offset 68
 138
 139 #define STRIDE_iop_timer_grp_r_tmr_cnt 8
 140 /* Register r_tmr_cnt, scope iop_timer_grp, type r */
 141 #define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0
 142 #define reg_iop_timer_grp_r_tmr_cnt___val___width 16
 143 #define reg_iop_timer_grp_r_tmr_cnt_offset 72
 144
 145 /* Register rw_intr_mask, scope iop_timer_grp, type rw */
 146 #define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0
 147 #define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1
 148 #define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0
 149 #define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1
 150 #define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1
 151 #define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1
 152 #define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2
 153 #define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1
 154 #define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2
 155 #define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3
 156 #define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1
 157 #define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3
 158 #define reg_iop_timer_grp_rw_intr_mask_offset 100
 159
 160 /* Register rw_ack_intr, scope iop_timer_grp, type rw */
 161 #define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0
 162 #define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1
 163 #define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0
 164 #define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1
 165 #define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1
 166 #define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1
 167 #define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2
 168 #define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1
 169 #define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2
 170 #define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3
 171 #define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1
 172 #define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3
 173 #define reg_iop_timer_grp_rw_ack_intr_offset 104
 174
 175 /* Register r_intr, scope iop_timer_grp, type r */
 176 #define reg_iop_timer_grp_r_intr___tmr0___lsb 0
 177 #define reg_iop_timer_grp_r_intr___tmr0___width 1
 178 #define reg_iop_timer_grp_r_intr___tmr0___bit 0
 179 #define reg_iop_timer_grp_r_intr___tmr1___lsb 1
 180 #define reg_iop_timer_grp_r_intr___tmr1___width 1
 181 #define reg_iop_timer_grp_r_intr___tmr1___bit 1
 182 #define reg_iop_timer_grp_r_intr___tmr2___lsb 2
 183 #define reg_iop_timer_grp_r_intr___tmr2___width 1
 184 #define reg_iop_timer_grp_r_intr___tmr2___bit 2
 185 #define reg_iop_timer_grp_r_intr___tmr3___lsb 3
 186 #define reg_iop_timer_grp_r_intr___tmr3___width 1
 187 #define reg_iop_timer_grp_r_intr___tmr3___bit 3
 188 #define reg_iop_timer_grp_r_intr_offset 108
 189
 190 /* Register r_masked_intr, scope iop_timer_grp, type r */
 191 #define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0
 192 #define reg_iop_timer_grp_r_masked_intr___tmr0___width 1
 193 #define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0
 194 #define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1
 195 #define reg_iop_timer_grp_r_masked_intr___tmr1___width 1
 196 #define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1
 197 #define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2
 198 #define reg_iop_timer_grp_r_masked_intr___tmr2___width 1
 199 #define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2
 200 #define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3
 201 #define reg_iop_timer_grp_r_masked_intr___tmr3___width 1
 202 #define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3
 203 #define reg_iop_timer_grp_r_masked_intr_offset 112
 204
 205
 206 /* Constants */
 207 #define regk_iop_timer_grp_clk200                 0x00000000
 208 #define regk_iop_timer_grp_clk_gen                0x00000002
 209 #define regk_iop_timer_grp_complete               0x00000002
 210 #define regk_iop_timer_grp_div_clk200             0x00000001
 211 #define regk_iop_timer_grp_div_clk_gen            0x00000003
 212 #define regk_iop_timer_grp_ext                    0x00000001
 213 #define regk_iop_timer_grp_hi                     0x00000000
 214 #define regk_iop_timer_grp_long_period            0x00000001
 215 #define regk_iop_timer_grp_neg                    0x00000002
 216 #define regk_iop_timer_grp_no                     0x00000000
 217 #define regk_iop_timer_grp_once                   0x00000003
 218 #define regk_iop_timer_grp_pause                  0x00000001
 219 #define regk_iop_timer_grp_pos                    0x00000001
 220 #define regk_iop_timer_grp_pos_neg                0x00000003
 221 #define regk_iop_timer_grp_pulse                  0x00000000
 222 #define regk_iop_timer_grp_r_tmr_cnt_size         0x00000004
 223 #define regk_iop_timer_grp_rs_tmr_cnt_size        0x00000004
 224 #define regk_iop_timer_grp_rw_cfg_default         0x00000002
 225 #define regk_iop_timer_grp_rw_intr_mask_default   0x00000000
 226 #define regk_iop_timer_grp_rw_tmr_cfg_default0    0x00018000
 227 #define regk_iop_timer_grp_rw_tmr_cfg_default1    0x0001a900
 228 #define regk_iop_timer_grp_rw_tmr_cfg_default2    0x0001d200
 229 #define regk_iop_timer_grp_rw_tmr_cfg_default3    0x0001fb00
 230 #define regk_iop_timer_grp_rw_tmr_cfg_size        0x00000004
 231 #define regk_iop_timer_grp_rw_tmr_len_default     0x00000000
 232 #define regk_iop_timer_grp_rw_tmr_len_size        0x00000004
 233 #define regk_iop_timer_grp_short_period           0x00000000
 234 #define regk_iop_timer_grp_stop                   0x00000000
 235 #define regk_iop_timer_grp_tmr                    0x00000004
 236 #define regk_iop_timer_grp_toggle                 0x00000001
 237 #define regk_iop_timer_grp_yes                    0x00000001
 238 #endif /* __iop_timer_grp_defs_asm_h */