arch/cris/include/arch-v32/arch/hwregs/iop/iop_sap_in_defs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __iop_sap_in_defs_h
   3 #define __iop_sap_in_defs_h
   4
   5 /*
   6  * This file is autogenerated from
   7  *   file:           ../../inst/io_proc/rtl/iop_sap_in.r
   8  *     id:           <not found>
   9  *     last modfied: Mon Apr 11 16:08:45 2005
  10  *
  11  *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r
  12  *      id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $
  13  * Any changes here will be lost.
  14  *
  15  * -*- buffer-read-only: t -*-
  16  */
  17 /* Main access macros */
  18 #ifndef REG_RD
  19 #define REG_RD( scope, inst, reg ) \
  20   REG_READ( reg_##scope##_##reg, \
  21             (inst) + REG_RD_ADDR_##scope##_##reg )
  22 #endif
  23
  24 #ifndef REG_WR
  25 #define REG_WR( scope, inst, reg, val ) \
  26   REG_WRITE( reg_##scope##_##reg, \
  27              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  28 #endif
  29
  30 #ifndef REG_RD_VECT
  31 #define REG_RD_VECT( scope, inst, reg, index ) \
  32   REG_READ( reg_##scope##_##reg, \
  33             (inst) + REG_RD_ADDR_##scope##_##reg + \
  34             (index) * STRIDE_##scope##_##reg )
  35 #endif
  36
  37 #ifndef REG_WR_VECT
  38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
  39   REG_WRITE( reg_##scope##_##reg, \
  40              (inst) + REG_WR_ADDR_##scope##_##reg + \
  41              (index) * STRIDE_##scope##_##reg, (val) )
  42 #endif
  43
  44 #ifndef REG_RD_INT
  45 #define REG_RD_INT( scope, inst, reg ) \
  46   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  47 #endif
  48
  49 #ifndef REG_WR_INT
  50 #define REG_WR_INT( scope, inst, reg, val ) \
  51   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  52 #endif
  53
  54 #ifndef REG_RD_INT_VECT
  55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
  56   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  57             (index) * STRIDE_##scope##_##reg )
  58 #endif
  59
  60 #ifndef REG_WR_INT_VECT
  61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  62   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  63              (index) * STRIDE_##scope##_##reg, (val) )
  64 #endif
  65
  66 #ifndef REG_TYPE_CONV
  67 #define REG_TYPE_CONV( type, orgtype, val ) \
  68   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  69 #endif
  70
  71 #ifndef reg_page_size
  72 #define reg_page_size 8192
  73 #endif
  74
  75 #ifndef REG_ADDR
  76 #define REG_ADDR( scope, inst, reg ) \
  77   ( (inst) + REG_RD_ADDR_##scope##_##reg )
  78 #endif
  79
  80 #ifndef REG_ADDR_VECT
  81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  82   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  83     (index) * STRIDE_##scope##_##reg )
  84 #endif
  85
  86 /* C-code for register scope iop_sap_in */
  87
  88 /* Register rw_bus0_sync, scope iop_sap_in, type rw */
  89 typedef struct {
  90   unsigned int byte0_sel     : 2;
  91   unsigned int byte0_ext_src : 3;
  92   unsigned int byte0_edge    : 2;
  93   unsigned int byte0_delay   : 1;
  94   unsigned int byte1_sel     : 2;
  95   unsigned int byte1_ext_src : 3;
  96   unsigned int byte1_edge    : 2;
  97   unsigned int byte1_delay   : 1;
  98   unsigned int byte2_sel     : 2;
  99   unsigned int byte2_ext_src : 3;
 100   unsigned int byte2_edge    : 2;
 101   unsigned int byte2_delay   : 1;
 102   unsigned int byte3_sel     : 2;
 103   unsigned int byte3_ext_src : 3;
 104   unsigned int byte3_edge    : 2;
 105   unsigned int byte3_delay   : 1;
 106 } reg_iop_sap_in_rw_bus0_sync;
 107 #define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0
 108 #define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0
 109
 110 /* Register rw_bus1_sync, scope iop_sap_in, type rw */
 111 typedef struct {
 112   unsigned int byte0_sel     : 2;
 113   unsigned int byte0_ext_src : 3;
 114   unsigned int byte0_edge    : 2;
 115   unsigned int byte0_delay   : 1;
 116   unsigned int byte1_sel     : 2;
 117   unsigned int byte1_ext_src : 3;
 118   unsigned int byte1_edge    : 2;
 119   unsigned int byte1_delay   : 1;
 120   unsigned int byte2_sel     : 2;
 121   unsigned int byte2_ext_src : 3;
 122   unsigned int byte2_edge    : 2;
 123   unsigned int byte2_delay   : 1;
 124   unsigned int byte3_sel     : 2;
 125   unsigned int byte3_ext_src : 3;
 126   unsigned int byte3_edge    : 2;
 127   unsigned int byte3_delay   : 1;
 128 } reg_iop_sap_in_rw_bus1_sync;
 129 #define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4
 130 #define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4
 131
 132 #define STRIDE_iop_sap_in_rw_gio 4
 133 /* Register rw_gio, scope iop_sap_in, type rw */
 134 typedef struct {
 135   unsigned int sync_sel     : 2;
 136   unsigned int sync_ext_src : 3;
 137   unsigned int sync_edge    : 2;
 138   unsigned int delay        : 1;
 139   unsigned int logic        : 2;
 140   unsigned int dummy1       : 22;
 141 } reg_iop_sap_in_rw_gio;
 142 #define REG_RD_ADDR_iop_sap_in_rw_gio 8
 143 #define REG_WR_ADDR_iop_sap_in_rw_gio 8
 144
 145
 146 /* Constants */
 147 enum {
 148   regk_iop_sap_in_and                      = 0x00000002,
 149   regk_iop_sap_in_ext_clk200               = 0x00000003,
 150   regk_iop_sap_in_gio1                     = 0x00000000,
 151   regk_iop_sap_in_gio13                    = 0x00000005,
 152   regk_iop_sap_in_gio18                    = 0x00000003,
 153   regk_iop_sap_in_gio19                    = 0x00000004,
 154   regk_iop_sap_in_gio21                    = 0x00000006,
 155   regk_iop_sap_in_gio23                    = 0x00000005,
 156   regk_iop_sap_in_gio29                    = 0x00000007,
 157   regk_iop_sap_in_gio5                     = 0x00000004,
 158   regk_iop_sap_in_gio6                     = 0x00000001,
 159   regk_iop_sap_in_gio7                     = 0x00000002,
 160   regk_iop_sap_in_inv                      = 0x00000001,
 161   regk_iop_sap_in_neg                      = 0x00000002,
 162   regk_iop_sap_in_no                       = 0x00000000,
 163   regk_iop_sap_in_no_del_ext_clk200        = 0x00000001,
 164   regk_iop_sap_in_none                     = 0x00000000,
 165   regk_iop_sap_in_or                       = 0x00000003,
 166   regk_iop_sap_in_pos                      = 0x00000001,
 167   regk_iop_sap_in_pos_neg                  = 0x00000003,
 168   regk_iop_sap_in_rw_bus0_sync_default     = 0x02020202,
 169   regk_iop_sap_in_rw_bus1_sync_default     = 0x02020202,
 170   regk_iop_sap_in_rw_gio_default           = 0x00000002,
 171   regk_iop_sap_in_rw_gio_size              = 0x00000020,
 172   regk_iop_sap_in_timer_grp0_tmr3          = 0x00000006,
 173   regk_iop_sap_in_timer_grp1_tmr3          = 0x00000004,
 174   regk_iop_sap_in_timer_grp2_tmr3          = 0x00000005,
 175   regk_iop_sap_in_timer_grp3_tmr3          = 0x00000007,
 176   regk_iop_sap_in_tmr_clk200               = 0x00000000,
 177   regk_iop_sap_in_two_clk200               = 0x00000002,
 178   regk_iop_sap_in_yes                      = 0x00000001
 179 };
 180 #endif /* __iop_sap_in_defs_h */