arch/cris/include/arch-v32/arch/hwregs/iop/iop_sw_spu_defs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __iop_sw_spu_defs_h
   3 #define __iop_sw_spu_defs_h
   4
   5 /*
   6  * This file is autogenerated from
   7  *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
   8  *     id:           <not found>
   9  *     last modfied: Mon Apr 11 16:10:19 2005
  10  *
  11  *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_spu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
  12  *      id: $Id: iop_sw_spu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
  13  * Any changes here will be lost.
  14  *
  15  * -*- buffer-read-only: t -*-
  16  */
  17 /* Main access macros */
  18 #ifndef REG_RD
  19 #define REG_RD( scope, inst, reg ) \
  20   REG_READ( reg_##scope##_##reg, \
  21             (inst) + REG_RD_ADDR_##scope##_##reg )
  22 #endif
  23
  24 #ifndef REG_WR
  25 #define REG_WR( scope, inst, reg, val ) \
  26   REG_WRITE( reg_##scope##_##reg, \
  27              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  28 #endif
  29
  30 #ifndef REG_RD_VECT
  31 #define REG_RD_VECT( scope, inst, reg, index ) \
  32   REG_READ( reg_##scope##_##reg, \
  33             (inst) + REG_RD_ADDR_##scope##_##reg + \
  34             (index) * STRIDE_##scope##_##reg )
  35 #endif
  36
  37 #ifndef REG_WR_VECT
  38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
  39   REG_WRITE( reg_##scope##_##reg, \
  40              (inst) + REG_WR_ADDR_##scope##_##reg + \
  41              (index) * STRIDE_##scope##_##reg, (val) )
  42 #endif
  43
  44 #ifndef REG_RD_INT
  45 #define REG_RD_INT( scope, inst, reg ) \
  46   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  47 #endif
  48
  49 #ifndef REG_WR_INT
  50 #define REG_WR_INT( scope, inst, reg, val ) \
  51   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  52 #endif
  53
  54 #ifndef REG_RD_INT_VECT
  55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
  56   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  57             (index) * STRIDE_##scope##_##reg )
  58 #endif
  59
  60 #ifndef REG_WR_INT_VECT
  61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  62   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  63              (index) * STRIDE_##scope##_##reg, (val) )
  64 #endif
  65
  66 #ifndef REG_TYPE_CONV
  67 #define REG_TYPE_CONV( type, orgtype, val ) \
  68   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  69 #endif
  70
  71 #ifndef reg_page_size
  72 #define reg_page_size 8192
  73 #endif
  74
  75 #ifndef REG_ADDR
  76 #define REG_ADDR( scope, inst, reg ) \
  77   ( (inst) + REG_RD_ADDR_##scope##_##reg )
  78 #endif
  79
  80 #ifndef REG_ADDR_VECT
  81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  82   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  83     (index) * STRIDE_##scope##_##reg )
  84 #endif
  85
  86 /* C-code for register scope iop_sw_spu */
  87
  88 /* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
  89 typedef struct {
  90   unsigned int keep_owner  : 1;
  91   unsigned int cmd         : 2;
  92   unsigned int size        : 3;
  93   unsigned int wr_spu0_mem : 1;
  94   unsigned int wr_spu1_mem : 1;
  95   unsigned int dummy1      : 24;
  96 } reg_iop_sw_spu_rw_mc_ctrl;
  97 #define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 0
  98 #define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 0
  99
 100 /* Register rw_mc_data, scope iop_sw_spu, type rw */
 101 typedef struct {
 102   unsigned int val : 32;
 103 } reg_iop_sw_spu_rw_mc_data;
 104 #define REG_RD_ADDR_iop_sw_spu_rw_mc_data 4
 105 #define REG_WR_ADDR_iop_sw_spu_rw_mc_data 4
 106
 107 /* Register rw_mc_addr, scope iop_sw_spu, type rw */
 108 typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
 109 #define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 8
 110 #define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 8
 111
 112 /* Register rs_mc_data, scope iop_sw_spu, type rs */
 113 typedef unsigned int reg_iop_sw_spu_rs_mc_data;
 114 #define REG_RD_ADDR_iop_sw_spu_rs_mc_data 12
 115
 116 /* Register r_mc_data, scope iop_sw_spu, type r */
 117 typedef unsigned int reg_iop_sw_spu_r_mc_data;
 118 #define REG_RD_ADDR_iop_sw_spu_r_mc_data 16
 119
 120 /* Register r_mc_stat, scope iop_sw_spu, type r */
 121 typedef struct {
 122   unsigned int busy_cpu      : 1;
 123   unsigned int busy_mpu      : 1;
 124   unsigned int busy_spu0     : 1;
 125   unsigned int busy_spu1     : 1;
 126   unsigned int owned_by_cpu  : 1;
 127   unsigned int owned_by_mpu  : 1;
 128   unsigned int owned_by_spu0 : 1;
 129   unsigned int owned_by_spu1 : 1;
 130   unsigned int dummy1        : 24;
 131 } reg_iop_sw_spu_r_mc_stat;
 132 #define REG_RD_ADDR_iop_sw_spu_r_mc_stat 20
 133
 134 /* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
 135 typedef struct {
 136   unsigned int byte0 : 8;
 137   unsigned int byte1 : 8;
 138   unsigned int byte2 : 8;
 139   unsigned int byte3 : 8;
 140 } reg_iop_sw_spu_rw_bus0_clr_mask;
 141 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
 142 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask 24
 143
 144 /* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
 145 typedef struct {
 146   unsigned int byte0 : 8;
 147   unsigned int byte1 : 8;
 148   unsigned int byte2 : 8;
 149   unsigned int byte3 : 8;
 150 } reg_iop_sw_spu_rw_bus0_set_mask;
 151 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask 28
 152 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask 28
 153
 154 /* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
 155 typedef struct {
 156   unsigned int byte0 : 1;
 157   unsigned int byte1 : 1;
 158   unsigned int byte2 : 1;
 159   unsigned int byte3 : 1;
 160   unsigned int dummy1 : 28;
 161 } reg_iop_sw_spu_rw_bus0_oe_clr_mask;
 162 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
 163 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask 32
 164
 165 /* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
 166 typedef struct {
 167   unsigned int byte0 : 1;
 168   unsigned int byte1 : 1;
 169   unsigned int byte2 : 1;
 170   unsigned int byte3 : 1;
 171   unsigned int dummy1 : 28;
 172 } reg_iop_sw_spu_rw_bus0_oe_set_mask;
 173 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
 174 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask 36
 175
 176 /* Register r_bus0_in, scope iop_sw_spu, type r */
 177 typedef unsigned int reg_iop_sw_spu_r_bus0_in;
 178 #define REG_RD_ADDR_iop_sw_spu_r_bus0_in 40
 179
 180 /* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
 181 typedef struct {
 182   unsigned int byte0 : 8;
 183   unsigned int byte1 : 8;
 184   unsigned int byte2 : 8;
 185   unsigned int byte3 : 8;
 186 } reg_iop_sw_spu_rw_bus1_clr_mask;
 187 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
 188 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask 44
 189
 190 /* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
 191 typedef struct {
 192   unsigned int byte0 : 8;
 193   unsigned int byte1 : 8;
 194   unsigned int byte2 : 8;
 195   unsigned int byte3 : 8;
 196 } reg_iop_sw_spu_rw_bus1_set_mask;
 197 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask 48
 198 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask 48
 199
 200 /* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
 201 typedef struct {
 202   unsigned int byte0 : 1;
 203   unsigned int byte1 : 1;
 204   unsigned int byte2 : 1;
 205   unsigned int byte3 : 1;
 206   unsigned int dummy1 : 28;
 207 } reg_iop_sw_spu_rw_bus1_oe_clr_mask;
 208 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
 209 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask 52
 210
 211 /* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
 212 typedef struct {
 213   unsigned int byte0 : 1;
 214   unsigned int byte1 : 1;
 215   unsigned int byte2 : 1;
 216   unsigned int byte3 : 1;
 217   unsigned int dummy1 : 28;
 218 } reg_iop_sw_spu_rw_bus1_oe_set_mask;
 219 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
 220 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask 56
 221
 222 /* Register r_bus1_in, scope iop_sw_spu, type r */
 223 typedef unsigned int reg_iop_sw_spu_r_bus1_in;
 224 #define REG_RD_ADDR_iop_sw_spu_r_bus1_in 60
 225
 226 /* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
 227 typedef struct {
 228   unsigned int val : 32;
 229 } reg_iop_sw_spu_rw_gio_clr_mask;
 230 #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 64
 231 #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 64
 232
 233 /* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
 234 typedef struct {
 235   unsigned int val : 32;
 236 } reg_iop_sw_spu_rw_gio_set_mask;
 237 #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 68
 238 #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 68
 239
 240 /* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
 241 typedef struct {
 242   unsigned int val : 32;
 243 } reg_iop_sw_spu_rw_gio_oe_clr_mask;
 244 #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
 245 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 72
 246
 247 /* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
 248 typedef struct {
 249   unsigned int val : 32;
 250 } reg_iop_sw_spu_rw_gio_oe_set_mask;
 251 #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
 252 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 76
 253
 254 /* Register r_gio_in, scope iop_sw_spu, type r */
 255 typedef unsigned int reg_iop_sw_spu_r_gio_in;
 256 #define REG_RD_ADDR_iop_sw_spu_r_gio_in 80
 257
 258 /* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
 259 typedef struct {
 260   unsigned int byte0 : 8;
 261   unsigned int byte1 : 8;
 262   unsigned int dummy1 : 16;
 263 } reg_iop_sw_spu_rw_bus0_clr_mask_lo;
 264 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
 265 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo 84
 266
 267 /* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
 268 typedef struct {
 269   unsigned int byte2 : 8;
 270   unsigned int byte3 : 8;
 271   unsigned int dummy1 : 16;
 272 } reg_iop_sw_spu_rw_bus0_clr_mask_hi;
 273 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
 274 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi 88
 275
 276 /* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
 277 typedef struct {
 278   unsigned int byte0 : 8;
 279   unsigned int byte1 : 8;
 280   unsigned int dummy1 : 16;
 281 } reg_iop_sw_spu_rw_bus0_set_mask_lo;
 282 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
 283 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo 92
 284
 285 /* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
 286 typedef struct {
 287   unsigned int byte2 : 8;
 288   unsigned int byte3 : 8;
 289   unsigned int dummy1 : 16;
 290 } reg_iop_sw_spu_rw_bus0_set_mask_hi;
 291 #define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
 292 #define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi 96
 293
 294 /* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
 295 typedef struct {
 296   unsigned int byte0 : 8;
 297   unsigned int byte1 : 8;
 298   unsigned int dummy1 : 16;
 299 } reg_iop_sw_spu_rw_bus1_clr_mask_lo;
 300 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
 301 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo 100
 302
 303 /* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
 304 typedef struct {
 305   unsigned int byte2 : 8;
 306   unsigned int byte3 : 8;
 307   unsigned int dummy1 : 16;
 308 } reg_iop_sw_spu_rw_bus1_clr_mask_hi;
 309 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
 310 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi 104
 311
 312 /* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
 313 typedef struct {
 314   unsigned int byte0 : 8;
 315   unsigned int byte1 : 8;
 316   unsigned int dummy1 : 16;
 317 } reg_iop_sw_spu_rw_bus1_set_mask_lo;
 318 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
 319 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo 108
 320
 321 /* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
 322 typedef struct {
 323   unsigned int byte2 : 8;
 324   unsigned int byte3 : 8;
 325   unsigned int dummy1 : 16;
 326 } reg_iop_sw_spu_rw_bus1_set_mask_hi;
 327 #define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
 328 #define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi 112
 329
 330 /* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
 331 typedef struct {
 332   unsigned int val : 16;
 333   unsigned int dummy1 : 16;
 334 } reg_iop_sw_spu_rw_gio_clr_mask_lo;
 335 #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
 336 #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 116
 337
 338 /* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
 339 typedef struct {
 340   unsigned int val : 16;
 341   unsigned int dummy1 : 16;
 342 } reg_iop_sw_spu_rw_gio_clr_mask_hi;
 343 #define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
 344 #define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 120
 345
 346 /* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
 347 typedef struct {
 348   unsigned int val : 16;
 349   unsigned int dummy1 : 16;
 350 } reg_iop_sw_spu_rw_gio_set_mask_lo;
 351 #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
 352 #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 124
 353
 354 /* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
 355 typedef struct {
 356   unsigned int val : 16;
 357   unsigned int dummy1 : 16;
 358 } reg_iop_sw_spu_rw_gio_set_mask_hi;
 359 #define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
 360 #define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 128
 361
 362 /* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
 363 typedef struct {
 364   unsigned int val : 16;
 365   unsigned int dummy1 : 16;
 366 } reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
 367 #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
 368 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 132
 369
 370 /* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
 371 typedef struct {
 372   unsigned int val : 16;
 373   unsigned int dummy1 : 16;
 374 } reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
 375 #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
 376 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 136
 377
 378 /* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
 379 typedef struct {
 380   unsigned int val : 16;
 381   unsigned int dummy1 : 16;
 382 } reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
 383 #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
 384 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 140
 385
 386 /* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
 387 typedef struct {
 388   unsigned int val : 16;
 389   unsigned int dummy1 : 16;
 390 } reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
 391 #define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
 392 #define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 144
 393
 394 /* Register rw_cpu_intr, scope iop_sw_spu, type rw */
 395 typedef struct {
 396   unsigned int intr0  : 1;
 397   unsigned int intr1  : 1;
 398   unsigned int intr2  : 1;
 399   unsigned int intr3  : 1;
 400   unsigned int intr4  : 1;
 401   unsigned int intr5  : 1;
 402   unsigned int intr6  : 1;
 403   unsigned int intr7  : 1;
 404   unsigned int intr8  : 1;
 405   unsigned int intr9  : 1;
 406   unsigned int intr10 : 1;
 407   unsigned int intr11 : 1;
 408   unsigned int intr12 : 1;
 409   unsigned int intr13 : 1;
 410   unsigned int intr14 : 1;
 411   unsigned int intr15 : 1;
 412   unsigned int dummy1 : 16;
 413 } reg_iop_sw_spu_rw_cpu_intr;
 414 #define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 148
 415 #define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 148
 416
 417 /* Register r_cpu_intr, scope iop_sw_spu, type r */
 418 typedef struct {
 419   unsigned int intr0  : 1;
 420   unsigned int intr1  : 1;
 421   unsigned int intr2  : 1;
 422   unsigned int intr3  : 1;
 423   unsigned int intr4  : 1;
 424   unsigned int intr5  : 1;
 425   unsigned int intr6  : 1;
 426   unsigned int intr7  : 1;
 427   unsigned int intr8  : 1;
 428   unsigned int intr9  : 1;
 429   unsigned int intr10 : 1;
 430   unsigned int intr11 : 1;
 431   unsigned int intr12 : 1;
 432   unsigned int intr13 : 1;
 433   unsigned int intr14 : 1;
 434   unsigned int intr15 : 1;
 435   unsigned int dummy1 : 16;
 436 } reg_iop_sw_spu_r_cpu_intr;
 437 #define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 152
 438
 439 /* Register r_hw_intr, scope iop_sw_spu, type r */
 440 typedef struct {
 441   unsigned int trigger_grp0    : 1;
 442   unsigned int trigger_grp1    : 1;
 443   unsigned int trigger_grp2    : 1;
 444   unsigned int trigger_grp3    : 1;
 445   unsigned int trigger_grp4    : 1;
 446   unsigned int trigger_grp5    : 1;
 447   unsigned int trigger_grp6    : 1;
 448   unsigned int trigger_grp7    : 1;
 449   unsigned int timer_grp0      : 1;
 450   unsigned int timer_grp1      : 1;
 451   unsigned int timer_grp2      : 1;
 452   unsigned int timer_grp3      : 1;
 453   unsigned int fifo_out0       : 1;
 454   unsigned int fifo_out0_extra : 1;
 455   unsigned int fifo_in0        : 1;
 456   unsigned int fifo_in0_extra  : 1;
 457   unsigned int fifo_out1       : 1;
 458   unsigned int fifo_out1_extra : 1;
 459   unsigned int fifo_in1        : 1;
 460   unsigned int fifo_in1_extra  : 1;
 461   unsigned int dmc_out0        : 1;
 462   unsigned int dmc_in0         : 1;
 463   unsigned int dmc_out1        : 1;
 464   unsigned int dmc_in1         : 1;
 465   unsigned int dummy1          : 8;
 466 } reg_iop_sw_spu_r_hw_intr;
 467 #define REG_RD_ADDR_iop_sw_spu_r_hw_intr 156
 468
 469 /* Register rw_mpu_intr, scope iop_sw_spu, type rw */
 470 typedef struct {
 471   unsigned int intr0  : 1;
 472   unsigned int intr1  : 1;
 473   unsigned int intr2  : 1;
 474   unsigned int intr3  : 1;
 475   unsigned int intr4  : 1;
 476   unsigned int intr5  : 1;
 477   unsigned int intr6  : 1;
 478   unsigned int intr7  : 1;
 479   unsigned int intr8  : 1;
 480   unsigned int intr9  : 1;
 481   unsigned int intr10 : 1;
 482   unsigned int intr11 : 1;
 483   unsigned int intr12 : 1;
 484   unsigned int intr13 : 1;
 485   unsigned int intr14 : 1;
 486   unsigned int intr15 : 1;
 487   unsigned int dummy1 : 16;
 488 } reg_iop_sw_spu_rw_mpu_intr;
 489 #define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 160
 490 #define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 160
 491
 492 /* Register r_mpu_intr, scope iop_sw_spu, type r */
 493 typedef struct {
 494   unsigned int intr0            : 1;
 495   unsigned int intr1            : 1;
 496   unsigned int intr2            : 1;
 497   unsigned int intr3            : 1;
 498   unsigned int intr4            : 1;
 499   unsigned int intr5            : 1;
 500   unsigned int intr6            : 1;
 501   unsigned int intr7            : 1;
 502   unsigned int intr8            : 1;
 503   unsigned int intr9            : 1;
 504   unsigned int intr10           : 1;
 505   unsigned int intr11           : 1;
 506   unsigned int intr12           : 1;
 507   unsigned int intr13           : 1;
 508   unsigned int intr14           : 1;
 509   unsigned int intr15           : 1;
 510   unsigned int other_spu_intr0  : 1;
 511   unsigned int other_spu_intr1  : 1;
 512   unsigned int other_spu_intr2  : 1;
 513   unsigned int other_spu_intr3  : 1;
 514   unsigned int other_spu_intr4  : 1;
 515   unsigned int other_spu_intr5  : 1;
 516   unsigned int other_spu_intr6  : 1;
 517   unsigned int other_spu_intr7  : 1;
 518   unsigned int other_spu_intr8  : 1;
 519   unsigned int other_spu_intr9  : 1;
 520   unsigned int other_spu_intr10 : 1;
 521   unsigned int other_spu_intr11 : 1;
 522   unsigned int other_spu_intr12 : 1;
 523   unsigned int other_spu_intr13 : 1;
 524   unsigned int other_spu_intr14 : 1;
 525   unsigned int other_spu_intr15 : 1;
 526 } reg_iop_sw_spu_r_mpu_intr;
 527 #define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 164
 528
 529
 530 /* Constants */
 531 enum {
 532   regk_iop_sw_spu_copy                     = 0x00000000,
 533   regk_iop_sw_spu_no                       = 0x00000000,
 534   regk_iop_sw_spu_nop                      = 0x00000000,
 535   regk_iop_sw_spu_rd                       = 0x00000002,
 536   regk_iop_sw_spu_reg_copy                 = 0x00000001,
 537   regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000,
 538   regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000,
 539   regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000,
 540   regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000,
 541   regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000,
 542   regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000,
 543   regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000,
 544   regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000,
 545   regk_iop_sw_spu_rw_gio_clr_mask_default  = 0x00000000,
 546   regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
 547   regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
 548   regk_iop_sw_spu_rw_gio_set_mask_default  = 0x00000000,
 549   regk_iop_sw_spu_set                      = 0x00000001,
 550   regk_iop_sw_spu_wr                       = 0x00000003,
 551   regk_iop_sw_spu_yes                      = 0x00000001
 552 };
 553 #endif /* __iop_sw_spu_defs_h */