arch/cris/include/arch-v32/mach-a3/mach/hwregs/gio_defs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __gio_defs_h
   3 #define __gio_defs_h
   4
   5 /*
   6  * This file is autogenerated from
   7  *   file:           gio.r
   8  *
   9  *   by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r
  10  * Any changes here will be lost.
  11  *
  12  * -*- buffer-read-only: t -*-
  13  */
  14 /* Main access macros */
  15 #ifndef REG_RD
  16 #define REG_RD( scope, inst, reg ) \
  17   REG_READ( reg_##scope##_##reg, \
  18             (inst) + REG_RD_ADDR_##scope##_##reg )
  19 #endif
  20
  21 #ifndef REG_WR
  22 #define REG_WR( scope, inst, reg, val ) \
  23   REG_WRITE( reg_##scope##_##reg, \
  24              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  25 #endif
  26
  27 #ifndef REG_RD_VECT
  28 #define REG_RD_VECT( scope, inst, reg, index ) \
  29   REG_READ( reg_##scope##_##reg, \
  30             (inst) + REG_RD_ADDR_##scope##_##reg + \
  31             (index) * STRIDE_##scope##_##reg )
  32 #endif
  33
  34 #ifndef REG_WR_VECT
  35 #define REG_WR_VECT( scope, inst, reg, index, val ) \
  36   REG_WRITE( reg_##scope##_##reg, \
  37              (inst) + REG_WR_ADDR_##scope##_##reg + \
  38              (index) * STRIDE_##scope##_##reg, (val) )
  39 #endif
  40
  41 #ifndef REG_RD_INT
  42 #define REG_RD_INT( scope, inst, reg ) \
  43   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  44 #endif
  45
  46 #ifndef REG_WR_INT
  47 #define REG_WR_INT( scope, inst, reg, val ) \
  48   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  49 #endif
  50
  51 #ifndef REG_RD_INT_VECT
  52 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
  53   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  54             (index) * STRIDE_##scope##_##reg )
  55 #endif
  56
  57 #ifndef REG_WR_INT_VECT
  58 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  59   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  60              (index) * STRIDE_##scope##_##reg, (val) )
  61 #endif
  62
  63 #ifndef REG_TYPE_CONV
  64 #define REG_TYPE_CONV( type, orgtype, val ) \
  65   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  66 #endif
  67
  68 #ifndef reg_page_size
  69 #define reg_page_size 8192
  70 #endif
  71
  72 #ifndef REG_ADDR
  73 #define REG_ADDR( scope, inst, reg ) \
  74   ( (inst) + REG_RD_ADDR_##scope##_##reg )
  75 #endif
  76
  77 #ifndef REG_ADDR_VECT
  78 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  79   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  80     (index) * STRIDE_##scope##_##reg )
  81 #endif
  82
  83 /* C-code for register scope gio */
  84
  85 /* Register r_pa_din, scope gio, type r */
  86 typedef struct {
  87   unsigned int data : 32;
  88 } reg_gio_r_pa_din;
  89 #define REG_RD_ADDR_gio_r_pa_din 0
  90
  91 /* Register rw_pa_dout, scope gio, type rw */
  92 typedef struct {
  93   unsigned int data : 32;
  94 } reg_gio_rw_pa_dout;
  95 #define REG_RD_ADDR_gio_rw_pa_dout 4
  96 #define REG_WR_ADDR_gio_rw_pa_dout 4
  97
  98 /* Register rw_pa_oe, scope gio, type rw */
  99 typedef struct {
 100   unsigned int oe : 32;
 101 } reg_gio_rw_pa_oe;
 102 #define REG_RD_ADDR_gio_rw_pa_oe 8
 103 #define REG_WR_ADDR_gio_rw_pa_oe 8
 104
 105 /* Register rw_pa_byte0_dout, scope gio, type rw */
 106 typedef struct {
 107   unsigned int data : 8;
 108   unsigned int dummy1 : 24;
 109 } reg_gio_rw_pa_byte0_dout;
 110 #define REG_RD_ADDR_gio_rw_pa_byte0_dout 12
 111 #define REG_WR_ADDR_gio_rw_pa_byte0_dout 12
 112
 113 /* Register rw_pa_byte0_oe, scope gio, type rw */
 114 typedef struct {
 115   unsigned int oe : 8;
 116   unsigned int dummy1 : 24;
 117 } reg_gio_rw_pa_byte0_oe;
 118 #define REG_RD_ADDR_gio_rw_pa_byte0_oe 16
 119 #define REG_WR_ADDR_gio_rw_pa_byte0_oe 16
 120
 121 /* Register rw_pa_byte1_dout, scope gio, type rw */
 122 typedef struct {
 123   unsigned int data : 8;
 124   unsigned int dummy1 : 24;
 125 } reg_gio_rw_pa_byte1_dout;
 126 #define REG_RD_ADDR_gio_rw_pa_byte1_dout 20
 127 #define REG_WR_ADDR_gio_rw_pa_byte1_dout 20
 128
 129 /* Register rw_pa_byte1_oe, scope gio, type rw */
 130 typedef struct {
 131   unsigned int oe : 8;
 132   unsigned int dummy1 : 24;
 133 } reg_gio_rw_pa_byte1_oe;
 134 #define REG_RD_ADDR_gio_rw_pa_byte1_oe 24
 135 #define REG_WR_ADDR_gio_rw_pa_byte1_oe 24
 136
 137 /* Register rw_pa_byte2_dout, scope gio, type rw */
 138 typedef struct {
 139   unsigned int data : 8;
 140   unsigned int dummy1 : 24;
 141 } reg_gio_rw_pa_byte2_dout;
 142 #define REG_RD_ADDR_gio_rw_pa_byte2_dout 28
 143 #define REG_WR_ADDR_gio_rw_pa_byte2_dout 28
 144
 145 /* Register rw_pa_byte2_oe, scope gio, type rw */
 146 typedef struct {
 147   unsigned int oe : 8;
 148   unsigned int dummy1 : 24;
 149 } reg_gio_rw_pa_byte2_oe;
 150 #define REG_RD_ADDR_gio_rw_pa_byte2_oe 32
 151 #define REG_WR_ADDR_gio_rw_pa_byte2_oe 32
 152
 153 /* Register rw_pa_byte3_dout, scope gio, type rw */
 154 typedef struct {
 155   unsigned int data : 8;
 156   unsigned int dummy1 : 24;
 157 } reg_gio_rw_pa_byte3_dout;
 158 #define REG_RD_ADDR_gio_rw_pa_byte3_dout 36
 159 #define REG_WR_ADDR_gio_rw_pa_byte3_dout 36
 160
 161 /* Register rw_pa_byte3_oe, scope gio, type rw */
 162 typedef struct {
 163   unsigned int oe : 8;
 164   unsigned int dummy1 : 24;
 165 } reg_gio_rw_pa_byte3_oe;
 166 #define REG_RD_ADDR_gio_rw_pa_byte3_oe 40
 167 #define REG_WR_ADDR_gio_rw_pa_byte3_oe 40
 168
 169 /* Register r_pb_din, scope gio, type r */
 170 typedef struct {
 171   unsigned int data : 32;
 172 } reg_gio_r_pb_din;
 173 #define REG_RD_ADDR_gio_r_pb_din 44
 174
 175 /* Register rw_pb_dout, scope gio, type rw */
 176 typedef struct {
 177   unsigned int data : 32;
 178 } reg_gio_rw_pb_dout;
 179 #define REG_RD_ADDR_gio_rw_pb_dout 48
 180 #define REG_WR_ADDR_gio_rw_pb_dout 48
 181
 182 /* Register rw_pb_oe, scope gio, type rw */
 183 typedef struct {
 184   unsigned int oe : 32;
 185 } reg_gio_rw_pb_oe;
 186 #define REG_RD_ADDR_gio_rw_pb_oe 52
 187 #define REG_WR_ADDR_gio_rw_pb_oe 52
 188
 189 /* Register rw_pb_byte0_dout, scope gio, type rw */
 190 typedef struct {
 191   unsigned int data : 8;
 192   unsigned int dummy1 : 24;
 193 } reg_gio_rw_pb_byte0_dout;
 194 #define REG_RD_ADDR_gio_rw_pb_byte0_dout 56
 195 #define REG_WR_ADDR_gio_rw_pb_byte0_dout 56
 196
 197 /* Register rw_pb_byte0_oe, scope gio, type rw */
 198 typedef struct {
 199   unsigned int oe : 8;
 200   unsigned int dummy1 : 24;
 201 } reg_gio_rw_pb_byte0_oe;
 202 #define REG_RD_ADDR_gio_rw_pb_byte0_oe 60
 203 #define REG_WR_ADDR_gio_rw_pb_byte0_oe 60
 204
 205 /* Register rw_pb_byte1_dout, scope gio, type rw */
 206 typedef struct {
 207   unsigned int data : 8;
 208   unsigned int dummy1 : 24;
 209 } reg_gio_rw_pb_byte1_dout;
 210 #define REG_RD_ADDR_gio_rw_pb_byte1_dout 64
 211 #define REG_WR_ADDR_gio_rw_pb_byte1_dout 64
 212
 213 /* Register rw_pb_byte1_oe, scope gio, type rw */
 214 typedef struct {
 215   unsigned int oe : 8;
 216   unsigned int dummy1 : 24;
 217 } reg_gio_rw_pb_byte1_oe;
 218 #define REG_RD_ADDR_gio_rw_pb_byte1_oe 68
 219 #define REG_WR_ADDR_gio_rw_pb_byte1_oe 68
 220
 221 /* Register rw_pb_byte2_dout, scope gio, type rw */
 222 typedef struct {
 223   unsigned int data : 8;
 224   unsigned int dummy1 : 24;
 225 } reg_gio_rw_pb_byte2_dout;
 226 #define REG_RD_ADDR_gio_rw_pb_byte2_dout 72
 227 #define REG_WR_ADDR_gio_rw_pb_byte2_dout 72
 228
 229 /* Register rw_pb_byte2_oe, scope gio, type rw */
 230 typedef struct {
 231   unsigned int oe : 8;
 232   unsigned int dummy1 : 24;
 233 } reg_gio_rw_pb_byte2_oe;
 234 #define REG_RD_ADDR_gio_rw_pb_byte2_oe 76
 235 #define REG_WR_ADDR_gio_rw_pb_byte2_oe 76
 236
 237 /* Register rw_pb_byte3_dout, scope gio, type rw */
 238 typedef struct {
 239   unsigned int data : 8;
 240   unsigned int dummy1 : 24;
 241 } reg_gio_rw_pb_byte3_dout;
 242 #define REG_RD_ADDR_gio_rw_pb_byte3_dout 80
 243 #define REG_WR_ADDR_gio_rw_pb_byte3_dout 80
 244
 245 /* Register rw_pb_byte3_oe, scope gio, type rw */
 246 typedef struct {
 247   unsigned int oe : 8;
 248   unsigned int dummy1 : 24;
 249 } reg_gio_rw_pb_byte3_oe;
 250 #define REG_RD_ADDR_gio_rw_pb_byte3_oe 84
 251 #define REG_WR_ADDR_gio_rw_pb_byte3_oe 84
 252
 253 /* Register r_pc_din, scope gio, type r */
 254 typedef struct {
 255   unsigned int data : 16;
 256   unsigned int dummy1 : 16;
 257 } reg_gio_r_pc_din;
 258 #define REG_RD_ADDR_gio_r_pc_din 88
 259
 260 /* Register rw_pc_dout, scope gio, type rw */
 261 typedef struct {
 262   unsigned int data : 16;
 263   unsigned int dummy1 : 16;
 264 } reg_gio_rw_pc_dout;
 265 #define REG_RD_ADDR_gio_rw_pc_dout 92
 266 #define REG_WR_ADDR_gio_rw_pc_dout 92
 267
 268 /* Register rw_pc_oe, scope gio, type rw */
 269 typedef struct {
 270   unsigned int oe : 16;
 271   unsigned int dummy1 : 16;
 272 } reg_gio_rw_pc_oe;
 273 #define REG_RD_ADDR_gio_rw_pc_oe 96
 274 #define REG_WR_ADDR_gio_rw_pc_oe 96
 275
 276 /* Register rw_pc_byte0_dout, scope gio, type rw */
 277 typedef struct {
 278   unsigned int data : 8;
 279   unsigned int dummy1 : 24;
 280 } reg_gio_rw_pc_byte0_dout;
 281 #define REG_RD_ADDR_gio_rw_pc_byte0_dout 100
 282 #define REG_WR_ADDR_gio_rw_pc_byte0_dout 100
 283
 284 /* Register rw_pc_byte0_oe, scope gio, type rw */
 285 typedef struct {
 286   unsigned int oe : 8;
 287   unsigned int dummy1 : 24;
 288 } reg_gio_rw_pc_byte0_oe;
 289 #define REG_RD_ADDR_gio_rw_pc_byte0_oe 104
 290 #define REG_WR_ADDR_gio_rw_pc_byte0_oe 104
 291
 292 /* Register rw_pc_byte1_dout, scope gio, type rw */
 293 typedef struct {
 294   unsigned int data : 8;
 295   unsigned int dummy1 : 24;
 296 } reg_gio_rw_pc_byte1_dout;
 297 #define REG_RD_ADDR_gio_rw_pc_byte1_dout 108
 298 #define REG_WR_ADDR_gio_rw_pc_byte1_dout 108
 299
 300 /* Register rw_pc_byte1_oe, scope gio, type rw */
 301 typedef struct {
 302   unsigned int oe : 8;
 303   unsigned int dummy1 : 24;
 304 } reg_gio_rw_pc_byte1_oe;
 305 #define REG_RD_ADDR_gio_rw_pc_byte1_oe 112
 306 #define REG_WR_ADDR_gio_rw_pc_byte1_oe 112
 307
 308 /* Register r_pd_din, scope gio, type r */
 309 typedef struct {
 310   unsigned int data : 32;
 311 } reg_gio_r_pd_din;
 312 #define REG_RD_ADDR_gio_r_pd_din 116
 313
 314 /* Register rw_intr_cfg, scope gio, type rw */
 315 typedef struct {
 316   unsigned int intr0 : 3;
 317   unsigned int intr1 : 3;
 318   unsigned int intr2 : 3;
 319   unsigned int intr3 : 3;
 320   unsigned int intr4 : 3;
 321   unsigned int intr5 : 3;
 322   unsigned int intr6 : 3;
 323   unsigned int intr7 : 3;
 324   unsigned int dummy1 : 8;
 325 } reg_gio_rw_intr_cfg;
 326 #define REG_RD_ADDR_gio_rw_intr_cfg 120
 327 #define REG_WR_ADDR_gio_rw_intr_cfg 120
 328
 329 /* Register rw_intr_pins, scope gio, type rw */
 330 typedef struct {
 331   unsigned int intr0 : 4;
 332   unsigned int intr1 : 4;
 333   unsigned int intr2 : 4;
 334   unsigned int intr3 : 4;
 335   unsigned int intr4 : 4;
 336   unsigned int intr5 : 4;
 337   unsigned int intr6 : 4;
 338   unsigned int intr7 : 4;
 339 } reg_gio_rw_intr_pins;
 340 #define REG_RD_ADDR_gio_rw_intr_pins 124
 341 #define REG_WR_ADDR_gio_rw_intr_pins 124
 342
 343 /* Register rw_intr_mask, scope gio, type rw */
 344 typedef struct {
 345   unsigned int intr0     : 1;
 346   unsigned int intr1     : 1;
 347   unsigned int intr2     : 1;
 348   unsigned int intr3     : 1;
 349   unsigned int intr4     : 1;
 350   unsigned int intr5     : 1;
 351   unsigned int intr6     : 1;
 352   unsigned int intr7     : 1;
 353   unsigned int i2c0_done : 1;
 354   unsigned int i2c1_done : 1;
 355   unsigned int dummy1    : 22;
 356 } reg_gio_rw_intr_mask;
 357 #define REG_RD_ADDR_gio_rw_intr_mask 128
 358 #define REG_WR_ADDR_gio_rw_intr_mask 128
 359
 360 /* Register rw_ack_intr, scope gio, type rw */
 361 typedef struct {
 362   unsigned int intr0     : 1;
 363   unsigned int intr1     : 1;
 364   unsigned int intr2     : 1;
 365   unsigned int intr3     : 1;
 366   unsigned int intr4     : 1;
 367   unsigned int intr5     : 1;
 368   unsigned int intr6     : 1;
 369   unsigned int intr7     : 1;
 370   unsigned int i2c0_done : 1;
 371   unsigned int i2c1_done : 1;
 372   unsigned int dummy1    : 22;
 373 } reg_gio_rw_ack_intr;
 374 #define REG_RD_ADDR_gio_rw_ack_intr 132
 375 #define REG_WR_ADDR_gio_rw_ack_intr 132
 376
 377 /* Register r_intr, scope gio, type r */
 378 typedef struct {
 379   unsigned int intr0     : 1;
 380   unsigned int intr1     : 1;
 381   unsigned int intr2     : 1;
 382   unsigned int intr3     : 1;
 383   unsigned int intr4     : 1;
 384   unsigned int intr5     : 1;
 385   unsigned int intr6     : 1;
 386   unsigned int intr7     : 1;
 387   unsigned int i2c0_done : 1;
 388   unsigned int i2c1_done : 1;
 389   unsigned int dummy1    : 22;
 390 } reg_gio_r_intr;
 391 #define REG_RD_ADDR_gio_r_intr 136
 392
 393 /* Register r_masked_intr, scope gio, type r */
 394 typedef struct {
 395   unsigned int intr0     : 1;
 396   unsigned int intr1     : 1;
 397   unsigned int intr2     : 1;
 398   unsigned int intr3     : 1;
 399   unsigned int intr4     : 1;
 400   unsigned int intr5     : 1;
 401   unsigned int intr6     : 1;
 402   unsigned int intr7     : 1;
 403   unsigned int i2c0_done : 1;
 404   unsigned int i2c1_done : 1;
 405   unsigned int dummy1    : 22;
 406 } reg_gio_r_masked_intr;
 407 #define REG_RD_ADDR_gio_r_masked_intr 140
 408
 409 /* Register rw_i2c0_start, scope gio, type rw */
 410 typedef struct {
 411   unsigned int run : 1;
 412   unsigned int dummy1 : 31;
 413 } reg_gio_rw_i2c0_start;
 414 #define REG_RD_ADDR_gio_rw_i2c0_start 144
 415 #define REG_WR_ADDR_gio_rw_i2c0_start 144
 416
 417 /* Register rw_i2c0_cfg, scope gio, type rw */
 418 typedef struct {
 419   unsigned int en        : 1;
 420   unsigned int bit_order : 1;
 421   unsigned int scl_io    : 1;
 422   unsigned int scl_inv   : 1;
 423   unsigned int sda_io    : 1;
 424   unsigned int sda_idle  : 1;
 425   unsigned int dummy1    : 26;
 426 } reg_gio_rw_i2c0_cfg;
 427 #define REG_RD_ADDR_gio_rw_i2c0_cfg 148
 428 #define REG_WR_ADDR_gio_rw_i2c0_cfg 148
 429
 430 /* Register rw_i2c0_ctrl, scope gio, type rw */
 431 typedef struct {
 432   unsigned int trf_bits    : 6;
 433   unsigned int switch_dir  : 6;
 434   unsigned int extra_start : 3;
 435   unsigned int early_end   : 1;
 436   unsigned int start_stop  : 1;
 437   unsigned int ack_dir0    : 1;
 438   unsigned int ack_dir1    : 1;
 439   unsigned int ack_dir2    : 1;
 440   unsigned int ack_dir3    : 1;
 441   unsigned int ack_dir4    : 1;
 442   unsigned int ack_dir5    : 1;
 443   unsigned int ack_bit     : 1;
 444   unsigned int start_bit   : 1;
 445   unsigned int freq        : 2;
 446   unsigned int dummy1      : 5;
 447 } reg_gio_rw_i2c0_ctrl;
 448 #define REG_RD_ADDR_gio_rw_i2c0_ctrl 152
 449 #define REG_WR_ADDR_gio_rw_i2c0_ctrl 152
 450
 451 /* Register rw_i2c0_data, scope gio, type rw */
 452 typedef struct {
 453   unsigned int data0 : 8;
 454   unsigned int data1 : 8;
 455   unsigned int data2 : 8;
 456   unsigned int data3 : 8;
 457 } reg_gio_rw_i2c0_data;
 458 #define REG_RD_ADDR_gio_rw_i2c0_data 156
 459 #define REG_WR_ADDR_gio_rw_i2c0_data 156
 460
 461 /* Register rw_i2c0_data2, scope gio, type rw */
 462 typedef struct {
 463   unsigned int data4     : 8;
 464   unsigned int data5     : 8;
 465   unsigned int start_val : 6;
 466   unsigned int ack_val   : 6;
 467   unsigned int dummy1    : 4;
 468 } reg_gio_rw_i2c0_data2;
 469 #define REG_RD_ADDR_gio_rw_i2c0_data2 160
 470 #define REG_WR_ADDR_gio_rw_i2c0_data2 160
 471
 472 /* Register rw_i2c1_start, scope gio, type rw */
 473 typedef struct {
 474   unsigned int run : 1;
 475   unsigned int dummy1 : 31;
 476 } reg_gio_rw_i2c1_start;
 477 #define REG_RD_ADDR_gio_rw_i2c1_start 164
 478 #define REG_WR_ADDR_gio_rw_i2c1_start 164
 479
 480 /* Register rw_i2c1_cfg, scope gio, type rw */
 481 typedef struct {
 482   unsigned int en        : 1;
 483   unsigned int bit_order : 1;
 484   unsigned int scl_io    : 1;
 485   unsigned int scl_inv   : 1;
 486   unsigned int sda0_io   : 1;
 487   unsigned int sda0_idle : 1;
 488   unsigned int sda1_io   : 1;
 489   unsigned int sda1_idle : 1;
 490   unsigned int sda2_io   : 1;
 491   unsigned int sda2_idle : 1;
 492   unsigned int sda3_io   : 1;
 493   unsigned int sda3_idle : 1;
 494   unsigned int sda_sel   : 2;
 495   unsigned int sen_idle  : 1;
 496   unsigned int sen_inv   : 1;
 497   unsigned int sen_sel   : 2;
 498   unsigned int dummy1    : 14;
 499 } reg_gio_rw_i2c1_cfg;
 500 #define REG_RD_ADDR_gio_rw_i2c1_cfg 168
 501 #define REG_WR_ADDR_gio_rw_i2c1_cfg 168
 502
 503 /* Register rw_i2c1_ctrl, scope gio, type rw */
 504 typedef struct {
 505   unsigned int trf_bits    : 6;
 506   unsigned int switch_dir  : 6;
 507   unsigned int extra_start : 3;
 508   unsigned int early_end   : 1;
 509   unsigned int start_stop  : 1;
 510   unsigned int ack_dir0    : 1;
 511   unsigned int ack_dir1    : 1;
 512   unsigned int ack_dir2    : 1;
 513   unsigned int ack_dir3    : 1;
 514   unsigned int ack_dir4    : 1;
 515   unsigned int ack_dir5    : 1;
 516   unsigned int ack_bit     : 1;
 517   unsigned int start_bit   : 1;
 518   unsigned int freq        : 2;
 519   unsigned int dummy1      : 5;
 520 } reg_gio_rw_i2c1_ctrl;
 521 #define REG_RD_ADDR_gio_rw_i2c1_ctrl 172
 522 #define REG_WR_ADDR_gio_rw_i2c1_ctrl 172
 523
 524 /* Register rw_i2c1_data, scope gio, type rw */
 525 typedef struct {
 526   unsigned int data0 : 8;
 527   unsigned int data1 : 8;
 528   unsigned int data2 : 8;
 529   unsigned int data3 : 8;
 530 } reg_gio_rw_i2c1_data;
 531 #define REG_RD_ADDR_gio_rw_i2c1_data 176
 532 #define REG_WR_ADDR_gio_rw_i2c1_data 176
 533
 534 /* Register rw_i2c1_data2, scope gio, type rw */
 535 typedef struct {
 536   unsigned int data4     : 8;
 537   unsigned int data5     : 8;
 538   unsigned int start_val : 6;
 539   unsigned int ack_val   : 6;
 540   unsigned int dummy1    : 4;
 541 } reg_gio_rw_i2c1_data2;
 542 #define REG_RD_ADDR_gio_rw_i2c1_data2 180
 543 #define REG_WR_ADDR_gio_rw_i2c1_data2 180
 544
 545 /* Register r_ppwm_stat, scope gio, type r */
 546 typedef struct {
 547   unsigned int freq : 2;
 548   unsigned int dummy1 : 30;
 549 } reg_gio_r_ppwm_stat;
 550 #define REG_RD_ADDR_gio_r_ppwm_stat 184
 551
 552 /* Register rw_ppwm_data, scope gio, type rw */
 553 typedef struct {
 554   unsigned int data : 8;
 555   unsigned int dummy1 : 24;
 556 } reg_gio_rw_ppwm_data;
 557 #define REG_RD_ADDR_gio_rw_ppwm_data 188
 558 #define REG_WR_ADDR_gio_rw_ppwm_data 188
 559
 560 /* Register rw_pwm0_ctrl, scope gio, type rw */
 561 typedef struct {
 562   unsigned int mode         : 2;
 563   unsigned int ccd_override : 1;
 564   unsigned int ccd_val      : 1;
 565   unsigned int dummy1       : 28;
 566 } reg_gio_rw_pwm0_ctrl;
 567 #define REG_RD_ADDR_gio_rw_pwm0_ctrl 192
 568 #define REG_WR_ADDR_gio_rw_pwm0_ctrl 192
 569
 570 /* Register rw_pwm0_var, scope gio, type rw */
 571 typedef struct {
 572   unsigned int lo : 13;
 573   unsigned int hi : 13;
 574   unsigned int dummy1 : 6;
 575 } reg_gio_rw_pwm0_var;
 576 #define REG_RD_ADDR_gio_rw_pwm0_var 196
 577 #define REG_WR_ADDR_gio_rw_pwm0_var 196
 578
 579 /* Register rw_pwm0_data, scope gio, type rw */
 580 typedef struct {
 581   unsigned int data : 8;
 582   unsigned int dummy1 : 24;
 583 } reg_gio_rw_pwm0_data;
 584 #define REG_RD_ADDR_gio_rw_pwm0_data 200
 585 #define REG_WR_ADDR_gio_rw_pwm0_data 200
 586
 587 /* Register rw_pwm1_ctrl, scope gio, type rw */
 588 typedef struct {
 589   unsigned int mode         : 2;
 590   unsigned int ccd_override : 1;
 591   unsigned int ccd_val      : 1;
 592   unsigned int dummy1       : 28;
 593 } reg_gio_rw_pwm1_ctrl;
 594 #define REG_RD_ADDR_gio_rw_pwm1_ctrl 204
 595 #define REG_WR_ADDR_gio_rw_pwm1_ctrl 204
 596
 597 /* Register rw_pwm1_var, scope gio, type rw */
 598 typedef struct {
 599   unsigned int lo : 13;
 600   unsigned int hi : 13;
 601   unsigned int dummy1 : 6;
 602 } reg_gio_rw_pwm1_var;
 603 #define REG_RD_ADDR_gio_rw_pwm1_var 208
 604 #define REG_WR_ADDR_gio_rw_pwm1_var 208
 605
 606 /* Register rw_pwm1_data, scope gio, type rw */
 607 typedef struct {
 608   unsigned int data : 8;
 609   unsigned int dummy1 : 24;
 610 } reg_gio_rw_pwm1_data;
 611 #define REG_RD_ADDR_gio_rw_pwm1_data 212
 612 #define REG_WR_ADDR_gio_rw_pwm1_data 212
 613
 614 /* Register rw_pwm2_ctrl, scope gio, type rw */
 615 typedef struct {
 616   unsigned int mode         : 2;
 617   unsigned int ccd_override : 1;
 618   unsigned int ccd_val      : 1;
 619   unsigned int dummy1       : 28;
 620 } reg_gio_rw_pwm2_ctrl;
 621 #define REG_RD_ADDR_gio_rw_pwm2_ctrl 216
 622 #define REG_WR_ADDR_gio_rw_pwm2_ctrl 216
 623
 624 /* Register rw_pwm2_var, scope gio, type rw */
 625 typedef struct {
 626   unsigned int lo : 13;
 627   unsigned int hi : 13;
 628   unsigned int dummy1 : 6;
 629 } reg_gio_rw_pwm2_var;
 630 #define REG_RD_ADDR_gio_rw_pwm2_var 220
 631 #define REG_WR_ADDR_gio_rw_pwm2_var 220
 632
 633 /* Register rw_pwm2_data, scope gio, type rw */
 634 typedef struct {
 635   unsigned int data : 8;
 636   unsigned int dummy1 : 24;
 637 } reg_gio_rw_pwm2_data;
 638 #define REG_RD_ADDR_gio_rw_pwm2_data 224
 639 #define REG_WR_ADDR_gio_rw_pwm2_data 224
 640
 641 /* Register rw_pwm_in_cfg, scope gio, type rw */
 642 typedef struct {
 643   unsigned int pin : 3;
 644   unsigned int dummy1 : 29;
 645 } reg_gio_rw_pwm_in_cfg;
 646 #define REG_RD_ADDR_gio_rw_pwm_in_cfg 228
 647 #define REG_WR_ADDR_gio_rw_pwm_in_cfg 228
 648
 649 /* Register r_pwm_in_lo, scope gio, type r */
 650 typedef struct {
 651   unsigned int data : 32;
 652 } reg_gio_r_pwm_in_lo;
 653 #define REG_RD_ADDR_gio_r_pwm_in_lo 232
 654
 655 /* Register r_pwm_in_hi, scope gio, type r */
 656 typedef struct {
 657   unsigned int data : 32;
 658 } reg_gio_r_pwm_in_hi;
 659 #define REG_RD_ADDR_gio_r_pwm_in_hi 236
 660
 661 /* Register r_pwm_in_cnt, scope gio, type r */
 662 typedef struct {
 663   unsigned int data : 32;
 664 } reg_gio_r_pwm_in_cnt;
 665 #define REG_RD_ADDR_gio_r_pwm_in_cnt 240
 666
 667
 668 /* Constants */
 669 enum {
 670   regk_gio_anyedge                         = 0x00000007,
 671   regk_gio_f100k                           = 0x00000000,
 672   regk_gio_f1562                           = 0x00000000,
 673   regk_gio_f195                            = 0x00000003,
 674   regk_gio_f1m                             = 0x00000002,
 675   regk_gio_f390                            = 0x00000002,
 676   regk_gio_f400k                           = 0x00000001,
 677   regk_gio_f5m                             = 0x00000003,
 678   regk_gio_f781                            = 0x00000001,
 679   regk_gio_hi                              = 0x00000001,
 680   regk_gio_in                              = 0x00000000,
 681   regk_gio_intr_pa0                        = 0x00000000,
 682   regk_gio_intr_pa1                        = 0x00000000,
 683   regk_gio_intr_pa10                       = 0x00000001,
 684   regk_gio_intr_pa11                       = 0x00000001,
 685   regk_gio_intr_pa12                       = 0x00000001,
 686   regk_gio_intr_pa13                       = 0x00000001,
 687   regk_gio_intr_pa14                       = 0x00000001,
 688   regk_gio_intr_pa15                       = 0x00000001,
 689   regk_gio_intr_pa16                       = 0x00000002,
 690   regk_gio_intr_pa17                       = 0x00000002,
 691   regk_gio_intr_pa18                       = 0x00000002,
 692   regk_gio_intr_pa19                       = 0x00000002,
 693   regk_gio_intr_pa2                        = 0x00000000,
 694   regk_gio_intr_pa20                       = 0x00000002,
 695   regk_gio_intr_pa21                       = 0x00000002,
 696   regk_gio_intr_pa22                       = 0x00000002,
 697   regk_gio_intr_pa23                       = 0x00000002,
 698   regk_gio_intr_pa24                       = 0x00000003,
 699   regk_gio_intr_pa25                       = 0x00000003,
 700   regk_gio_intr_pa26                       = 0x00000003,
 701   regk_gio_intr_pa27                       = 0x00000003,
 702   regk_gio_intr_pa28                       = 0x00000003,
 703   regk_gio_intr_pa29                       = 0x00000003,
 704   regk_gio_intr_pa3                        = 0x00000000,
 705   regk_gio_intr_pa30                       = 0x00000003,
 706   regk_gio_intr_pa31                       = 0x00000003,
 707   regk_gio_intr_pa4                        = 0x00000000,
 708   regk_gio_intr_pa5                        = 0x00000000,
 709   regk_gio_intr_pa6                        = 0x00000000,
 710   regk_gio_intr_pa7                        = 0x00000000,
 711   regk_gio_intr_pa8                        = 0x00000001,
 712   regk_gio_intr_pa9                        = 0x00000001,
 713   regk_gio_intr_pb0                        = 0x00000004,
 714   regk_gio_intr_pb1                        = 0x00000004,
 715   regk_gio_intr_pb10                       = 0x00000005,
 716   regk_gio_intr_pb11                       = 0x00000005,
 717   regk_gio_intr_pb12                       = 0x00000005,
 718   regk_gio_intr_pb13                       = 0x00000005,
 719   regk_gio_intr_pb14                       = 0x00000005,
 720   regk_gio_intr_pb15                       = 0x00000005,
 721   regk_gio_intr_pb16                       = 0x00000006,
 722   regk_gio_intr_pb17                       = 0x00000006,
 723   regk_gio_intr_pb18                       = 0x00000006,
 724   regk_gio_intr_pb19                       = 0x00000006,
 725   regk_gio_intr_pb2                        = 0x00000004,
 726   regk_gio_intr_pb20                       = 0x00000006,
 727   regk_gio_intr_pb21                       = 0x00000006,
 728   regk_gio_intr_pb22                       = 0x00000006,
 729   regk_gio_intr_pb23                       = 0x00000006,
 730   regk_gio_intr_pb24                       = 0x00000007,
 731   regk_gio_intr_pb25                       = 0x00000007,
 732   regk_gio_intr_pb26                       = 0x00000007,
 733   regk_gio_intr_pb27                       = 0x00000007,
 734   regk_gio_intr_pb28                       = 0x00000007,
 735   regk_gio_intr_pb29                       = 0x00000007,
 736   regk_gio_intr_pb3                        = 0x00000004,
 737   regk_gio_intr_pb30                       = 0x00000007,
 738   regk_gio_intr_pb31                       = 0x00000007,
 739   regk_gio_intr_pb4                        = 0x00000004,
 740   regk_gio_intr_pb5                        = 0x00000004,
 741   regk_gio_intr_pb6                        = 0x00000004,
 742   regk_gio_intr_pb7                        = 0x00000004,
 743   regk_gio_intr_pb8                        = 0x00000005,
 744   regk_gio_intr_pb9                        = 0x00000005,
 745   regk_gio_intr_pc0                        = 0x00000008,
 746   regk_gio_intr_pc1                        = 0x00000008,
 747   regk_gio_intr_pc10                       = 0x00000009,
 748   regk_gio_intr_pc11                       = 0x00000009,
 749   regk_gio_intr_pc12                       = 0x00000009,
 750   regk_gio_intr_pc13                       = 0x00000009,
 751   regk_gio_intr_pc14                       = 0x00000009,
 752   regk_gio_intr_pc15                       = 0x00000009,
 753   regk_gio_intr_pc2                        = 0x00000008,
 754   regk_gio_intr_pc3                        = 0x00000008,
 755   regk_gio_intr_pc4                        = 0x00000008,
 756   regk_gio_intr_pc5                        = 0x00000008,
 757   regk_gio_intr_pc6                        = 0x00000008,
 758   regk_gio_intr_pc7                        = 0x00000008,
 759   regk_gio_intr_pc8                        = 0x00000009,
 760   regk_gio_intr_pc9                        = 0x00000009,
 761   regk_gio_intr_pd0                        = 0x0000000c,
 762   regk_gio_intr_pd1                        = 0x0000000c,
 763   regk_gio_intr_pd10                       = 0x0000000d,
 764   regk_gio_intr_pd11                       = 0x0000000d,
 765   regk_gio_intr_pd12                       = 0x0000000d,
 766   regk_gio_intr_pd13                       = 0x0000000d,
 767   regk_gio_intr_pd14                       = 0x0000000d,
 768   regk_gio_intr_pd15                       = 0x0000000d,
 769   regk_gio_intr_pd16                       = 0x0000000e,
 770   regk_gio_intr_pd17                       = 0x0000000e,
 771   regk_gio_intr_pd18                       = 0x0000000e,
 772   regk_gio_intr_pd19                       = 0x0000000e,
 773   regk_gio_intr_pd2                        = 0x0000000c,
 774   regk_gio_intr_pd20                       = 0x0000000e,
 775   regk_gio_intr_pd21                       = 0x0000000e,
 776   regk_gio_intr_pd22                       = 0x0000000e,
 777   regk_gio_intr_pd23                       = 0x0000000e,
 778   regk_gio_intr_pd24                       = 0x0000000f,
 779   regk_gio_intr_pd25                       = 0x0000000f,
 780   regk_gio_intr_pd26                       = 0x0000000f,
 781   regk_gio_intr_pd27                       = 0x0000000f,
 782   regk_gio_intr_pd28                       = 0x0000000f,
 783   regk_gio_intr_pd29                       = 0x0000000f,
 784   regk_gio_intr_pd3                        = 0x0000000c,
 785   regk_gio_intr_pd30                       = 0x0000000f,
 786   regk_gio_intr_pd31                       = 0x0000000f,
 787   regk_gio_intr_pd4                        = 0x0000000c,
 788   regk_gio_intr_pd5                        = 0x0000000c,
 789   regk_gio_intr_pd6                        = 0x0000000c,
 790   regk_gio_intr_pd7                        = 0x0000000c,
 791   regk_gio_intr_pd8                        = 0x0000000d,
 792   regk_gio_intr_pd9                        = 0x0000000d,
 793   regk_gio_lo                              = 0x00000002,
 794   regk_gio_lsb                             = 0x00000000,
 795   regk_gio_msb                             = 0x00000001,
 796   regk_gio_negedge                         = 0x00000006,
 797   regk_gio_no                              = 0x00000000,
 798   regk_gio_no_switch                       = 0x0000003f,
 799   regk_gio_none                            = 0x00000007,
 800   regk_gio_off                             = 0x00000000,
 801   regk_gio_opendrain                       = 0x00000000,
 802   regk_gio_out                             = 0x00000001,
 803   regk_gio_posedge                         = 0x00000005,
 804   regk_gio_pwm_hfp                         = 0x00000002,
 805   regk_gio_pwm_pa0                         = 0x00000001,
 806   regk_gio_pwm_pa19                        = 0x00000004,
 807   regk_gio_pwm_pa6                         = 0x00000002,
 808   regk_gio_pwm_pa7                         = 0x00000003,
 809   regk_gio_pwm_pb26                        = 0x00000005,
 810   regk_gio_pwm_pd23                        = 0x00000006,
 811   regk_gio_pwm_pd31                        = 0x00000007,
 812   regk_gio_pwm_std                         = 0x00000001,
 813   regk_gio_pwm_var                         = 0x00000003,
 814   regk_gio_rw_i2c0_cfg_default             = 0x00000020,
 815   regk_gio_rw_i2c0_ctrl_default            = 0x00010000,
 816   regk_gio_rw_i2c0_start_default           = 0x00000000,
 817   regk_gio_rw_i2c1_cfg_default             = 0x00000aa0,
 818   regk_gio_rw_i2c1_ctrl_default            = 0x00010000,
 819   regk_gio_rw_i2c1_start_default           = 0x00000000,
 820   regk_gio_rw_intr_cfg_default             = 0x00000000,
 821   regk_gio_rw_intr_mask_default            = 0x00000000,
 822   regk_gio_rw_pa_oe_default                = 0x00000000,
 823   regk_gio_rw_pb_oe_default                = 0x00000000,
 824   regk_gio_rw_pc_oe_default                = 0x00000000,
 825   regk_gio_rw_ppwm_data_default            = 0x00000000,
 826   regk_gio_rw_pwm0_ctrl_default            = 0x00000000,
 827   regk_gio_rw_pwm1_ctrl_default            = 0x00000000,
 828   regk_gio_rw_pwm2_ctrl_default            = 0x00000000,
 829   regk_gio_rw_pwm_in_cfg_default           = 0x00000000,
 830   regk_gio_sda0                            = 0x00000000,
 831   regk_gio_sda1                            = 0x00000001,
 832   regk_gio_sda2                            = 0x00000002,
 833   regk_gio_sda3                            = 0x00000003,
 834   regk_gio_sen                             = 0x00000000,
 835   regk_gio_set                             = 0x00000003,
 836   regk_gio_yes                             = 0x00000001
 837 };
 838 #endif /* __gio_defs_h */