arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __timer_defs_h
   3 #define __timer_defs_h
   4
   5 /*
   6  * This file is autogenerated from
   7  *   file:           ../../inst/timer/rtl/timer_regs.r
   8  *     id:           timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
   9  *     last modfied: Mon Apr 11 16:09:53 2005
  10  *
  11  *   by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r
  12  *      id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $
  13  * Any changes here will be lost.
  14  *
  15  * -*- buffer-read-only: t -*-
  16  */
  17 /* Main access macros */
  18 #ifndef REG_RD
  19 #define REG_RD( scope, inst, reg ) \
  20   REG_READ( reg_##scope##_##reg, \
  21             (inst) + REG_RD_ADDR_##scope##_##reg )
  22 #endif
  23
  24 #ifndef REG_WR
  25 #define REG_WR( scope, inst, reg, val ) \
  26   REG_WRITE( reg_##scope##_##reg, \
  27              (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  28 #endif
  29
  30 #ifndef REG_RD_VECT
  31 #define REG_RD_VECT( scope, inst, reg, index ) \
  32   REG_READ( reg_##scope##_##reg, \
  33             (inst) + REG_RD_ADDR_##scope##_##reg + \
  34             (index) * STRIDE_##scope##_##reg )
  35 #endif
  36
  37 #ifndef REG_WR_VECT
  38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
  39   REG_WRITE( reg_##scope##_##reg, \
  40              (inst) + REG_WR_ADDR_##scope##_##reg + \
  41              (index) * STRIDE_##scope##_##reg, (val) )
  42 #endif
  43
  44 #ifndef REG_RD_INT
  45 #define REG_RD_INT( scope, inst, reg ) \
  46   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
  47 #endif
  48
  49 #ifndef REG_WR_INT
  50 #define REG_WR_INT( scope, inst, reg, val ) \
  51   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
  52 #endif
  53
  54 #ifndef REG_RD_INT_VECT
  55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
  56   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
  57             (index) * STRIDE_##scope##_##reg )
  58 #endif
  59
  60 #ifndef REG_WR_INT_VECT
  61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  62   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
  63              (index) * STRIDE_##scope##_##reg, (val) )
  64 #endif
  65
  66 #ifndef REG_TYPE_CONV
  67 #define REG_TYPE_CONV( type, orgtype, val ) \
  68   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
  69 #endif
  70
  71 #ifndef reg_page_size
  72 #define reg_page_size 8192
  73 #endif
  74
  75 #ifndef REG_ADDR
  76 #define REG_ADDR( scope, inst, reg ) \
  77   ( (inst) + REG_RD_ADDR_##scope##_##reg )
  78 #endif
  79
  80 #ifndef REG_ADDR_VECT
  81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  82   ( (inst) + REG_RD_ADDR_##scope##_##reg + \
  83     (index) * STRIDE_##scope##_##reg )
  84 #endif
  85
  86 /* C-code for register scope timer */
  87
  88 /* Register rw_tmr0_div, scope timer, type rw */
  89 typedef unsigned int reg_timer_rw_tmr0_div;
  90 #define REG_RD_ADDR_timer_rw_tmr0_div 0
  91 #define REG_WR_ADDR_timer_rw_tmr0_div 0
  92
  93 /* Register r_tmr0_data, scope timer, type r */
  94 typedef unsigned int reg_timer_r_tmr0_data;
  95 #define REG_RD_ADDR_timer_r_tmr0_data 4
  96
  97 /* Register rw_tmr0_ctrl, scope timer, type rw */
  98 typedef struct {
  99   unsigned int op   : 2;
 100   unsigned int freq : 3;
 101   unsigned int dummy1 : 27;
 102 } reg_timer_rw_tmr0_ctrl;
 103 #define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
 104 #define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
 105
 106 /* Register rw_tmr1_div, scope timer, type rw */
 107 typedef unsigned int reg_timer_rw_tmr1_div;
 108 #define REG_RD_ADDR_timer_rw_tmr1_div 16
 109 #define REG_WR_ADDR_timer_rw_tmr1_div 16
 110
 111 /* Register r_tmr1_data, scope timer, type r */
 112 typedef unsigned int reg_timer_r_tmr1_data;
 113 #define REG_RD_ADDR_timer_r_tmr1_data 20
 114
 115 /* Register rw_tmr1_ctrl, scope timer, type rw */
 116 typedef struct {
 117   unsigned int op   : 2;
 118   unsigned int freq : 3;
 119   unsigned int dummy1 : 27;
 120 } reg_timer_rw_tmr1_ctrl;
 121 #define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
 122 #define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
 123
 124 /* Register rs_cnt_data, scope timer, type rs */
 125 typedef struct {
 126   unsigned int tmr : 24;
 127   unsigned int cnt : 8;
 128 } reg_timer_rs_cnt_data;
 129 #define REG_RD_ADDR_timer_rs_cnt_data 32
 130
 131 /* Register r_cnt_data, scope timer, type r */
 132 typedef struct {
 133   unsigned int tmr : 24;
 134   unsigned int cnt : 8;
 135 } reg_timer_r_cnt_data;
 136 #define REG_RD_ADDR_timer_r_cnt_data 36
 137
 138 /* Register rw_cnt_cfg, scope timer, type rw */
 139 typedef struct {
 140   unsigned int clk : 2;
 141   unsigned int dummy1 : 30;
 142 } reg_timer_rw_cnt_cfg;
 143 #define REG_RD_ADDR_timer_rw_cnt_cfg 40
 144 #define REG_WR_ADDR_timer_rw_cnt_cfg 40
 145
 146 /* Register rw_trig, scope timer, type rw */
 147 typedef unsigned int reg_timer_rw_trig;
 148 #define REG_RD_ADDR_timer_rw_trig 48
 149 #define REG_WR_ADDR_timer_rw_trig 48
 150
 151 /* Register rw_trig_cfg, scope timer, type rw */
 152 typedef struct {
 153   unsigned int tmr : 2;
 154   unsigned int dummy1 : 30;
 155 } reg_timer_rw_trig_cfg;
 156 #define REG_RD_ADDR_timer_rw_trig_cfg 52
 157 #define REG_WR_ADDR_timer_rw_trig_cfg 52
 158
 159 /* Register r_time, scope timer, type r */
 160 typedef unsigned int reg_timer_r_time;
 161 #define REG_RD_ADDR_timer_r_time 56
 162
 163 /* Register rw_out, scope timer, type rw */
 164 typedef struct {
 165   unsigned int tmr : 2;
 166   unsigned int dummy1 : 30;
 167 } reg_timer_rw_out;
 168 #define REG_RD_ADDR_timer_rw_out 60
 169 #define REG_WR_ADDR_timer_rw_out 60
 170
 171 /* Register rw_wd_ctrl, scope timer, type rw */
 172 typedef struct {
 173   unsigned int cnt : 8;
 174   unsigned int cmd : 1;
 175   unsigned int key : 7;
 176   unsigned int dummy1 : 16;
 177 } reg_timer_rw_wd_ctrl;
 178 #define REG_RD_ADDR_timer_rw_wd_ctrl 64
 179 #define REG_WR_ADDR_timer_rw_wd_ctrl 64
 180
 181 /* Register r_wd_stat, scope timer, type r */
 182 typedef struct {
 183   unsigned int cnt : 8;
 184   unsigned int cmd : 1;
 185   unsigned int dummy1 : 23;
 186 } reg_timer_r_wd_stat;
 187 #define REG_RD_ADDR_timer_r_wd_stat 68
 188
 189 /* Register rw_intr_mask, scope timer, type rw */
 190 typedef struct {
 191   unsigned int tmr0 : 1;
 192   unsigned int tmr1 : 1;
 193   unsigned int cnt  : 1;
 194   unsigned int trig : 1;
 195   unsigned int dummy1 : 28;
 196 } reg_timer_rw_intr_mask;
 197 #define REG_RD_ADDR_timer_rw_intr_mask 72
 198 #define REG_WR_ADDR_timer_rw_intr_mask 72
 199
 200 /* Register rw_ack_intr, scope timer, type rw */
 201 typedef struct {
 202   unsigned int tmr0 : 1;
 203   unsigned int tmr1 : 1;
 204   unsigned int cnt  : 1;
 205   unsigned int trig : 1;
 206   unsigned int dummy1 : 28;
 207 } reg_timer_rw_ack_intr;
 208 #define REG_RD_ADDR_timer_rw_ack_intr 76
 209 #define REG_WR_ADDR_timer_rw_ack_intr 76
 210
 211 /* Register r_intr, scope timer, type r */
 212 typedef struct {
 213   unsigned int tmr0 : 1;
 214   unsigned int tmr1 : 1;
 215   unsigned int cnt  : 1;
 216   unsigned int trig : 1;
 217   unsigned int dummy1 : 28;
 218 } reg_timer_r_intr;
 219 #define REG_RD_ADDR_timer_r_intr 80
 220
 221 /* Register r_masked_intr, scope timer, type r */
 222 typedef struct {
 223   unsigned int tmr0 : 1;
 224   unsigned int tmr1 : 1;
 225   unsigned int cnt  : 1;
 226   unsigned int trig : 1;
 227   unsigned int dummy1 : 28;
 228 } reg_timer_r_masked_intr;
 229 #define REG_RD_ADDR_timer_r_masked_intr 84
 230
 231 /* Register rw_test, scope timer, type rw */
 232 typedef struct {
 233   unsigned int dis : 1;
 234   unsigned int en  : 1;
 235   unsigned int dummy1 : 30;
 236 } reg_timer_rw_test;
 237 #define REG_RD_ADDR_timer_rw_test 88
 238 #define REG_WR_ADDR_timer_rw_test 88
 239
 240
 241 /* Constants */
 242 enum {
 243   regk_timer_ext                           = 0x00000001,
 244   regk_timer_f100                          = 0x00000007,
 245   regk_timer_f29_493                       = 0x00000004,
 246   regk_timer_f32                           = 0x00000005,
 247   regk_timer_f32_768                       = 0x00000006,
 248   regk_timer_hold                          = 0x00000001,
 249   regk_timer_ld                            = 0x00000000,
 250   regk_timer_no                            = 0x00000000,
 251   regk_timer_off                           = 0x00000000,
 252   regk_timer_run                           = 0x00000002,
 253   regk_timer_rw_cnt_cfg_default            = 0x00000000,
 254   regk_timer_rw_intr_mask_default          = 0x00000000,
 255   regk_timer_rw_out_default                = 0x00000000,
 256   regk_timer_rw_test_default               = 0x00000000,
 257   regk_timer_rw_tmr0_ctrl_default          = 0x00000000,
 258   regk_timer_rw_tmr1_ctrl_default          = 0x00000000,
 259   regk_timer_rw_trig_cfg_default           = 0x00000000,
 260   regk_timer_start                         = 0x00000001,
 261   regk_timer_stop                          = 0x00000000,
 262   regk_timer_time                          = 0x00000001,
 263   regk_timer_tmr0                          = 0x00000002,
 264   regk_timer_tmr1                          = 0x00000003,
 265   regk_timer_yes                           = 0x00000001
 266 };
 267 #endif /* __timer_defs_h */