arch/hexagon/include/asm/cacheflush.h

   1 /*
   2  * Cache flush operations for the Hexagon architecture
   3  *
   4  * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 and
   8  * only version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  18  * 02110-1301, USA.
  19  */
  20
  21 #ifndef _ASM_CACHEFLUSH_H
  22 #define _ASM_CACHEFLUSH_H
  23
  24 #include <linux/mm_types.h>
  25
  26 /* Cache flushing:
  27  *
  28  *  - flush_cache_all() flushes entire cache
  29  *  - flush_cache_mm(mm) flushes the specified mm context's cache lines
  30  *  - flush_cache_page(mm, vmaddr, pfn) flushes a single page
  31  *  - flush_cache_range(vma, start, end) flushes a range of pages
  32  *  - flush_icache_range(start, end) flush a range of instructions
  33  *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
  34  *  - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
  35  *
  36  *  Need to doublecheck which one is really needed for ptrace stuff to work.
  37  */
  38 #define LINESIZE        32
  39 #define LINEBITS        5
  40
  41 #define flush_cache_all()                       do { } while (0)
  42 #define flush_cache_mm(mm)                      do { } while (0)
  43 #define flush_cache_dup_mm(mm)                  do { } while (0)
  44 #define flush_cache_range(vma, start, end)      do { } while (0)
  45 #define flush_cache_page(vma, vmaddr, pfn)      do { } while (0)
  46 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
  47 #define flush_dcache_page(page)                 do { } while (0)
  48 #define flush_dcache_mmap_lock(mapping)         do { } while (0)
  49 #define flush_dcache_mmap_unlock(mapping)       do { } while (0)
  50 #define flush_icache_page(vma, pg)              do { } while (0)
  51 #define flush_icache_user_range(vma, pg, adr, len)      do { } while (0)
  52 #define flush_cache_vmap(start, end)            do { } while (0)
  53 #define flush_cache_vunmap(start, end)          do { } while (0)
  54
  55 /*
  56  * Flush Dcache range through current map.
  57  */
  58 extern void flush_dcache_range(unsigned long start, unsigned long end);
  59
  60 /*
  61  * Flush Icache range through current map.
  62  */
  63 extern void flush_icache_range(unsigned long start, unsigned long end);
  64
  65 /*
  66  * Memory-management related flushes are there to ensure in non-physically
  67  * indexed cache schemes that stale lines belonging to a given ASID aren't
  68  * in the cache to confuse things.  The prototype Hexagon Virtual Machine
  69  * only uses a single ASID for all user-mode maps, which should
  70  * mean that they aren't necessary.  A brute-force, flush-everything
  71  * implementation, with the name xxxxx_hexagon() is present in
  72  * arch/hexagon/mm/cache.c, but let's not wire it up until we know
  73  * it is needed.
  74  */
  75 extern void flush_cache_all_hexagon(void);
  76
  77 /*
  78  * This may or may not ever have to be non-null, depending on the
  79  * virtual machine MMU.  For a native kernel, it's definitiely  a no-op
  80  *
  81  * This is also the place where deferred cache coherency stuff seems
  82  * to happen, classically...  but instead we do it like ia64 and
  83  * clean the cache when the PTE is set.
  84  *
  85  */
  86 static inline void update_mmu_cache(struct vm_area_struct *vma,
  87                                         unsigned long address, pte_t *ptep)
  88 {
  89         /*  generic_ptrace_pokedata doesn't wind up here, does it?  */
  90 }
  91
  92 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
  93                        unsigned long vaddr, void *dst, void *src, int len);
  94
  95 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
  96         memcpy(dst, src, len)
  97
  98 extern void hexagon_inv_dcache_range(unsigned long start, unsigned long end);
  99 extern void hexagon_clean_dcache_range(unsigned long start, unsigned long end);
 100
 101 #endif