1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <asm/semaphore.h>
8 #include <asm/processor.h>
12 #include <asm/mmu_context.h>
13 #ifdef CONFIG_X86_LOCAL_APIC
14 #include <asm/mpspec.h>
16 #include <mach_apic.h>
21 DEFINE_PER_CPU(unsigned char, cpu_16bit_stack
[CPU_16BIT_STACK_SIZE
]);
22 EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack
);
24 static int cachesize_override __devinitdata
= -1;
25 static int disable_x86_fxsr __devinitdata
= 0;
26 static int disable_x86_serial_nr __devinitdata
= 1;
28 struct cpu_dev
* cpu_devs
[X86_VENDOR_NUM
] = {};
30 extern int disable_pse
;
32 static void default_init(struct cpuinfo_x86
* c
)
34 /* Not much we can do here... */
35 /* Check if at least it has cpuid */
36 if (c
->cpuid_level
== -1) {
37 /* No cpuid. It must be an ancient CPU */
39 strcpy(c
->x86_model_id
, "486");
41 strcpy(c
->x86_model_id
, "386");
45 static struct cpu_dev default_cpu
= {
46 .c_init
= default_init
,
48 static struct cpu_dev
* this_cpu
= &default_cpu
;
50 static int __init
cachesize_setup(char *str
)
52 get_option (&str
, &cachesize_override
);
55 __setup("cachesize=", cachesize_setup
);
57 int __devinit
get_model_name(struct cpuinfo_x86
*c
)
62 if (cpuid_eax(0x80000000) < 0x80000004)
65 v
= (unsigned int *) c
->x86_model_id
;
66 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
67 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
68 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
69 c
->x86_model_id
[48] = 0;
71 /* Intel chips right-justify this string for some dumb reason;
72 undo that brain damage */
73 p
= q
= &c
->x86_model_id
[0];
79 while ( q
<= &c
->x86_model_id
[48] )
80 *q
++ = '\0'; /* Zero-pad the rest */
87 void __devinit
display_cacheinfo(struct cpuinfo_x86
*c
)
89 unsigned int n
, dummy
, ecx
, edx
, l2size
;
91 n
= cpuid_eax(0x80000000);
93 if (n
>= 0x80000005) {
94 cpuid(0x80000005, &dummy
, &dummy
, &ecx
, &edx
);
95 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
96 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
97 c
->x86_cache_size
=(ecx
>>24)+(edx
>>24);
100 if (n
< 0x80000006) /* Some chips just has a large L1. */
103 ecx
= cpuid_ecx(0x80000006);
106 /* do processor-specific cache resizing */
107 if (this_cpu
->c_size_cache
)
108 l2size
= this_cpu
->c_size_cache(c
,l2size
);
110 /* Allow user to override all this if necessary. */
111 if (cachesize_override
!= -1)
112 l2size
= cachesize_override
;
115 return; /* Again, no L2 cache is possible */
117 c
->x86_cache_size
= l2size
;
119 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
123 /* Naming convention should be: <Name> [(<Codename>)] */
124 /* This table only is used unless init_<vendor>() below doesn't set it; */
125 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
127 /* Look up CPU names by table lookup. */
128 static char __devinit
*table_lookup_model(struct cpuinfo_x86
*c
)
130 struct cpu_model_info
*info
;
132 if ( c
->x86_model
>= 16 )
133 return NULL
; /* Range check */
138 info
= this_cpu
->c_models
;
140 while (info
&& info
->family
) {
141 if (info
->family
== c
->x86
)
142 return info
->model_names
[c
->x86_model
];
145 return NULL
; /* Not found */
149 static void __devinit
get_cpu_vendor(struct cpuinfo_x86
*c
, int early
)
151 char *v
= c
->x86_vendor_id
;
154 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
156 if (!strcmp(v
,cpu_devs
[i
]->c_ident
[0]) ||
157 (cpu_devs
[i
]->c_ident
[1] &&
158 !strcmp(v
,cpu_devs
[i
]->c_ident
[1]))) {
161 this_cpu
= cpu_devs
[i
];
169 static int __init
x86_fxsr_setup(char * s
)
171 disable_x86_fxsr
= 1;
174 __setup("nofxsr", x86_fxsr_setup
);
177 /* Standard macro to see if a specific flag is changeable */
178 static inline int flag_is_changeable_p(u32 flag
)
192 : "=&r" (f1
), "=&r" (f2
)
195 return ((f1
^f2
) & flag
) != 0;
199 /* Probe for the CPUID instruction */
200 static int __devinit
have_cpuid_p(void)
202 return flag_is_changeable_p(X86_EFLAGS_ID
);
205 /* Do minimum CPU detection early.
206 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
207 The others are not touched to avoid unwanted side effects.
209 WARNING: this function is only called on the BP. Don't add code here
210 that is supposed to run on all CPUs. */
211 static void __init
early_cpu_detect(void)
213 struct cpuinfo_x86
*c
= &boot_cpu_data
;
215 c
->x86_cache_alignment
= 32;
220 /* Get vendor name */
221 cpuid(0x00000000, &c
->cpuid_level
,
222 (int *)&c
->x86_vendor_id
[0],
223 (int *)&c
->x86_vendor_id
[8],
224 (int *)&c
->x86_vendor_id
[4]);
226 get_cpu_vendor(c
, 1);
229 if (c
->cpuid_level
>= 0x00000001) {
230 u32 junk
, tfms
, cap0
, misc
;
231 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
232 c
->x86
= (tfms
>> 8) & 15;
233 c
->x86_model
= (tfms
>> 4) & 15;
235 c
->x86
+= (tfms
>> 20) & 0xff;
237 c
->x86_model
+= ((tfms
>> 16) & 0xF) << 4;
238 c
->x86_mask
= tfms
& 15;
240 c
->x86_cache_alignment
= ((misc
>> 8) & 0xff) * 8;
244 void __devinit
generic_identify(struct cpuinfo_x86
* c
)
249 if (have_cpuid_p()) {
250 /* Get vendor name */
251 cpuid(0x00000000, &c
->cpuid_level
,
252 (int *)&c
->x86_vendor_id
[0],
253 (int *)&c
->x86_vendor_id
[8],
254 (int *)&c
->x86_vendor_id
[4]);
256 get_cpu_vendor(c
, 0);
257 /* Initialize the standard set of capabilities */
258 /* Note that the vendor-specific code below might override */
260 /* Intel-defined flags: level 0x00000001 */
261 if ( c
->cpuid_level
>= 0x00000001 ) {
262 u32 capability
, excap
;
263 cpuid(0x00000001, &tfms
, &junk
, &excap
, &capability
);
264 c
->x86_capability
[0] = capability
;
265 c
->x86_capability
[4] = excap
;
266 c
->x86
= (tfms
>> 8) & 15;
267 c
->x86_model
= (tfms
>> 4) & 15;
269 c
->x86
+= (tfms
>> 20) & 0xff;
270 c
->x86_model
+= ((tfms
>> 16) & 0xF) << 4;
272 c
->x86_mask
= tfms
& 15;
274 /* Have CPUID level 0 only - unheard of */
278 /* AMD-defined flags: level 0x80000001 */
279 xlvl
= cpuid_eax(0x80000000);
280 if ( (xlvl
& 0xffff0000) == 0x80000000 ) {
281 if ( xlvl
>= 0x80000001 ) {
282 c
->x86_capability
[1] = cpuid_edx(0x80000001);
283 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
285 if ( xlvl
>= 0x80000004 )
286 get_model_name(c
); /* Default name */
290 early_intel_workaround(c
);
293 phys_proc_id
[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
297 static void __devinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
299 if (cpu_has(c
, X86_FEATURE_PN
) && disable_x86_serial_nr
) {
300 /* Disable processor serial number */
302 rdmsr(MSR_IA32_BBL_CR_CTL
,lo
,hi
);
304 wrmsr(MSR_IA32_BBL_CR_CTL
,lo
,hi
);
305 printk(KERN_NOTICE
"CPU serial number disabled.\n");
306 clear_bit(X86_FEATURE_PN
, c
->x86_capability
);
308 /* Disabling the serial number may affect the cpuid level */
309 c
->cpuid_level
= cpuid_eax(0);
313 static int __init
x86_serial_nr_setup(char *s
)
315 disable_x86_serial_nr
= 0;
318 __setup("serialnumber", x86_serial_nr_setup
);
323 * This does the hard work of actually picking apart the CPU stuff...
325 void __devinit
identify_cpu(struct cpuinfo_x86
*c
)
329 c
->loops_per_jiffy
= loops_per_jiffy
;
330 c
->x86_cache_size
= -1;
331 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
332 c
->cpuid_level
= -1; /* CPUID not detected */
333 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
334 c
->x86_vendor_id
[0] = '\0'; /* Unset */
335 c
->x86_model_id
[0] = '\0'; /* Unset */
336 c
->x86_max_cores
= 1;
337 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
339 if (!have_cpuid_p()) {
340 /* First of all, decide if this is a 486 or higher */
341 /* It's a 486 if we can modify the AC flag */
342 if ( flag_is_changeable_p(X86_EFLAGS_AC
) )
350 printk(KERN_DEBUG
"CPU: After generic identify, caps:");
351 for (i
= 0; i
< NCAPINTS
; i
++)
352 printk(" %08lx", c
->x86_capability
[i
]);
355 if (this_cpu
->c_identify
) {
356 this_cpu
->c_identify(c
);
358 printk(KERN_DEBUG
"CPU: After vendor identify, caps:");
359 for (i
= 0; i
< NCAPINTS
; i
++)
360 printk(" %08lx", c
->x86_capability
[i
]);
365 * Vendor-specific initialization. In this section we
366 * canonicalize the feature flags, meaning if there are
367 * features a certain CPU supports which CPUID doesn't
368 * tell us, CPUID claiming incorrect flags, or other bugs,
369 * we handle them here.
371 * At the end of this section, c->x86_capability better
372 * indicate the features this CPU genuinely supports!
374 if (this_cpu
->c_init
)
377 /* Disable the PN if appropriate */
378 squash_the_stupid_serial_number(c
);
381 * The vendor-specific functions might have changed features. Now
382 * we do "generic changes."
387 clear_bit(X86_FEATURE_TSC
, c
->x86_capability
);
390 if (disable_x86_fxsr
) {
391 clear_bit(X86_FEATURE_FXSR
, c
->x86_capability
);
392 clear_bit(X86_FEATURE_XMM
, c
->x86_capability
);
396 clear_bit(X86_FEATURE_PSE
, c
->x86_capability
);
398 /* If the model name is still unset, do table lookup. */
399 if ( !c
->x86_model_id
[0] ) {
401 p
= table_lookup_model(c
);
403 strcpy(c
->x86_model_id
, p
);
406 sprintf(c
->x86_model_id
, "%02x/%02x",
407 c
->x86_vendor
, c
->x86_model
);
410 /* Now the feature flags better reflect actual CPU features! */
412 printk(KERN_DEBUG
"CPU: After all inits, caps:");
413 for (i
= 0; i
< NCAPINTS
; i
++)
414 printk(" %08lx", c
->x86_capability
[i
]);
418 * On SMP, boot_cpu_data holds the common feature set between
419 * all CPUs; so make sure that we indicate which features are
420 * common between the CPUs. The first time this routine gets
421 * executed, c == &boot_cpu_data.
423 if ( c
!= &boot_cpu_data
) {
424 /* AND the already accumulated flags with these */
425 for ( i
= 0 ; i
< NCAPINTS
; i
++ )
426 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
429 /* Init Machine Check Exception if available. */
432 if (c
== &boot_cpu_data
)
436 if (c
== &boot_cpu_data
)
443 void __devinit
detect_ht(struct cpuinfo_x86
*c
)
445 u32 eax
, ebx
, ecx
, edx
;
446 int index_msb
, core_bits
;
447 int cpu
= smp_processor_id();
449 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
451 c
->apicid
= phys_pkg_id((ebx
>> 24) & 0xFF, 0);
453 if (!cpu_has(c
, X86_FEATURE_HT
) || cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
456 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
458 if (smp_num_siblings
== 1) {
459 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
460 } else if (smp_num_siblings
> 1 ) {
462 if (smp_num_siblings
> NR_CPUS
) {
463 printk(KERN_WARNING
"CPU: Unsupported number of the siblings %d", smp_num_siblings
);
464 smp_num_siblings
= 1;
468 index_msb
= get_count_order(smp_num_siblings
);
469 phys_proc_id
[cpu
] = phys_pkg_id((ebx
>> 24) & 0xFF, index_msb
);
471 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
474 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
476 index_msb
= get_count_order(smp_num_siblings
) ;
478 core_bits
= get_count_order(c
->x86_max_cores
);
480 cpu_core_id
[cpu
] = phys_pkg_id((ebx
>> 24) & 0xFF, index_msb
) &
481 ((1 << core_bits
) - 1);
483 if (c
->x86_max_cores
> 1)
484 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
490 void __devinit
print_cpu_info(struct cpuinfo_x86
*c
)
494 if (c
->x86_vendor
< X86_VENDOR_NUM
)
495 vendor
= this_cpu
->c_vendor
;
496 else if (c
->cpuid_level
>= 0)
497 vendor
= c
->x86_vendor_id
;
499 if (vendor
&& strncmp(c
->x86_model_id
, vendor
, strlen(vendor
)))
500 printk("%s ", vendor
);
502 if (!c
->x86_model_id
[0])
503 printk("%d86", c
->x86
);
505 printk("%s", c
->x86_model_id
);
507 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
508 printk(" stepping %02x\n", c
->x86_mask
);
513 cpumask_t cpu_initialized __devinitdata
= CPU_MASK_NONE
;
516 * We're emulating future behavior.
517 * In the future, the cpu-specific init functions will be called implicitly
518 * via the magic of initcalls.
519 * They will insert themselves into the cpu_devs structure.
520 * Then, when cpu_init() is called, we can just iterate over that array.
523 extern int intel_cpu_init(void);
524 extern int cyrix_init_cpu(void);
525 extern int nsc_init_cpu(void);
526 extern int amd_init_cpu(void);
527 extern int centaur_init_cpu(void);
528 extern int transmeta_init_cpu(void);
529 extern int rise_init_cpu(void);
530 extern int nexgen_init_cpu(void);
531 extern int umc_init_cpu(void);
533 void __init
early_cpu_init(void)
540 transmeta_init_cpu();
546 #ifdef CONFIG_DEBUG_PAGEALLOC
547 /* pse is not compatible with on-the-fly unmapping,
548 * disable it even if the cpus claim to support it.
550 clear_bit(X86_FEATURE_PSE
, boot_cpu_data
.x86_capability
);
555 * cpu_init() initializes state that is per-CPU. Some data is already
556 * initialized (naturally) in the bootstrap process, such as the GDT
557 * and IDT. We reload them nevertheless, this function acts as a
558 * 'CPU state barrier', nothing should get across.
560 void __devinit
cpu_init(void)
562 int cpu
= smp_processor_id();
563 struct tss_struct
* t
= &per_cpu(init_tss
, cpu
);
564 struct thread_struct
*thread
= ¤t
->thread
;
565 struct desc_struct
*gdt
= get_cpu_gdt_table(cpu
);
566 __u32 stk16_off
= (__u32
)&per_cpu(cpu_16bit_stack
, cpu
);
568 if (cpu_test_and_set(cpu
, cpu_initialized
)) {
569 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
570 for (;;) local_irq_enable();
572 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
574 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
575 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
576 if (tsc_disable
&& cpu_has_tsc
) {
577 printk(KERN_NOTICE
"Disabling TSC...\n");
578 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
579 clear_bit(X86_FEATURE_TSC
, boot_cpu_data
.x86_capability
);
580 set_in_cr4(X86_CR4_TSD
);
584 * Initialize the per-CPU GDT with the boot GDT,
585 * and set up the GDT descriptor:
587 memcpy(gdt
, cpu_gdt_table
, GDT_SIZE
);
589 /* Set up GDT entry for 16bit stack */
590 *(__u64
*)(&gdt
[GDT_ENTRY_ESPFIX_SS
]) |=
591 ((((__u64
)stk16_off
) << 16) & 0x000000ffffff0000ULL
) |
592 ((((__u64
)stk16_off
) << 32) & 0xff00000000000000ULL
) |
593 (CPU_16BIT_STACK_SIZE
- 1);
595 cpu_gdt_descr
[cpu
].size
= GDT_SIZE
- 1;
596 cpu_gdt_descr
[cpu
].address
= (unsigned long)gdt
;
598 load_gdt(&cpu_gdt_descr
[cpu
]);
599 load_idt(&idt_descr
);
602 * Set up and load the per-CPU TSS and LDT
604 atomic_inc(&init_mm
.mm_count
);
605 current
->active_mm
= &init_mm
;
608 enter_lazy_tlb(&init_mm
, current
);
610 load_esp0(t
, thread
);
613 load_LDT(&init_mm
.context
);
615 #ifdef CONFIG_DOUBLEFAULT
616 /* Set up doublefault TSS pointer in the GDT */
617 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
620 /* Clear %fs and %gs. */
621 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
623 /* Clear all 6 debug registers: */
632 * Force FPU initialization:
634 current_thread_info()->status
= 0;
636 mxcsr_feature_mask_init();
639 #ifdef CONFIG_HOTPLUG_CPU
640 void __devinit
cpu_uninit(void)
642 int cpu
= raw_smp_processor_id();
643 cpu_clear(cpu
, cpu_initialized
);
646 per_cpu(cpu_tlbstate
, cpu
).state
= 0;
647 per_cpu(cpu_tlbstate
, cpu
).active_mm
= &init_mm
;