1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/semaphore.h>
9 #include <asm/processor.h>
13 #include <asm/mmu_context.h>
16 #ifdef CONFIG_X86_LOCAL_APIC
17 #include <asm/mpspec.h>
19 #include <mach_apic.h>
25 DEFINE_PER_CPU(struct Xgt_desc_struct
, cpu_gdt_descr
);
26 EXPORT_PER_CPU_SYMBOL(cpu_gdt_descr
);
28 struct i386_pda
*_cpu_pda
[NR_CPUS
] __read_mostly
;
29 EXPORT_SYMBOL(_cpu_pda
);
31 static int cachesize_override __cpuinitdata
= -1;
32 static int disable_x86_fxsr __cpuinitdata
;
33 static int disable_x86_serial_nr __cpuinitdata
= 1;
34 static int disable_x86_sep __cpuinitdata
;
36 struct cpu_dev
* cpu_devs
[X86_VENDOR_NUM
] = {};
38 extern int disable_pse
;
40 static void __cpuinit
default_init(struct cpuinfo_x86
* c
)
42 /* Not much we can do here... */
43 /* Check if at least it has cpuid */
44 if (c
->cpuid_level
== -1) {
45 /* No cpuid. It must be an ancient CPU */
47 strcpy(c
->x86_model_id
, "486");
49 strcpy(c
->x86_model_id
, "386");
53 static struct cpu_dev __cpuinitdata default_cpu
= {
54 .c_init
= default_init
,
55 .c_vendor
= "Unknown",
57 static struct cpu_dev
* this_cpu
= &default_cpu
;
59 static int __init
cachesize_setup(char *str
)
61 get_option (&str
, &cachesize_override
);
64 __setup("cachesize=", cachesize_setup
);
66 int __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
71 if (cpuid_eax(0x80000000) < 0x80000004)
74 v
= (unsigned int *) c
->x86_model_id
;
75 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
76 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
77 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
78 c
->x86_model_id
[48] = 0;
80 /* Intel chips right-justify this string for some dumb reason;
81 undo that brain damage */
82 p
= q
= &c
->x86_model_id
[0];
88 while ( q
<= &c
->x86_model_id
[48] )
89 *q
++ = '\0'; /* Zero-pad the rest */
96 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
98 unsigned int n
, dummy
, ecx
, edx
, l2size
;
100 n
= cpuid_eax(0x80000000);
102 if (n
>= 0x80000005) {
103 cpuid(0x80000005, &dummy
, &dummy
, &ecx
, &edx
);
104 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
105 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
106 c
->x86_cache_size
=(ecx
>>24)+(edx
>>24);
109 if (n
< 0x80000006) /* Some chips just has a large L1. */
112 ecx
= cpuid_ecx(0x80000006);
115 /* do processor-specific cache resizing */
116 if (this_cpu
->c_size_cache
)
117 l2size
= this_cpu
->c_size_cache(c
,l2size
);
119 /* Allow user to override all this if necessary. */
120 if (cachesize_override
!= -1)
121 l2size
= cachesize_override
;
124 return; /* Again, no L2 cache is possible */
126 c
->x86_cache_size
= l2size
;
128 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
132 /* Naming convention should be: <Name> [(<Codename>)] */
133 /* This table only is used unless init_<vendor>() below doesn't set it; */
134 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
136 /* Look up CPU names by table lookup. */
137 static char __cpuinit
*table_lookup_model(struct cpuinfo_x86
*c
)
139 struct cpu_model_info
*info
;
141 if ( c
->x86_model
>= 16 )
142 return NULL
; /* Range check */
147 info
= this_cpu
->c_models
;
149 while (info
&& info
->family
) {
150 if (info
->family
== c
->x86
)
151 return info
->model_names
[c
->x86_model
];
154 return NULL
; /* Not found */
158 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
, int early
)
160 char *v
= c
->x86_vendor_id
;
164 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
166 if (!strcmp(v
,cpu_devs
[i
]->c_ident
[0]) ||
167 (cpu_devs
[i
]->c_ident
[1] &&
168 !strcmp(v
,cpu_devs
[i
]->c_ident
[1]))) {
171 this_cpu
= cpu_devs
[i
];
178 printk(KERN_ERR
"CPU: Vendor unknown, using generic init.\n");
179 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
181 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
182 this_cpu
= &default_cpu
;
186 static int __init
x86_fxsr_setup(char * s
)
188 /* Tell all the other CPU's to not use it... */
189 disable_x86_fxsr
= 1;
192 * ... and clear the bits early in the boot_cpu_data
193 * so that the bootup process doesn't try to do this
196 clear_bit(X86_FEATURE_FXSR
, boot_cpu_data
.x86_capability
);
197 clear_bit(X86_FEATURE_XMM
, boot_cpu_data
.x86_capability
);
200 __setup("nofxsr", x86_fxsr_setup
);
203 static int __init
x86_sep_setup(char * s
)
208 __setup("nosep", x86_sep_setup
);
211 /* Standard macro to see if a specific flag is changeable */
212 static inline int flag_is_changeable_p(u32 flag
)
226 : "=&r" (f1
), "=&r" (f2
)
229 return ((f1
^f2
) & flag
) != 0;
233 /* Probe for the CPUID instruction */
234 static int __cpuinit
have_cpuid_p(void)
236 return flag_is_changeable_p(X86_EFLAGS_ID
);
239 /* Do minimum CPU detection early.
240 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
241 The others are not touched to avoid unwanted side effects.
243 WARNING: this function is only called on the BP. Don't add code here
244 that is supposed to run on all CPUs. */
245 static void __init
early_cpu_detect(void)
247 struct cpuinfo_x86
*c
= &boot_cpu_data
;
249 c
->x86_cache_alignment
= 32;
254 /* Get vendor name */
255 cpuid(0x00000000, &c
->cpuid_level
,
256 (int *)&c
->x86_vendor_id
[0],
257 (int *)&c
->x86_vendor_id
[8],
258 (int *)&c
->x86_vendor_id
[4]);
260 get_cpu_vendor(c
, 1);
263 if (c
->cpuid_level
>= 0x00000001) {
264 u32 junk
, tfms
, cap0
, misc
;
265 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
266 c
->x86
= (tfms
>> 8) & 15;
267 c
->x86_model
= (tfms
>> 4) & 15;
269 c
->x86
+= (tfms
>> 20) & 0xff;
271 c
->x86_model
+= ((tfms
>> 16) & 0xF) << 4;
272 c
->x86_mask
= tfms
& 15;
274 c
->x86_cache_alignment
= ((misc
>> 8) & 0xff) * 8;
278 static void __cpuinit
generic_identify(struct cpuinfo_x86
* c
)
283 if (have_cpuid_p()) {
284 /* Get vendor name */
285 cpuid(0x00000000, &c
->cpuid_level
,
286 (int *)&c
->x86_vendor_id
[0],
287 (int *)&c
->x86_vendor_id
[8],
288 (int *)&c
->x86_vendor_id
[4]);
290 get_cpu_vendor(c
, 0);
291 /* Initialize the standard set of capabilities */
292 /* Note that the vendor-specific code below might override */
294 /* Intel-defined flags: level 0x00000001 */
295 if ( c
->cpuid_level
>= 0x00000001 ) {
296 u32 capability
, excap
;
297 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
298 c
->x86_capability
[0] = capability
;
299 c
->x86_capability
[4] = excap
;
300 c
->x86
= (tfms
>> 8) & 15;
301 c
->x86_model
= (tfms
>> 4) & 15;
303 c
->x86
+= (tfms
>> 20) & 0xff;
305 c
->x86_model
+= ((tfms
>> 16) & 0xF) << 4;
306 c
->x86_mask
= tfms
& 15;
308 c
->apicid
= phys_pkg_id((ebx
>> 24) & 0xFF, 0);
310 c
->apicid
= (ebx
>> 24) & 0xFF;
313 /* Have CPUID level 0 only - unheard of */
317 /* AMD-defined flags: level 0x80000001 */
318 xlvl
= cpuid_eax(0x80000000);
319 if ( (xlvl
& 0xffff0000) == 0x80000000 ) {
320 if ( xlvl
>= 0x80000001 ) {
321 c
->x86_capability
[1] = cpuid_edx(0x80000001);
322 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
324 if ( xlvl
>= 0x80000004 )
325 get_model_name(c
); /* Default name */
329 early_intel_workaround(c
);
332 c
->phys_proc_id
= (cpuid_ebx(1) >> 24) & 0xff;
336 static void __cpuinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
338 if (cpu_has(c
, X86_FEATURE_PN
) && disable_x86_serial_nr
) {
339 /* Disable processor serial number */
341 rdmsr(MSR_IA32_BBL_CR_CTL
,lo
,hi
);
343 wrmsr(MSR_IA32_BBL_CR_CTL
,lo
,hi
);
344 printk(KERN_NOTICE
"CPU serial number disabled.\n");
345 clear_bit(X86_FEATURE_PN
, c
->x86_capability
);
347 /* Disabling the serial number may affect the cpuid level */
348 c
->cpuid_level
= cpuid_eax(0);
352 static int __init
x86_serial_nr_setup(char *s
)
354 disable_x86_serial_nr
= 0;
357 __setup("serialnumber", x86_serial_nr_setup
);
362 * This does the hard work of actually picking apart the CPU stuff...
364 void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
368 c
->loops_per_jiffy
= loops_per_jiffy
;
369 c
->x86_cache_size
= -1;
370 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
371 c
->cpuid_level
= -1; /* CPUID not detected */
372 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
373 c
->x86_vendor_id
[0] = '\0'; /* Unset */
374 c
->x86_model_id
[0] = '\0'; /* Unset */
375 c
->x86_max_cores
= 1;
376 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
378 if (!have_cpuid_p()) {
379 /* First of all, decide if this is a 486 or higher */
380 /* It's a 486 if we can modify the AC flag */
381 if ( flag_is_changeable_p(X86_EFLAGS_AC
) )
389 printk(KERN_DEBUG
"CPU: After generic identify, caps:");
390 for (i
= 0; i
< NCAPINTS
; i
++)
391 printk(" %08lx", c
->x86_capability
[i
]);
394 if (this_cpu
->c_identify
) {
395 this_cpu
->c_identify(c
);
397 printk(KERN_DEBUG
"CPU: After vendor identify, caps:");
398 for (i
= 0; i
< NCAPINTS
; i
++)
399 printk(" %08lx", c
->x86_capability
[i
]);
404 * Vendor-specific initialization. In this section we
405 * canonicalize the feature flags, meaning if there are
406 * features a certain CPU supports which CPUID doesn't
407 * tell us, CPUID claiming incorrect flags, or other bugs,
408 * we handle them here.
410 * At the end of this section, c->x86_capability better
411 * indicate the features this CPU genuinely supports!
413 if (this_cpu
->c_init
)
416 /* Disable the PN if appropriate */
417 squash_the_stupid_serial_number(c
);
420 * The vendor-specific functions might have changed features. Now
421 * we do "generic changes."
426 clear_bit(X86_FEATURE_TSC
, c
->x86_capability
);
429 if (disable_x86_fxsr
) {
430 clear_bit(X86_FEATURE_FXSR
, c
->x86_capability
);
431 clear_bit(X86_FEATURE_XMM
, c
->x86_capability
);
436 clear_bit(X86_FEATURE_SEP
, c
->x86_capability
);
439 clear_bit(X86_FEATURE_PSE
, c
->x86_capability
);
441 /* If the model name is still unset, do table lookup. */
442 if ( !c
->x86_model_id
[0] ) {
444 p
= table_lookup_model(c
);
446 strcpy(c
->x86_model_id
, p
);
449 sprintf(c
->x86_model_id
, "%02x/%02x",
450 c
->x86
, c
->x86_model
);
453 /* Now the feature flags better reflect actual CPU features! */
455 printk(KERN_DEBUG
"CPU: After all inits, caps:");
456 for (i
= 0; i
< NCAPINTS
; i
++)
457 printk(" %08lx", c
->x86_capability
[i
]);
461 * On SMP, boot_cpu_data holds the common feature set between
462 * all CPUs; so make sure that we indicate which features are
463 * common between the CPUs. The first time this routine gets
464 * executed, c == &boot_cpu_data.
466 if ( c
!= &boot_cpu_data
) {
467 /* AND the already accumulated flags with these */
468 for ( i
= 0 ; i
< NCAPINTS
; i
++ )
469 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
472 /* Init Machine Check Exception if available. */
475 if (c
== &boot_cpu_data
)
479 if (c
== &boot_cpu_data
)
486 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
488 u32 eax
, ebx
, ecx
, edx
;
489 int index_msb
, core_bits
;
491 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
493 if (!cpu_has(c
, X86_FEATURE_HT
) || cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
496 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
498 if (smp_num_siblings
== 1) {
499 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
500 } else if (smp_num_siblings
> 1 ) {
502 if (smp_num_siblings
> NR_CPUS
) {
503 printk(KERN_WARNING
"CPU: Unsupported number of the "
504 "siblings %d", smp_num_siblings
);
505 smp_num_siblings
= 1;
509 index_msb
= get_count_order(smp_num_siblings
);
510 c
->phys_proc_id
= phys_pkg_id((ebx
>> 24) & 0xFF, index_msb
);
512 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
515 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
517 index_msb
= get_count_order(smp_num_siblings
) ;
519 core_bits
= get_count_order(c
->x86_max_cores
);
521 c
->cpu_core_id
= phys_pkg_id((ebx
>> 24) & 0xFF, index_msb
) &
522 ((1 << core_bits
) - 1);
524 if (c
->x86_max_cores
> 1)
525 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
531 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
535 if (c
->x86_vendor
< X86_VENDOR_NUM
)
536 vendor
= this_cpu
->c_vendor
;
537 else if (c
->cpuid_level
>= 0)
538 vendor
= c
->x86_vendor_id
;
540 if (vendor
&& strncmp(c
->x86_model_id
, vendor
, strlen(vendor
)))
541 printk("%s ", vendor
);
543 if (!c
->x86_model_id
[0])
544 printk("%d86", c
->x86
);
546 printk("%s", c
->x86_model_id
);
548 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
549 printk(" stepping %02x\n", c
->x86_mask
);
554 cpumask_t cpu_initialized __cpuinitdata
= CPU_MASK_NONE
;
557 * We're emulating future behavior.
558 * In the future, the cpu-specific init functions will be called implicitly
559 * via the magic of initcalls.
560 * They will insert themselves into the cpu_devs structure.
561 * Then, when cpu_init() is called, we can just iterate over that array.
564 extern int intel_cpu_init(void);
565 extern int cyrix_init_cpu(void);
566 extern int nsc_init_cpu(void);
567 extern int amd_init_cpu(void);
568 extern int centaur_init_cpu(void);
569 extern int transmeta_init_cpu(void);
570 extern int rise_init_cpu(void);
571 extern int nexgen_init_cpu(void);
572 extern int umc_init_cpu(void);
574 void __init
early_cpu_init(void)
581 transmeta_init_cpu();
587 #ifdef CONFIG_DEBUG_PAGEALLOC
588 /* pse is not compatible with on-the-fly unmapping,
589 * disable it even if the cpus claim to support it.
591 clear_bit(X86_FEATURE_PSE
, boot_cpu_data
.x86_capability
);
596 __cpuinit
int alloc_gdt(int cpu
)
598 struct Xgt_desc_struct
*cpu_gdt_descr
= &per_cpu(cpu_gdt_descr
, cpu
);
599 struct desc_struct
*gdt
;
600 struct i386_pda
*pda
;
602 gdt
= (struct desc_struct
*)cpu_gdt_descr
->address
;
606 * This is a horrible hack to allocate the GDT. The problem
607 * is that cpu_init() is called really early for the boot CPU
608 * (and hence needs bootmem) but much later for the secondary
609 * CPUs, when bootmem will have gone away
611 if (NODE_DATA(0)->bdata
->node_bootmem_map
) {
612 BUG_ON(gdt
!= NULL
|| pda
!= NULL
);
614 gdt
= alloc_bootmem_pages(PAGE_SIZE
);
615 pda
= alloc_bootmem(sizeof(*pda
));
616 /* alloc_bootmem(_pages) panics on failure, so no check */
618 memset(gdt
, 0, PAGE_SIZE
);
619 memset(pda
, 0, sizeof(*pda
));
621 /* GDT and PDA might already have been allocated if
622 this is a CPU hotplug re-insertion. */
624 gdt
= (struct desc_struct
*)get_zeroed_page(GFP_KERNEL
);
627 pda
= kmalloc_node(sizeof(*pda
), GFP_KERNEL
, cpu_to_node(cpu
));
629 if (unlikely(!gdt
|| !pda
)) {
630 free_pages((unsigned long)gdt
, 0);
636 cpu_gdt_descr
->address
= (unsigned long)gdt
;
642 /* Initial PDA used by boot CPU */
643 struct i386_pda boot_pda
= {
647 /* Initialize the CPU's GDT and PDA. The boot CPU does this for
648 itself, but secondaries find this done for them. */
649 __cpuinit
int init_gdt(int cpu
, struct task_struct
*idle
)
651 struct Xgt_desc_struct
*cpu_gdt_descr
= &per_cpu(cpu_gdt_descr
, cpu
);
652 struct desc_struct
*gdt
;
653 struct i386_pda
*pda
;
655 /* For non-boot CPUs, the GDT and PDA should already have been
657 if (!alloc_gdt(cpu
)) {
658 printk(KERN_CRIT
"CPU%d failed to allocate GDT or PDA\n", cpu
);
662 gdt
= (struct desc_struct
*)cpu_gdt_descr
->address
;
665 BUG_ON(gdt
== NULL
|| pda
== NULL
);
668 * Initialize the per-CPU GDT with the boot GDT,
669 * and set up the GDT descriptor:
671 memcpy(gdt
, cpu_gdt_table
, GDT_SIZE
);
672 cpu_gdt_descr
->size
= GDT_SIZE
- 1;
674 pack_descriptor((u32
*)&gdt
[GDT_ENTRY_PDA
].a
,
675 (u32
*)&gdt
[GDT_ENTRY_PDA
].b
,
676 (unsigned long)pda
, sizeof(*pda
) - 1,
677 0x80 | DESCTYPE_S
| 0x2, 0); /* present read-write data segment */
679 memset(pda
, 0, sizeof(*pda
));
685 /* Common CPU init for both boot and secondary CPUs */
686 static void __cpuinit
_cpu_init(int cpu
, struct task_struct
*curr
)
688 struct tss_struct
* t
= &per_cpu(init_tss
, cpu
);
689 struct thread_struct
*thread
= &curr
->thread
;
690 struct Xgt_desc_struct
*cpu_gdt_descr
= &per_cpu(cpu_gdt_descr
, cpu
);
692 /* Reinit these anyway, even if they've already been done (on
693 the boot CPU, this will transition from the boot gdt+pda to
695 load_gdt(cpu_gdt_descr
);
697 if (cpu_test_and_set(cpu
, cpu_initialized
)) {
698 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
699 for (;;) local_irq_enable();
702 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
704 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
705 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
706 if (tsc_disable
&& cpu_has_tsc
) {
707 printk(KERN_NOTICE
"Disabling TSC...\n");
708 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
709 clear_bit(X86_FEATURE_TSC
, boot_cpu_data
.x86_capability
);
710 set_in_cr4(X86_CR4_TSD
);
713 load_idt(&idt_descr
);
716 * Set up and load the per-CPU TSS and LDT
718 atomic_inc(&init_mm
.mm_count
);
719 curr
->active_mm
= &init_mm
;
722 enter_lazy_tlb(&init_mm
, curr
);
724 load_esp0(t
, thread
);
727 load_LDT(&init_mm
.context
);
729 #ifdef CONFIG_DOUBLEFAULT
730 /* Set up doublefault TSS pointer in the GDT */
731 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
734 /* Clear %fs and %gs. */
735 asm volatile ("movl %0, %%fs; movl %0, %%gs" : : "r" (0));
737 /* Clear all 6 debug registers: */
746 * Force FPU initialization:
748 current_thread_info()->status
= 0;
750 mxcsr_feature_mask_init();
753 /* Entrypoint to initialize secondary CPU */
754 void __cpuinit
secondary_cpu_init(void)
756 int cpu
= smp_processor_id();
757 struct task_struct
*curr
= current
;
759 _cpu_init(cpu
, curr
);
763 * cpu_init() initializes state that is per-CPU. Some data is already
764 * initialized (naturally) in the bootstrap process, such as the GDT
765 * and IDT. We reload them nevertheless, this function acts as a
766 * 'CPU state barrier', nothing should get across.
768 void __cpuinit
cpu_init(void)
770 int cpu
= smp_processor_id();
771 struct task_struct
*curr
= current
;
773 /* Set up the real GDT and PDA, so we can transition from the
775 if (!init_gdt(cpu
, curr
)) {
776 /* failed to allocate something; not much we can do... */
781 _cpu_init(cpu
, curr
);
784 #ifdef CONFIG_HOTPLUG_CPU
785 void __cpuinit
cpu_uninit(void)
787 int cpu
= raw_smp_processor_id();
788 cpu_clear(cpu
, cpu_initialized
);
791 per_cpu(cpu_tlbstate
, cpu
).state
= 0;
792 per_cpu(cpu_tlbstate
, cpu
).active_mm
= &init_mm
;