arch/i386/kernel/cpu/cpufreq/longhaul.c

   1 /*
   2  *  (C) 2001-2004  Dave Jones. <davej@codemonkey.org.uk>
   3  *  (C) 2002  Padraig Brady. <padraig@antefacto.com>
   4  *
   5  *  Licensed under the terms of the GNU GPL License version 2.
   6  *  Based upon datasheets & sample CPUs kindly provided by VIA.
   7  *
   8  *  VIA have currently 3 different versions of Longhaul.
   9  *  Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
  10  *   It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
  11  *  Version 2 of longhaul is the same as v1, but adds voltage scaling.
  12  *   Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C)
  13  *   voltage scaling support has currently been disabled in this driver
  14  *   until we have code that gets it right.
  15  *  Version 3 of longhaul got renamed to Powersaver and redesigned
  16  *   to use the POWERSAVER MSR at 0x110a.
  17  *   It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
  18  *   It's pretty much the same feature wise to longhaul v2, though
  19  *   there is provision for scaling FSB too, but this doesn't work
  20  *   too well in practice so we don't even try to use this.
  21  *
  22  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/init.h>
  29 #include <linux/cpufreq.h>
  30 #include <linux/slab.h>
  31 #include <linux/string.h>
  32
  33 #include <asm/msr.h>
  34 #include <asm/timex.h>
  35 #include <asm/io.h>
  36 #include <asm/acpi.h>
  37 #include <linux/acpi.h>
  38 #include <acpi/processor.h>
  39
  40 #include "longhaul.h"
  41
  42 #define PFX "longhaul: "
  43
  44 #define TYPE_LONGHAUL_V1        1
  45 #define TYPE_LONGHAUL_V2        2
  46 #define TYPE_POWERSAVER         3
  47
  48 #define CPU_SAMUEL      1
  49 #define CPU_SAMUEL2     2
  50 #define CPU_EZRA        3
  51 #define CPU_EZRA_T      4
  52 #define CPU_NEHEMIAH    5
  53
  54 static int cpu_model;
  55 static unsigned int numscales=16, numvscales;
  56 static unsigned int fsb;
  57 static int minvid, maxvid;
  58 static unsigned int minmult, maxmult;
  59 static int can_scale_voltage;
  60 static int vrmrev;
  61 static struct acpi_processor *pr = NULL;
  62 static struct acpi_processor_cx *cx = NULL;
  63
  64 /* Module parameters */
  65 static int dont_scale_voltage;
  66
  67
  68 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
  69
  70
  71 /* Clock ratios multiplied by 10 */
  72 static int clock_ratio[32];
  73 static int eblcr_table[32];
  74 static int voltage_table[32];
  75 static unsigned int highest_speed, lowest_speed; /* kHz */
  76 static int longhaul_version;
  77 static struct cpufreq_frequency_table *longhaul_table;
  78
  79 #ifdef CONFIG_CPU_FREQ_DEBUG
  80 static char speedbuffer[8];
  81
  82 static char *print_speed(int speed)
  83 {
  84         if (speed < 1000) {
  85                 snprintf(speedbuffer, sizeof(speedbuffer),"%dMHz", speed);
  86                 return speedbuffer;
  87         }
  88
  89         if (speed%1000 == 0)
  90                 snprintf(speedbuffer, sizeof(speedbuffer),
  91                         "%dGHz", speed/1000);
  92         else
  93                 snprintf(speedbuffer, sizeof(speedbuffer),
  94                         "%d.%dGHz", speed/1000, (speed%1000)/100);
  95
  96         return speedbuffer;
  97 }
  98 #endif
  99
 100
 101 static unsigned int calc_speed(int mult)
 102 {
 103         int khz;
 104         khz = (mult/10)*fsb;
 105         if (mult%10)
 106                 khz += fsb/2;
 107         khz *= 1000;
 108         return khz;
 109 }
 110
 111
 112 static int longhaul_get_cpu_mult(void)
 113 {
 114         unsigned long invalue=0,lo, hi;
 115
 116         rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
 117         invalue = (lo & (1<<22|1<<23|1<<24|1<<25)) >>22;
 118         if (longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) {
 119                 if (lo & (1<<27))
 120                         invalue+=16;
 121         }
 122         return eblcr_table[invalue];
 123 }
 124
 125 /* For processor with BCR2 MSR */
 126
 127 static void do_longhaul1(int cx_address, unsigned int clock_ratio_index)
 128 {
 129         union msr_bcr2 bcr2;
 130         u32 t;
 131
 132         rdmsrl(MSR_VIA_BCR2, bcr2.val);
 133         /* Enable software clock multiplier */
 134         bcr2.bits.ESOFTBF = 1;
 135         bcr2.bits.CLOCKMUL = clock_ratio_index;
 136
 137         /* Sync to timer tick */
 138         safe_halt();
 139         ACPI_FLUSH_CPU_CACHE();
 140         /* Change frequency on next halt or sleep */
 141         wrmsrl(MSR_VIA_BCR2, bcr2.val);
 142         /* Invoke C3 */
 143         inb(cx_address);
 144         /* Dummy op - must do something useless after P_LVL3 read */
 145         t = inl(acpi_fadt.xpm_tmr_blk.address);
 146
 147         /* Disable software clock multiplier */
 148         local_irq_disable();
 149         rdmsrl(MSR_VIA_BCR2, bcr2.val);
 150         bcr2.bits.ESOFTBF = 0;
 151         wrmsrl(MSR_VIA_BCR2, bcr2.val);
 152 }
 153
 154 /* For processor with Longhaul MSR */
 155
 156 static void do_powersaver(int cx_address, unsigned int clock_ratio_index)
 157 {
 158         union msr_longhaul longhaul;
 159         u32 t;
 160
 161         rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 162         longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
 163         longhaul.bits.SoftBusRatio = clock_ratio_index & 0xf;
 164         longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
 165         longhaul.bits.EnableSoftBusRatio = 1;
 166
 167         /* Sync to timer tick */
 168         safe_halt();
 169         ACPI_FLUSH_CPU_CACHE();
 170         /* Change frequency on next halt or sleep */
 171         wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 172         /* Invoke C3 */
 173         inb(cx_address);
 174         /* Dummy op - must do something useless after P_LVL3 read */
 175         t = inl(acpi_fadt.xpm_tmr_blk.address);
 176
 177         /* Disable bus ratio bit */
 178         local_irq_disable();
 179         longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
 180         longhaul.bits.EnableSoftBusRatio = 0;
 181         longhaul.bits.EnableSoftBSEL = 0;
 182         longhaul.bits.EnableSoftVID = 0;
 183         wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 184 }
 185
 186 /**
 187  * longhaul_set_cpu_frequency()
 188  * @clock_ratio_index : bitpattern of the new multiplier.
 189  *
 190  * Sets a new clock ratio.
 191  */
 192
 193 static void longhaul_setstate(unsigned int clock_ratio_index)
 194 {
 195         int speed, mult;
 196         struct cpufreq_freqs freqs;
 197         static unsigned int old_ratio=-1;
 198         unsigned long flags;
 199         unsigned int pic1_mask, pic2_mask;
 200
 201         if (old_ratio == clock_ratio_index)
 202                 return;
 203         old_ratio = clock_ratio_index;
 204
 205         mult = clock_ratio[clock_ratio_index];
 206         if (mult == -1)
 207                 return;
 208
 209         speed = calc_speed(mult);
 210         if ((speed > highest_speed) || (speed < lowest_speed))
 211                 return;
 212
 213         freqs.old = calc_speed(longhaul_get_cpu_mult());
 214         freqs.new = speed;
 215         freqs.cpu = 0; /* longhaul.c is UP only driver */
 216
 217         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 218
 219         dprintk ("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
 220                         fsb, mult/10, mult%10, print_speed(speed/1000));
 221
 222         preempt_disable();
 223         local_irq_save(flags);
 224
 225         pic2_mask = inb(0xA1);
 226         pic1_mask = inb(0x21);  /* works on C3. save mask. */
 227         outb(0xFF,0xA1);        /* Overkill */
 228         outb(0xFE,0x21);        /* TMR0 only */
 229
 230         /* Disable bus master arbitration */
 231         if (pr->flags.bm_check) {
 232                 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1,
 233                                   ACPI_MTX_DO_NOT_LOCK);
 234         }
 235
 236         switch (longhaul_version) {
 237
 238         /*
 239          * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
 240          * Software controlled multipliers only.
 241          *
 242          * *NB* Until we get voltage scaling working v1 & v2 are the same code.
 243          * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5b] and Ezra [C5C]
 244          */
 245         case TYPE_LONGHAUL_V1:
 246         case TYPE_LONGHAUL_V2:
 247                 do_longhaul1(cx->address, clock_ratio_index);
 248                 break;
 249
 250         /*
 251          * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
 252          * We can scale voltage with this too, but that's currently
 253          * disabled until we come up with a decent 'match freq to voltage'
 254          * algorithm.
 255          * When we add voltage scaling, we will also need to do the
 256          * voltage/freq setting in order depending on the direction
 257          * of scaling (like we do in powernow-k7.c)
 258          * Nehemiah can do FSB scaling too, but this has never been proven
 259          * to work in practice.
 260          */
 261         case TYPE_POWERSAVER:
 262                 do_powersaver(cx->address, clock_ratio_index);
 263                 break;
 264         }
 265
 266         /* Enable bus master arbitration */
 267         if (pr->flags.bm_check) {
 268                 acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0,
 269                                   ACPI_MTX_DO_NOT_LOCK);
 270         }
 271
 272         outb(pic2_mask,0xA1);   /* restore mask */
 273         outb(pic1_mask,0x21);
 274
 275         local_irq_restore(flags);
 276         preempt_enable();
 277
 278         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 279 }
 280
 281 /*
 282  * Centaur decided to make life a little more tricky.
 283  * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
 284  * Samuel2 and above have to try and guess what the FSB is.
 285  * We do this by assuming we booted at maximum multiplier, and interpolate
 286  * between that value multiplied by possible FSBs and cpu_mhz which
 287  * was calculated at boot time. Really ugly, but no other way to do this.
 288  */
 289
 290 #define ROUNDING        0xf
 291
 292 static int _guess(int guess)
 293 {
 294         int target;
 295
 296         target = ((maxmult/10)*guess);
 297         if (maxmult%10 != 0)
 298                 target += (guess/2);
 299         target += ROUNDING/2;
 300         target &= ~ROUNDING;
 301         return target;
 302 }
 303
 304
 305 static int guess_fsb(void)
 306 {
 307         int speed = (cpu_khz/1000);
 308         int i;
 309         int speeds[3] = { 66, 100, 133 };
 310
 311         speed += ROUNDING/2;
 312         speed &= ~ROUNDING;
 313
 314         for (i=0; i<3; i++) {
 315                 if (_guess(speeds[i]) == speed)
 316                         return speeds[i];
 317         }
 318         return 0;
 319 }
 320
 321
 322 static int __init longhaul_get_ranges(void)
 323 {
 324         unsigned long invalue;
 325         unsigned int ezra_t_multipliers[32]= {
 326                         90,  30,  40, 100,  55,  35,  45,  95,
 327                         50,  70,  80,  60, 120,  75,  85,  65,
 328                         -1, 110, 120,  -1, 135, 115, 125, 105,
 329                         130, 150, 160, 140,  -1, 155,  -1, 145 };
 330         unsigned int j, k = 0;
 331         union msr_longhaul longhaul;
 332         unsigned long lo, hi;
 333         unsigned int eblcr_fsb_table_v1[] = { 66, 133, 100, -1 };
 334         unsigned int eblcr_fsb_table_v2[] = { 133, 100, -1, 66 };
 335
 336         switch (longhaul_version) {
 337         case TYPE_LONGHAUL_V1:
 338         case TYPE_LONGHAUL_V2:
 339                 /* Ugh, Longhaul v1 didn't have the min/max MSRs.
 340                    Assume min=3.0x & max = whatever we booted at. */
 341                 minmult = 30;
 342                 maxmult = longhaul_get_cpu_mult();
 343                 rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
 344                 invalue = (lo & (1<<18|1<<19)) >>18;
 345                 if (cpu_model==CPU_SAMUEL || cpu_model==CPU_SAMUEL2)
 346                         fsb = eblcr_fsb_table_v1[invalue];
 347                 else
 348                         fsb = guess_fsb();
 349                 break;
 350
 351         case TYPE_POWERSAVER:
 352                 /* Ezra-T */
 353                 if (cpu_model==CPU_EZRA_T) {
 354                         rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
 355                         invalue = longhaul.bits.MaxMHzBR;
 356                         if (longhaul.bits.MaxMHzBR4)
 357                                 invalue += 16;
 358                         maxmult=ezra_t_multipliers[invalue];
 359
 360                         invalue = longhaul.bits.MinMHzBR;
 361                         if (longhaul.bits.MinMHzBR4 == 1)
 362                                 minmult = 30;
 363                         else
 364                                 minmult = ezra_t_multipliers[invalue];
 365                         fsb = eblcr_fsb_table_v2[longhaul.bits.MaxMHzFSB];
 366                         break;
 367                 }
 368
 369                 /* Nehemiah */
 370                 if (cpu_model==CPU_NEHEMIAH) {
 371                         rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
 372
 373                         /*
 374                          * TODO: This code works, but raises a lot of questions.
 375                          * - Some Nehemiah's seem to have broken Min/MaxMHzBR's.
 376                          *   We get around this by using a hardcoded multiplier of 4.0x
 377                          *   for the minimimum speed, and the speed we booted up at for the max.
 378                          *   This is done in longhaul_get_cpu_mult() by reading the EBLCR register.
 379                          * - According to some VIA documentation EBLCR is only
 380                          *   in pre-Nehemiah C3s. How this still works is a mystery.
 381                          *   We're possibly using something undocumented and unsupported,
 382                          *   But it works, so we don't grumble.
 383                          */
 384                         minmult=40;
 385                         maxmult=longhaul_get_cpu_mult();
 386
 387                         /* Starting with the 1.2GHz parts, theres a 200MHz bus. */
 388                         if ((cpu_khz/1000) > 1200)
 389                                 fsb = 200;
 390                         else
 391                                 fsb = eblcr_fsb_table_v2[longhaul.bits.MaxMHzFSB];
 392                         break;
 393                 }
 394         }
 395
 396         dprintk ("MinMult:%d.%dx MaxMult:%d.%dx\n",
 397                  minmult/10, minmult%10, maxmult/10, maxmult%10);
 398
 399         if (fsb == -1) {
 400                 printk (KERN_INFO PFX "Invalid (reserved) FSB!\n");
 401                 return -EINVAL;
 402         }
 403
 404         highest_speed = calc_speed(maxmult);
 405         lowest_speed = calc_speed(minmult);
 406         dprintk ("FSB:%dMHz  Lowest speed: %s   Highest speed:%s\n", fsb,
 407                  print_speed(lowest_speed/1000),
 408                  print_speed(highest_speed/1000));
 409
 410         if (lowest_speed == highest_speed) {
 411                 printk (KERN_INFO PFX "highestspeed == lowest, aborting.\n");
 412                 return -EINVAL;
 413         }
 414         if (lowest_speed > highest_speed) {
 415                 printk (KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
 416                         lowest_speed, highest_speed);
 417                 return -EINVAL;
 418         }
 419
 420         longhaul_table = kmalloc((numscales + 1) * sizeof(struct cpufreq_frequency_table), GFP_KERNEL);
 421         if(!longhaul_table)
 422                 return -ENOMEM;
 423
 424         for (j=0; j < numscales; j++) {
 425                 unsigned int ratio;
 426                 ratio = clock_ratio[j];
 427                 if (ratio == -1)
 428                         continue;
 429                 if (ratio > maxmult || ratio < minmult)
 430                         continue;
 431                 longhaul_table[k].frequency = calc_speed(ratio);
 432                 longhaul_table[k].index = j;
 433                 k++;
 434         }
 435
 436         longhaul_table[k].frequency = CPUFREQ_TABLE_END;
 437         if (!k) {
 438                 kfree (longhaul_table);
 439                 return -EINVAL;
 440         }
 441
 442         return 0;
 443 }
 444
 445
 446 static void __init longhaul_setup_voltagescaling(void)
 447 {
 448         union msr_longhaul longhaul;
 449
 450         rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
 451
 452         if (!(longhaul.bits.RevisionID & 1))
 453                 return;
 454
 455         minvid = longhaul.bits.MinimumVID;
 456         maxvid = longhaul.bits.MaximumVID;
 457         vrmrev = longhaul.bits.VRMRev;
 458
 459         if (minvid == 0 || maxvid == 0) {
 460                 printk (KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
 461                                         "Voltage scaling disabled.\n",
 462                                         minvid/1000, minvid%1000, maxvid/1000, maxvid%1000);
 463                 return;
 464         }
 465
 466         if (minvid == maxvid) {
 467                 printk (KERN_INFO PFX "Claims to support voltage scaling but min & max are "
 468                                 "both %d.%03d. Voltage scaling disabled\n",
 469                                 maxvid/1000, maxvid%1000);
 470                 return;
 471         }
 472
 473         if (vrmrev==0) {
 474                 dprintk ("VRM 8.5\n");
 475                 memcpy (voltage_table, vrm85scales, sizeof(voltage_table));
 476                 numvscales = (voltage_table[maxvid]-voltage_table[minvid])/25;
 477         } else {
 478                 dprintk ("Mobile VRM\n");
 479                 memcpy (voltage_table, mobilevrmscales, sizeof(voltage_table));
 480                 numvscales = (voltage_table[maxvid]-voltage_table[minvid])/5;
 481         }
 482
 483         /* Current voltage isn't readable at first, so we need to
 484            set it to a known value. The spec says to use maxvid */
 485         longhaul.bits.RevisionKey = longhaul.bits.RevisionID;   /* FIXME: This is bad. */
 486         longhaul.bits.EnableSoftVID = 1;
 487         longhaul.bits.SoftVID = maxvid;
 488         wrmsrl (MSR_VIA_LONGHAUL, longhaul.val);
 489
 490         minvid = voltage_table[minvid];
 491         maxvid = voltage_table[maxvid];
 492
 493         dprintk ("Min VID=%d.%03d Max VID=%d.%03d, %d possible voltage scales\n",
 494                 maxvid/1000, maxvid%1000, minvid/1000, minvid%1000, numvscales);
 495
 496         can_scale_voltage = 1;
 497 }
 498
 499
 500 static int longhaul_verify(struct cpufreq_policy *policy)
 501 {
 502         return cpufreq_frequency_table_verify(policy, longhaul_table);
 503 }
 504
 505
 506 static int longhaul_target(struct cpufreq_policy *policy,
 507                             unsigned int target_freq, unsigned int relation)
 508 {
 509         unsigned int table_index = 0;
 510         unsigned int new_clock_ratio = 0;
 511
 512         if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index))
 513                 return -EINVAL;
 514
 515         new_clock_ratio = longhaul_table[table_index].index & 0xFF;
 516
 517         longhaul_setstate(new_clock_ratio);
 518
 519         return 0;
 520 }
 521
 522
 523 static unsigned int longhaul_get(unsigned int cpu)
 524 {
 525         if (cpu)
 526                 return 0;
 527         return calc_speed(longhaul_get_cpu_mult());
 528 }
 529
 530 static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
 531                                           u32 nesting_level,
 532                                           void *context, void **return_value)
 533 {
 534         struct acpi_device *d;
 535
 536         if ( acpi_bus_get_device(obj_handle, &d) ) {
 537                 return 0;
 538         }
 539         *return_value = (void *)acpi_driver_data(d);
 540         return 1;
 541 }
 542
 543 static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
 544 {
 545         struct cpuinfo_x86 *c = cpu_data;
 546         char *cpuname=NULL;
 547         int ret;
 548
 549         /* Check ACPI support for C3 state */
 550         acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT, ACPI_UINT32_MAX,
 551                          &longhaul_walk_callback, NULL, (void *)&pr);
 552         if (pr == NULL) goto err_acpi;
 553
 554         cx = &pr->power.states[ACPI_STATE_C3];
 555         if (cx->address == 0 || cx->latency > 1000) goto err_acpi;
 556
 557         /* Now check what we have on this motherboard */
 558         switch (c->x86_model) {
 559         case 6:
 560                 cpu_model = CPU_SAMUEL;
 561                 cpuname = "C3 'Samuel' [C5A]";
 562                 longhaul_version = TYPE_LONGHAUL_V1;
 563                 memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
 564                 memcpy (eblcr_table, samuel1_eblcr, sizeof(samuel1_eblcr));
 565                 break;
 566
 567         case 7:
 568                 longhaul_version = TYPE_LONGHAUL_V1;
 569                 switch (c->x86_mask) {
 570                 case 0:
 571                         cpu_model = CPU_SAMUEL2;
 572                         cpuname = "C3 'Samuel 2' [C5B]";
 573                         /* Note, this is not a typo, early Samuel2's had Samuel1 ratios. */
 574                         memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
 575                         memcpy (eblcr_table, samuel2_eblcr, sizeof(samuel2_eblcr));
 576                         break;
 577                 case 1 ... 15:
 578                         if (c->x86_mask < 8) {
 579                                 cpu_model = CPU_SAMUEL2;
 580                                 cpuname = "C3 'Samuel 2' [C5B]";
 581                         } else {
 582                                 cpu_model = CPU_EZRA;
 583                                 cpuname = "C3 'Ezra' [C5C]";
 584                         }
 585                         memcpy (clock_ratio, ezra_clock_ratio, sizeof(ezra_clock_ratio));
 586                         memcpy (eblcr_table, ezra_eblcr, sizeof(ezra_eblcr));
 587                         break;
 588                 }
 589                 break;
 590
 591         case 8:
 592                 cpu_model = CPU_EZRA_T;
 593                 cpuname = "C3 'Ezra-T' [C5M]";
 594                 longhaul_version = TYPE_POWERSAVER;
 595                 numscales=32;
 596                 memcpy (clock_ratio, ezrat_clock_ratio, sizeof(ezrat_clock_ratio));
 597                 memcpy (eblcr_table, ezrat_eblcr, sizeof(ezrat_eblcr));
 598                 break;
 599
 600         case 9:
 601                 cpu_model = CPU_NEHEMIAH;
 602                 longhaul_version = TYPE_POWERSAVER;
 603                 numscales=32;
 604                 switch (c->x86_mask) {
 605                 case 0 ... 1:
 606                         cpuname = "C3 'Nehemiah A' [C5N]";
 607                         memcpy (clock_ratio, nehemiah_a_clock_ratio, sizeof(nehemiah_a_clock_ratio));
 608                         memcpy (eblcr_table, nehemiah_a_eblcr, sizeof(nehemiah_a_eblcr));
 609                         break;
 610                 case 2 ... 4:
 611                         cpuname = "C3 'Nehemiah B' [C5N]";
 612                         memcpy (clock_ratio, nehemiah_b_clock_ratio, sizeof(nehemiah_b_clock_ratio));
 613                         memcpy (eblcr_table, nehemiah_b_eblcr, sizeof(nehemiah_b_eblcr));
 614                         break;
 615                 case 5 ... 15:
 616                         cpuname = "C3 'Nehemiah C' [C5N]";
 617                         memcpy (clock_ratio, nehemiah_c_clock_ratio, sizeof(nehemiah_c_clock_ratio));
 618                         memcpy (eblcr_table, nehemiah_c_eblcr, sizeof(nehemiah_c_eblcr));
 619                         break;
 620                 }
 621                 break;
 622
 623         default:
 624                 cpuname = "Unknown";
 625                 break;
 626         }
 627
 628         printk (KERN_INFO PFX "VIA %s CPU detected.  ", cpuname);
 629         switch (longhaul_version) {
 630         case TYPE_LONGHAUL_V1:
 631         case TYPE_LONGHAUL_V2:
 632                 printk ("Longhaul v%d supported.\n", longhaul_version);
 633                 break;
 634         case TYPE_POWERSAVER:
 635                 printk ("Powersaver supported.\n");
 636                 break;
 637         };
 638
 639         ret = longhaul_get_ranges();
 640         if (ret != 0)
 641                 return ret;
 642
 643         if ((longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) &&
 644                  (dont_scale_voltage==0))
 645                 longhaul_setup_voltagescaling();
 646
 647         policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
 648         policy->cpuinfo.transition_latency = 200000;    /* nsec */
 649         policy->cur = calc_speed(longhaul_get_cpu_mult());
 650
 651         ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
 652         if (ret)
 653                 return ret;
 654
 655         cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
 656
 657         return 0;
 658
 659 err_acpi:
 660         printk(KERN_ERR PFX "No ACPI support for CPU frequency changes.\n");
 661         return -ENODEV;
 662 }
 663
 664 static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
 665 {
 666         cpufreq_frequency_table_put_attr(policy->cpu);
 667         return 0;
 668 }
 669
 670 static struct freq_attr* longhaul_attr[] = {
 671         &cpufreq_freq_attr_scaling_available_freqs,
 672         NULL,
 673 };
 674
 675 static struct cpufreq_driver longhaul_driver = {
 676         .verify = longhaul_verify,
 677         .target = longhaul_target,
 678         .get    = longhaul_get,
 679         .init   = longhaul_cpu_init,
 680         .exit   = __devexit_p(longhaul_cpu_exit),
 681         .name   = "longhaul",
 682         .owner  = THIS_MODULE,
 683         .attr   = longhaul_attr,
 684 };
 685
 686
 687 static int __init longhaul_init(void)
 688 {
 689         struct cpuinfo_x86 *c = cpu_data;
 690
 691         if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
 692                 return -ENODEV;
 693
 694 #ifdef CONFIG_SMP
 695         if (num_online_cpus() > 1) {
 696                 return -ENODEV;
 697                 printk(KERN_ERR PFX "More than 1 CPU detected, longhaul disabled.\n");
 698         }
 699 #endif
 700 #ifdef CONFIG_X86_IO_APIC
 701         if (cpu_has_apic) {
 702                 printk(KERN_ERR PFX "APIC detected. Longhaul is currently broken in this configuration.\n");
 703                 return -ENODEV;
 704         }
 705 #endif
 706         switch (c->x86_model) {
 707         case 6 ... 9:
 708                 return cpufreq_register_driver(&longhaul_driver);
 709         default:
 710                 printk (KERN_INFO PFX "Unknown VIA CPU. Contact davej@codemonkey.org.uk\n");
 711         }
 712
 713         return -ENODEV;
 714 }
 715
 716
 717 static void __exit longhaul_exit(void)
 718 {
 719         int i;
 720
 721         for (i=0; i < numscales; i++) {
 722                 if (clock_ratio[i] == maxmult) {
 723                         longhaul_setstate(i);
 724                         break;
 725                 }
 726         }
 727
 728         cpufreq_unregister_driver(&longhaul_driver);
 729         kfree(longhaul_table);
 730 }
 731
 732 module_param (dont_scale_voltage, int, 0644);
 733 MODULE_PARM_DESC(dont_scale_voltage, "Don't scale voltage of processor");
 734
 735 MODULE_AUTHOR ("Dave Jones <davej@codemonkey.org.uk>");
 736 MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors.");
 737 MODULE_LICENSE ("GPL");
 738
 739 late_initcall(longhaul_init);
 740 module_exit(longhaul_exit);
 741