2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
41 #include <asm/timer.h>
42 #include <asm/i8259.h>
44 #include <asm/msidef.h>
45 #include <asm/hypertransport.h>
47 #include <mach_apic.h>
48 #include <mach_apicdef.h>
52 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
53 atomic_t irq_mis_count
;
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
58 static DEFINE_SPINLOCK(ioapic_lock
);
59 static DEFINE_SPINLOCK(vector_lock
);
61 int timer_over_8254 __initdata
= 1;
64 * Is the SiS APIC rmw bug present ?
65 * -1 = don't know, 0 = no, 1 = yes
67 int sis_apic_bug
= -1;
70 * # of IRQ routing registers
72 int nr_ioapic_registers
[MAX_IO_APICS
];
74 static int disable_timer_pin_1 __initdata
;
77 * Rough estimation of how many shared IRQs there are, can
80 #define MAX_PLUS_SHARED_IRQS NR_IRQS
81 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
84 * This is performance-critical, we want to do it O(1)
86 * the indexing order of this array favors 1:1 mappings
87 * between pins and IRQs.
90 static struct irq_pin_list
{
92 } irq_2_pin
[PIN_MAP_SIZE
];
96 unsigned int unused
[3];
100 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
102 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
103 + (mp_ioapics
[idx
].mpc_apicaddr
& ~PAGE_MASK
);
106 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
108 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
109 writel(reg
, &io_apic
->index
);
110 return readl(&io_apic
->data
);
113 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
115 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
116 writel(reg
, &io_apic
->index
);
117 writel(value
, &io_apic
->data
);
121 * Re-write a value: to be used for read-modify-write
122 * cycles where the read already set up the index register.
124 * Older SiS APIC requires we rewrite the index register
126 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
128 volatile struct io_apic
*io_apic
= io_apic_base(apic
);
130 writel(reg
, &io_apic
->index
);
131 writel(value
, &io_apic
->data
);
135 struct { u32 w1
, w2
; };
136 struct IO_APIC_route_entry entry
;
139 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
141 union entry_union eu
;
143 spin_lock_irqsave(&ioapic_lock
, flags
);
144 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
145 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
146 spin_unlock_irqrestore(&ioapic_lock
, flags
);
150 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
153 union entry_union eu
;
155 spin_lock_irqsave(&ioapic_lock
, flags
);
156 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
157 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
158 spin_unlock_irqrestore(&ioapic_lock
, flags
);
162 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
163 * shared ISA-space IRQs, so we have to support them. We are super
164 * fast in the common case, and fast for shared ISA-space IRQs.
166 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
168 static int first_free_entry
= NR_IRQS
;
169 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
172 entry
= irq_2_pin
+ entry
->next
;
174 if (entry
->pin
!= -1) {
175 entry
->next
= first_free_entry
;
176 entry
= irq_2_pin
+ entry
->next
;
177 if (++first_free_entry
>= PIN_MAP_SIZE
)
178 panic("io_apic.c: whoops");
185 * Reroute an IRQ to a different pin.
187 static void __init
replace_pin_at_irq(unsigned int irq
,
188 int oldapic
, int oldpin
,
189 int newapic
, int newpin
)
191 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
194 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
195 entry
->apic
= newapic
;
200 entry
= irq_2_pin
+ entry
->next
;
204 static void __modify_IO_APIC_irq (unsigned int irq
, unsigned long enable
, unsigned long disable
)
206 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
207 unsigned int pin
, reg
;
213 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
216 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
219 entry
= irq_2_pin
+ entry
->next
;
224 static void __mask_IO_APIC_irq (unsigned int irq
)
226 __modify_IO_APIC_irq(irq
, 0x00010000, 0);
230 static void __unmask_IO_APIC_irq (unsigned int irq
)
232 __modify_IO_APIC_irq(irq
, 0, 0x00010000);
235 /* mask = 1, trigger = 0 */
236 static void __mask_and_edge_IO_APIC_irq (unsigned int irq
)
238 __modify_IO_APIC_irq(irq
, 0x00010000, 0x00008000);
241 /* mask = 0, trigger = 1 */
242 static void __unmask_and_level_IO_APIC_irq (unsigned int irq
)
244 __modify_IO_APIC_irq(irq
, 0x00008000, 0x00010000);
247 static void mask_IO_APIC_irq (unsigned int irq
)
251 spin_lock_irqsave(&ioapic_lock
, flags
);
252 __mask_IO_APIC_irq(irq
);
253 spin_unlock_irqrestore(&ioapic_lock
, flags
);
256 static void unmask_IO_APIC_irq (unsigned int irq
)
260 spin_lock_irqsave(&ioapic_lock
, flags
);
261 __unmask_IO_APIC_irq(irq
);
262 spin_unlock_irqrestore(&ioapic_lock
, flags
);
265 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
267 struct IO_APIC_route_entry entry
;
269 /* Check delivery_mode to be sure we're not clearing an SMI pin */
270 entry
= ioapic_read_entry(apic
, pin
);
271 if (entry
.delivery_mode
== dest_SMI
)
275 * Disable it in the IO-APIC irq-routing table:
277 memset(&entry
, 0, sizeof(entry
));
279 ioapic_write_entry(apic
, pin
, entry
);
282 static void clear_IO_APIC (void)
286 for (apic
= 0; apic
< nr_ioapics
; apic
++)
287 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
288 clear_IO_APIC_pin(apic
, pin
);
292 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
296 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
297 unsigned int apicid_value
;
300 cpus_and(tmp
, cpumask
, cpu_online_map
);
304 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
306 apicid_value
= cpu_mask_to_apicid(cpumask
);
307 /* Prepare to do the io_apic_write */
308 apicid_value
= apicid_value
<< 24;
309 spin_lock_irqsave(&ioapic_lock
, flags
);
314 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
317 entry
= irq_2_pin
+ entry
->next
;
319 set_native_irq_info(irq
, cpumask
);
320 spin_unlock_irqrestore(&ioapic_lock
, flags
);
323 #if defined(CONFIG_IRQBALANCE)
324 # include <asm/processor.h> /* kernel_thread() */
325 # include <linux/kernel_stat.h> /* kstat */
326 # include <linux/slab.h> /* kmalloc() */
327 # include <linux/timer.h> /* time_after() */
329 #ifdef CONFIG_BALANCED_IRQ_DEBUG
330 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
331 # define Dprintk(x...) do { TDprintk(x); } while (0)
333 # define TDprintk(x...)
334 # define Dprintk(x...)
337 #define IRQBALANCE_CHECK_ARCH -999
338 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
339 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
340 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
341 #define BALANCED_IRQ_LESS_DELTA (HZ)
343 static int irqbalance_disabled __read_mostly
= IRQBALANCE_CHECK_ARCH
;
344 static int physical_balance __read_mostly
;
345 static long balanced_irq_interval __read_mostly
= MAX_BALANCED_IRQ_INTERVAL
;
347 static struct irq_cpu_info
{
348 unsigned long * last_irq
;
349 unsigned long * irq_delta
;
351 } irq_cpu_data
[NR_CPUS
];
353 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
354 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
355 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
357 #define IDLE_ENOUGH(cpu,now) \
358 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
360 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
362 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
364 static cpumask_t balance_irq_affinity
[NR_IRQS
] = {
365 [0 ... NR_IRQS
-1] = CPU_MASK_ALL
368 void set_balance_irq_affinity(unsigned int irq
, cpumask_t mask
)
370 balance_irq_affinity
[irq
] = mask
;
373 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
374 unsigned long now
, int direction
)
382 if (unlikely(cpu
== curr_cpu
))
385 if (direction
== 1) {
394 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
,allowed_mask
) ||
395 (search_idle
&& !IDLE_ENOUGH(cpu
,now
)));
400 static inline void balance_irq(int cpu
, int irq
)
402 unsigned long now
= jiffies
;
403 cpumask_t allowed_mask
;
404 unsigned int new_cpu
;
406 if (irqbalance_disabled
)
409 cpus_and(allowed_mask
, cpu_online_map
, balance_irq_affinity
[irq
]);
410 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
411 if (cpu
!= new_cpu
) {
412 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
416 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
419 Dprintk("Rotating IRQs among CPUs.\n");
420 for_each_online_cpu(i
) {
421 for (j
= 0; j
< NR_IRQS
; j
++) {
422 if (!irq_desc
[j
].action
)
424 /* Is it a significant load ? */
425 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
),j
) <
426 useful_load_threshold
)
431 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
432 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
436 static void do_irq_balance(void)
439 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
440 unsigned long move_this_load
= 0;
441 int max_loaded
= 0, min_loaded
= 0;
443 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
445 int tmp_loaded
, first_attempt
= 1;
446 unsigned long tmp_cpu_irq
;
447 unsigned long imbalance
= 0;
448 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
450 for_each_possible_cpu(i
) {
455 package_index
= CPU_TO_PACKAGEINDEX(i
);
456 for (j
= 0; j
< NR_IRQS
; j
++) {
457 unsigned long value_now
, delta
;
458 /* Is this an active IRQ? */
459 if (!irq_desc
[j
].action
)
461 if ( package_index
== i
)
462 IRQ_DELTA(package_index
,j
) = 0;
463 /* Determine the total count per processor per IRQ */
464 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
466 /* Determine the activity per processor per IRQ */
467 delta
= value_now
- LAST_CPU_IRQ(i
,j
);
469 /* Update last_cpu_irq[][] for the next time */
470 LAST_CPU_IRQ(i
,j
) = value_now
;
472 /* Ignore IRQs whose rate is less than the clock */
473 if (delta
< useful_load_threshold
)
475 /* update the load for the processor or package total */
476 IRQ_DELTA(package_index
,j
) += delta
;
478 /* Keep track of the higher numbered sibling as well */
479 if (i
!= package_index
)
482 * We have sibling A and sibling B in the package
484 * cpu_irq[A] = load for cpu A + load for cpu B
485 * cpu_irq[B] = load for cpu B
487 CPU_IRQ(package_index
) += delta
;
490 /* Find the least loaded processor package */
491 for_each_online_cpu(i
) {
492 if (i
!= CPU_TO_PACKAGEINDEX(i
))
494 if (min_cpu_irq
> CPU_IRQ(i
)) {
495 min_cpu_irq
= CPU_IRQ(i
);
499 max_cpu_irq
= ULONG_MAX
;
502 /* Look for heaviest loaded processor.
503 * We may come back to get the next heaviest loaded processor.
504 * Skip processors with trivial loads.
508 for_each_online_cpu(i
) {
509 if (i
!= CPU_TO_PACKAGEINDEX(i
))
511 if (max_cpu_irq
<= CPU_IRQ(i
))
513 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
514 tmp_cpu_irq
= CPU_IRQ(i
);
519 if (tmp_loaded
== -1) {
520 /* In the case of small number of heavy interrupt sources,
521 * loading some of the cpus too much. We use Ingo's original
522 * approach to rotate them around.
524 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
525 rotate_irqs_among_cpus(useful_load_threshold
);
528 goto not_worth_the_effort
;
531 first_attempt
= 0; /* heaviest search */
532 max_cpu_irq
= tmp_cpu_irq
; /* load */
533 max_loaded
= tmp_loaded
; /* processor */
534 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
536 Dprintk("max_loaded cpu = %d\n", max_loaded
);
537 Dprintk("min_loaded cpu = %d\n", min_loaded
);
538 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq
);
539 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq
);
540 Dprintk("load imbalance = %lu\n", imbalance
);
542 /* if imbalance is less than approx 10% of max load, then
543 * observe diminishing returns action. - quit
545 if (imbalance
< (max_cpu_irq
>> 3)) {
546 Dprintk("Imbalance too trivial\n");
547 goto not_worth_the_effort
;
551 /* if we select an IRQ to move that can't go where we want, then
552 * see if there is another one to try.
556 for (j
= 0; j
< NR_IRQS
; j
++) {
557 /* Is this an active IRQ? */
558 if (!irq_desc
[j
].action
)
560 if (imbalance
<= IRQ_DELTA(max_loaded
,j
))
562 /* Try to find the IRQ that is closest to the imbalance
563 * without going over.
565 if (move_this_load
< IRQ_DELTA(max_loaded
,j
)) {
566 move_this_load
= IRQ_DELTA(max_loaded
,j
);
570 if (selected_irq
== -1) {
574 imbalance
= move_this_load
;
576 /* For physical_balance case, we accumlated both load
577 * values in the one of the siblings cpu_irq[],
578 * to use the same code for physical and logical processors
579 * as much as possible.
581 * NOTE: the cpu_irq[] array holds the sum of the load for
582 * sibling A and sibling B in the slot for the lowest numbered
583 * sibling (A), _AND_ the load for sibling B in the slot for
584 * the higher numbered sibling.
586 * We seek the least loaded sibling by making the comparison
589 load
= CPU_IRQ(min_loaded
) >> 1;
590 for_each_cpu_mask(j
, cpu_sibling_map
[min_loaded
]) {
591 if (load
> CPU_IRQ(j
)) {
592 /* This won't change cpu_sibling_map[min_loaded] */
598 cpus_and(allowed_mask
,
600 balance_irq_affinity
[selected_irq
]);
601 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
602 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
604 if (!cpus_empty(tmp
)) {
606 Dprintk("irq = %d moved to cpu = %d\n",
607 selected_irq
, min_loaded
);
608 /* mark for change destination */
609 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
611 /* Since we made a change, come back sooner to
612 * check for more variation.
614 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
615 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
620 not_worth_the_effort
:
622 * if we did not find an IRQ to move, then adjust the time interval
625 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
626 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
627 Dprintk("IRQ worth rotating not found\n");
631 static int balanced_irq(void *unused
)
634 unsigned long prev_balance_time
= jiffies
;
635 long time_remaining
= balanced_irq_interval
;
639 /* push everything to CPU 0 to give us a starting point. */
640 for (i
= 0 ; i
< NR_IRQS
; i
++) {
641 irq_desc
[i
].pending_mask
= cpumask_of_cpu(0);
642 set_pending_irq(i
, cpumask_of_cpu(0));
646 time_remaining
= schedule_timeout_interruptible(time_remaining
);
648 if (time_after(jiffies
,
649 prev_balance_time
+balanced_irq_interval
)) {
652 prev_balance_time
= jiffies
;
653 time_remaining
= balanced_irq_interval
;
660 static int __init
balanced_irq_init(void)
663 struct cpuinfo_x86
*c
;
666 cpus_shift_right(tmp
, cpu_online_map
, 2);
668 /* When not overwritten by the command line ask subarchitecture. */
669 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
670 irqbalance_disabled
= NO_BALANCE_IRQ
;
671 if (irqbalance_disabled
)
674 /* disable irqbalance completely if there is only one processor online */
675 if (num_online_cpus() < 2) {
676 irqbalance_disabled
= 1;
680 * Enable physical balance only if more than 1 physical processor
683 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
684 physical_balance
= 1;
686 for_each_online_cpu(i
) {
687 irq_cpu_data
[i
].irq_delta
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
688 irq_cpu_data
[i
].last_irq
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
689 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
690 printk(KERN_ERR
"balanced_irq_init: out of memory");
693 memset(irq_cpu_data
[i
].irq_delta
,0,sizeof(unsigned long) * NR_IRQS
);
694 memset(irq_cpu_data
[i
].last_irq
,0,sizeof(unsigned long) * NR_IRQS
);
697 printk(KERN_INFO
"Starting balanced_irq\n");
698 if (kernel_thread(balanced_irq
, NULL
, CLONE_KERNEL
) >= 0)
701 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
703 for_each_possible_cpu(i
) {
704 kfree(irq_cpu_data
[i
].irq_delta
);
705 irq_cpu_data
[i
].irq_delta
= NULL
;
706 kfree(irq_cpu_data
[i
].last_irq
);
707 irq_cpu_data
[i
].last_irq
= NULL
;
712 int __init
irqbalance_disable(char *str
)
714 irqbalance_disabled
= 1;
718 __setup("noirqbalance", irqbalance_disable
);
720 late_initcall(balanced_irq_init
);
721 #endif /* CONFIG_IRQBALANCE */
722 #endif /* CONFIG_SMP */
725 void fastcall
send_IPI_self(int vector
)
732 apic_wait_icr_idle();
733 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
735 * Send the IPI. The write to APIC_ICR fires this off.
737 apic_write_around(APIC_ICR
, cfg
);
739 #endif /* !CONFIG_SMP */
743 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
744 * specific CPU-side IRQs.
748 static int pirq_entries
[MAX_PIRQS
];
749 static int pirqs_enabled
;
750 int skip_ioapic_setup
;
752 static int __init
ioapic_setup(char *str
)
754 skip_ioapic_setup
= 1;
758 __setup("noapic", ioapic_setup
);
760 static int __init
ioapic_pirq_setup(char *str
)
763 int ints
[MAX_PIRQS
+1];
765 get_options(str
, ARRAY_SIZE(ints
), ints
);
767 for (i
= 0; i
< MAX_PIRQS
; i
++)
768 pirq_entries
[i
] = -1;
771 apic_printk(APIC_VERBOSE
, KERN_INFO
772 "PIRQ redirection, working around broken MP-BIOS.\n");
774 if (ints
[0] < MAX_PIRQS
)
777 for (i
= 0; i
< max
; i
++) {
778 apic_printk(APIC_VERBOSE
, KERN_DEBUG
779 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
781 * PIRQs are mapped upside down, usually.
783 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
788 __setup("pirq=", ioapic_pirq_setup
);
791 * Find the IRQ entry number of a certain pin.
793 static int find_irq_entry(int apic
, int pin
, int type
)
797 for (i
= 0; i
< mp_irq_entries
; i
++)
798 if (mp_irqs
[i
].mpc_irqtype
== type
&&
799 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
800 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
801 mp_irqs
[i
].mpc_dstirq
== pin
)
808 * Find the pin to which IRQ[irq] (ISA) is connected
810 static int __init
find_isa_irq_pin(int irq
, int type
)
814 for (i
= 0; i
< mp_irq_entries
; i
++) {
815 int lbus
= mp_irqs
[i
].mpc_srcbus
;
817 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
818 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
819 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
||
820 mp_bus_id_to_type
[lbus
] == MP_BUS_NEC98
822 (mp_irqs
[i
].mpc_irqtype
== type
) &&
823 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
825 return mp_irqs
[i
].mpc_dstirq
;
830 static int __init
find_isa_irq_apic(int irq
, int type
)
834 for (i
= 0; i
< mp_irq_entries
; i
++) {
835 int lbus
= mp_irqs
[i
].mpc_srcbus
;
837 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
838 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
839 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
||
840 mp_bus_id_to_type
[lbus
] == MP_BUS_NEC98
842 (mp_irqs
[i
].mpc_irqtype
== type
) &&
843 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
846 if (i
< mp_irq_entries
) {
848 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
849 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
858 * Find a specific PCI IRQ entry.
859 * Not an __init, possibly needed by modules
861 static int pin_2_irq(int idx
, int apic
, int pin
);
863 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
865 int apic
, i
, best_guess
= -1;
867 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
868 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
869 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
870 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
873 for (i
= 0; i
< mp_irq_entries
; i
++) {
874 int lbus
= mp_irqs
[i
].mpc_srcbus
;
876 for (apic
= 0; apic
< nr_ioapics
; apic
++)
877 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
878 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
881 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
882 !mp_irqs
[i
].mpc_irqtype
&&
884 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
885 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
887 if (!(apic
|| IO_APIC_IRQ(irq
)))
890 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
893 * Use the first all-but-pin matching entry as a
894 * best-guess fuzzy result for broken mptables.
902 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
905 * This function currently is only a helper for the i386 smp boot process where
906 * we need to reprogram the ioredtbls to cater for the cpus which have come online
907 * so mask in all cases should simply be TARGET_CPUS
910 void __init
setup_ioapic_dest(void)
912 int pin
, ioapic
, irq
, irq_entry
;
914 if (skip_ioapic_setup
== 1)
917 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
918 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
919 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
922 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
923 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
931 * EISA Edge/Level control register, ELCR
933 static int EISA_ELCR(unsigned int irq
)
936 unsigned int port
= 0x4d0 + (irq
>> 3);
937 return (inb(port
) >> (irq
& 7)) & 1;
939 apic_printk(APIC_VERBOSE
, KERN_INFO
940 "Broken MPtable reports ISA irq %d\n", irq
);
944 /* EISA interrupts are always polarity zero and can be edge or level
945 * trigger depending on the ELCR value. If an interrupt is listed as
946 * EISA conforming in the MP table, that means its trigger type must
947 * be read in from the ELCR */
949 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
950 #define default_EISA_polarity(idx) (0)
952 /* ISA interrupts are always polarity zero edge triggered,
953 * when listed as conforming in the MP table. */
955 #define default_ISA_trigger(idx) (0)
956 #define default_ISA_polarity(idx) (0)
958 /* PCI interrupts are always polarity one level triggered,
959 * when listed as conforming in the MP table. */
961 #define default_PCI_trigger(idx) (1)
962 #define default_PCI_polarity(idx) (1)
964 /* MCA interrupts are always polarity zero level triggered,
965 * when listed as conforming in the MP table. */
967 #define default_MCA_trigger(idx) (1)
968 #define default_MCA_polarity(idx) (0)
970 /* NEC98 interrupts are always polarity zero edge triggered,
971 * when listed as conforming in the MP table. */
973 #define default_NEC98_trigger(idx) (0)
974 #define default_NEC98_polarity(idx) (0)
976 static int __init
MPBIOS_polarity(int idx
)
978 int bus
= mp_irqs
[idx
].mpc_srcbus
;
982 * Determine IRQ line polarity (high active or low active):
984 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
986 case 0: /* conforms, ie. bus-type dependent polarity */
988 switch (mp_bus_id_to_type
[bus
])
990 case MP_BUS_ISA
: /* ISA pin */
992 polarity
= default_ISA_polarity(idx
);
995 case MP_BUS_EISA
: /* EISA pin */
997 polarity
= default_EISA_polarity(idx
);
1000 case MP_BUS_PCI
: /* PCI pin */
1002 polarity
= default_PCI_polarity(idx
);
1005 case MP_BUS_MCA
: /* MCA pin */
1007 polarity
= default_MCA_polarity(idx
);
1010 case MP_BUS_NEC98
: /* NEC 98 pin */
1012 polarity
= default_NEC98_polarity(idx
);
1017 printk(KERN_WARNING
"broken BIOS!!\n");
1024 case 1: /* high active */
1029 case 2: /* reserved */
1031 printk(KERN_WARNING
"broken BIOS!!\n");
1035 case 3: /* low active */
1040 default: /* invalid */
1042 printk(KERN_WARNING
"broken BIOS!!\n");
1050 static int MPBIOS_trigger(int idx
)
1052 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1056 * Determine IRQ trigger mode (edge or level sensitive):
1058 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
1060 case 0: /* conforms, ie. bus-type dependent */
1062 switch (mp_bus_id_to_type
[bus
])
1064 case MP_BUS_ISA
: /* ISA pin */
1066 trigger
= default_ISA_trigger(idx
);
1069 case MP_BUS_EISA
: /* EISA pin */
1071 trigger
= default_EISA_trigger(idx
);
1074 case MP_BUS_PCI
: /* PCI pin */
1076 trigger
= default_PCI_trigger(idx
);
1079 case MP_BUS_MCA
: /* MCA pin */
1081 trigger
= default_MCA_trigger(idx
);
1084 case MP_BUS_NEC98
: /* NEC 98 pin */
1086 trigger
= default_NEC98_trigger(idx
);
1091 printk(KERN_WARNING
"broken BIOS!!\n");
1103 case 2: /* reserved */
1105 printk(KERN_WARNING
"broken BIOS!!\n");
1114 default: /* invalid */
1116 printk(KERN_WARNING
"broken BIOS!!\n");
1124 static inline int irq_polarity(int idx
)
1126 return MPBIOS_polarity(idx
);
1129 static inline int irq_trigger(int idx
)
1131 return MPBIOS_trigger(idx
);
1134 static int pin_2_irq(int idx
, int apic
, int pin
)
1137 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1140 * Debugging check, we are in big trouble if this message pops up!
1142 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
1143 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1145 switch (mp_bus_id_to_type
[bus
])
1147 case MP_BUS_ISA
: /* ISA pin */
1152 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
1155 case MP_BUS_PCI
: /* PCI pin */
1158 * PCI IRQs are mapped in order
1162 irq
+= nr_ioapic_registers
[i
++];
1166 * For MPS mode, so far only needed by ES7000 platform
1168 if (ioapic_renumber_irq
)
1169 irq
= ioapic_renumber_irq(apic
, irq
);
1175 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
1182 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1184 if ((pin
>= 16) && (pin
<= 23)) {
1185 if (pirq_entries
[pin
-16] != -1) {
1186 if (!pirq_entries
[pin
-16]) {
1187 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1188 "disabling PIRQ%d\n", pin
-16);
1190 irq
= pirq_entries
[pin
-16];
1191 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1192 "using PIRQ%d -> IRQ %d\n",
1200 static inline int IO_APIC_irq_trigger(int irq
)
1204 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1205 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1206 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1207 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
1208 return irq_trigger(idx
);
1212 * nonexistent IRQs are edge default
1217 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1218 u8 irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_DEVICE_VECTOR
, 0 };
1220 static int __assign_irq_vector(int irq
)
1222 static int current_vector
= FIRST_DEVICE_VECTOR
, offset
= 0;
1225 BUG_ON((unsigned)irq
>= NR_IRQ_VECTORS
);
1227 if (irq_vector
[irq
] > 0)
1228 return irq_vector
[irq
];
1230 current_vector
+= 8;
1231 if (current_vector
== SYSCALL_VECTOR
)
1232 current_vector
+= 8;
1234 if (current_vector
>= FIRST_SYSTEM_VECTOR
) {
1238 current_vector
= FIRST_DEVICE_VECTOR
+ offset
;
1241 vector
= current_vector
;
1242 irq_vector
[irq
] = vector
;
1247 static int assign_irq_vector(int irq
)
1249 unsigned long flags
;
1252 spin_lock_irqsave(&vector_lock
, flags
);
1253 vector
= __assign_irq_vector(irq
);
1254 spin_unlock_irqrestore(&vector_lock
, flags
);
1258 static struct irq_chip ioapic_chip
;
1260 #define IOAPIC_AUTO -1
1261 #define IOAPIC_EDGE 0
1262 #define IOAPIC_LEVEL 1
1264 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1266 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1267 trigger
== IOAPIC_LEVEL
)
1268 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1269 handle_fasteoi_irq
, "fasteoi");
1271 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1272 handle_edge_irq
, "edge");
1273 set_intr_gate(vector
, interrupt
[irq
]);
1276 static void __init
setup_IO_APIC_irqs(void)
1278 struct IO_APIC_route_entry entry
;
1279 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1280 unsigned long flags
;
1282 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1284 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1285 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1288 * add it to the IO-APIC irq-routing table:
1290 memset(&entry
,0,sizeof(entry
));
1292 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1293 entry
.dest_mode
= INT_DEST_MODE
;
1294 entry
.mask
= 0; /* enable IRQ */
1295 entry
.dest
.logical
.logical_dest
=
1296 cpu_mask_to_apicid(TARGET_CPUS
);
1298 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1301 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1302 " IO-APIC (apicid-pin) %d-%d",
1303 mp_ioapics
[apic
].mpc_apicid
,
1307 apic_printk(APIC_VERBOSE
, ", %d-%d",
1308 mp_ioapics
[apic
].mpc_apicid
, pin
);
1312 entry
.trigger
= irq_trigger(idx
);
1313 entry
.polarity
= irq_polarity(idx
);
1315 if (irq_trigger(idx
)) {
1320 irq
= pin_2_irq(idx
, apic
, pin
);
1322 * skip adding the timer int on secondary nodes, which causes
1323 * a small but painful rift in the time-space continuum
1325 if (multi_timer_check(apic
, irq
))
1328 add_pin_to_irq(irq
, apic
, pin
);
1330 if (!apic
&& !IO_APIC_IRQ(irq
))
1333 if (IO_APIC_IRQ(irq
)) {
1334 vector
= assign_irq_vector(irq
);
1335 entry
.vector
= vector
;
1336 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1338 if (!apic
&& (irq
< 16))
1339 disable_8259A_irq(irq
);
1341 ioapic_write_entry(apic
, pin
, entry
);
1342 spin_lock_irqsave(&ioapic_lock
, flags
);
1343 set_native_irq_info(irq
, TARGET_CPUS
);
1344 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1349 apic_printk(APIC_VERBOSE
, " not connected.\n");
1353 * Set up the 8259A-master output pin:
1355 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
1357 struct IO_APIC_route_entry entry
;
1359 memset(&entry
,0,sizeof(entry
));
1361 disable_8259A_irq(0);
1364 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1367 * We use logical delivery to get the timer IRQ
1370 entry
.dest_mode
= INT_DEST_MODE
;
1371 entry
.mask
= 0; /* unmask IRQ now */
1372 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1373 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1376 entry
.vector
= vector
;
1379 * The timer IRQ doesn't have to know that behind the
1380 * scene we have a 8259A-master in AEOI mode ...
1382 irq_desc
[0].chip
= &ioapic_chip
;
1383 set_irq_handler(0, handle_edge_irq
);
1386 * Add it to the IO-APIC irq-routing table:
1388 ioapic_write_entry(apic
, pin
, entry
);
1390 enable_8259A_irq(0);
1393 static inline void UNEXPECTED_IO_APIC(void)
1397 void __init
print_IO_APIC(void)
1400 union IO_APIC_reg_00 reg_00
;
1401 union IO_APIC_reg_01 reg_01
;
1402 union IO_APIC_reg_02 reg_02
;
1403 union IO_APIC_reg_03 reg_03
;
1404 unsigned long flags
;
1406 if (apic_verbosity
== APIC_QUIET
)
1409 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1410 for (i
= 0; i
< nr_ioapics
; i
++)
1411 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1412 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
1415 * We are a bit conservative about what we expect. We have to
1416 * know about every hardware change ASAP.
1418 printk(KERN_INFO
"testing the IO APIC.......................\n");
1420 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1422 spin_lock_irqsave(&ioapic_lock
, flags
);
1423 reg_00
.raw
= io_apic_read(apic
, 0);
1424 reg_01
.raw
= io_apic_read(apic
, 1);
1425 if (reg_01
.bits
.version
>= 0x10)
1426 reg_02
.raw
= io_apic_read(apic
, 2);
1427 if (reg_01
.bits
.version
>= 0x20)
1428 reg_03
.raw
= io_apic_read(apic
, 3);
1429 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1431 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
1432 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1433 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1434 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1435 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1436 if (reg_00
.bits
.ID
>= get_physical_broadcast())
1437 UNEXPECTED_IO_APIC();
1438 if (reg_00
.bits
.__reserved_1
|| reg_00
.bits
.__reserved_2
)
1439 UNEXPECTED_IO_APIC();
1441 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1442 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1443 if ( (reg_01
.bits
.entries
!= 0x0f) && /* older (Neptune) boards */
1444 (reg_01
.bits
.entries
!= 0x17) && /* typical ISA+PCI boards */
1445 (reg_01
.bits
.entries
!= 0x1b) && /* Compaq Proliant boards */
1446 (reg_01
.bits
.entries
!= 0x1f) && /* dual Xeon boards */
1447 (reg_01
.bits
.entries
!= 0x22) && /* bigger Xeon boards */
1448 (reg_01
.bits
.entries
!= 0x2E) &&
1449 (reg_01
.bits
.entries
!= 0x3F)
1451 UNEXPECTED_IO_APIC();
1453 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1454 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1455 if ( (reg_01
.bits
.version
!= 0x01) && /* 82489DX IO-APICs */
1456 (reg_01
.bits
.version
!= 0x10) && /* oldest IO-APICs */
1457 (reg_01
.bits
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
1458 (reg_01
.bits
.version
!= 0x13) && /* Xeon IO-APICs */
1459 (reg_01
.bits
.version
!= 0x20) /* Intel P64H (82806 AA) */
1461 UNEXPECTED_IO_APIC();
1462 if (reg_01
.bits
.__reserved_1
|| reg_01
.bits
.__reserved_2
)
1463 UNEXPECTED_IO_APIC();
1466 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1467 * but the value of reg_02 is read as the previous read register
1468 * value, so ignore it if reg_02 == reg_01.
1470 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1471 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1472 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1473 if (reg_02
.bits
.__reserved_1
|| reg_02
.bits
.__reserved_2
)
1474 UNEXPECTED_IO_APIC();
1478 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1479 * or reg_03, but the value of reg_0[23] is read as the previous read
1480 * register value, so ignore it if reg_03 == reg_0[12].
1482 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1483 reg_03
.raw
!= reg_01
.raw
) {
1484 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1485 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1486 if (reg_03
.bits
.__reserved_1
)
1487 UNEXPECTED_IO_APIC();
1490 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1492 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1493 " Stat Dest Deli Vect: \n");
1495 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1496 struct IO_APIC_route_entry entry
;
1498 entry
= ioapic_read_entry(apic
, i
);
1500 printk(KERN_DEBUG
" %02x %03X %02X ",
1502 entry
.dest
.logical
.logical_dest
,
1503 entry
.dest
.physical
.physical_dest
1506 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1511 entry
.delivery_status
,
1513 entry
.delivery_mode
,
1518 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1519 for (i
= 0; i
< NR_IRQS
; i
++) {
1520 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1523 printk(KERN_DEBUG
"IRQ%d ", i
);
1525 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1528 entry
= irq_2_pin
+ entry
->next
;
1533 printk(KERN_INFO
".................................... done.\n");
1540 static void print_APIC_bitfield (int base
)
1545 if (apic_verbosity
== APIC_QUIET
)
1548 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1549 for (i
= 0; i
< 8; i
++) {
1550 v
= apic_read(base
+ i
*0x10);
1551 for (j
= 0; j
< 32; j
++) {
1561 void /*__init*/ print_local_APIC(void * dummy
)
1563 unsigned int v
, ver
, maxlvt
;
1565 if (apic_verbosity
== APIC_QUIET
)
1568 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1569 smp_processor_id(), hard_smp_processor_id());
1570 v
= apic_read(APIC_ID
);
1571 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
1572 v
= apic_read(APIC_LVR
);
1573 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1574 ver
= GET_APIC_VERSION(v
);
1575 maxlvt
= get_maxlvt();
1577 v
= apic_read(APIC_TASKPRI
);
1578 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1580 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1581 v
= apic_read(APIC_ARBPRI
);
1582 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1583 v
& APIC_ARBPRI_MASK
);
1584 v
= apic_read(APIC_PROCPRI
);
1585 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1588 v
= apic_read(APIC_EOI
);
1589 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1590 v
= apic_read(APIC_RRR
);
1591 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1592 v
= apic_read(APIC_LDR
);
1593 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1594 v
= apic_read(APIC_DFR
);
1595 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1596 v
= apic_read(APIC_SPIV
);
1597 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1599 printk(KERN_DEBUG
"... APIC ISR field:\n");
1600 print_APIC_bitfield(APIC_ISR
);
1601 printk(KERN_DEBUG
"... APIC TMR field:\n");
1602 print_APIC_bitfield(APIC_TMR
);
1603 printk(KERN_DEBUG
"... APIC IRR field:\n");
1604 print_APIC_bitfield(APIC_IRR
);
1606 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1607 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1608 apic_write(APIC_ESR
, 0);
1609 v
= apic_read(APIC_ESR
);
1610 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1613 v
= apic_read(APIC_ICR
);
1614 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1615 v
= apic_read(APIC_ICR2
);
1616 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1618 v
= apic_read(APIC_LVTT
);
1619 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1621 if (maxlvt
> 3) { /* PC is LVT#4. */
1622 v
= apic_read(APIC_LVTPC
);
1623 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1625 v
= apic_read(APIC_LVT0
);
1626 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1627 v
= apic_read(APIC_LVT1
);
1628 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1630 if (maxlvt
> 2) { /* ERR is LVT#3. */
1631 v
= apic_read(APIC_LVTERR
);
1632 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1635 v
= apic_read(APIC_TMICT
);
1636 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1637 v
= apic_read(APIC_TMCCT
);
1638 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1639 v
= apic_read(APIC_TDCR
);
1640 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1644 void print_all_local_APICs (void)
1646 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1649 void /*__init*/ print_PIC(void)
1652 unsigned long flags
;
1654 if (apic_verbosity
== APIC_QUIET
)
1657 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1659 spin_lock_irqsave(&i8259A_lock
, flags
);
1661 v
= inb(0xa1) << 8 | inb(0x21);
1662 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1664 v
= inb(0xa0) << 8 | inb(0x20);
1665 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1669 v
= inb(0xa0) << 8 | inb(0x20);
1673 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1675 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1677 v
= inb(0x4d1) << 8 | inb(0x4d0);
1678 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1683 static void __init
enable_IO_APIC(void)
1685 union IO_APIC_reg_01 reg_01
;
1686 int i8259_apic
, i8259_pin
;
1688 unsigned long flags
;
1690 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1691 irq_2_pin
[i
].pin
= -1;
1692 irq_2_pin
[i
].next
= 0;
1695 for (i
= 0; i
< MAX_PIRQS
; i
++)
1696 pirq_entries
[i
] = -1;
1699 * The number of IO-APIC IRQ registers (== #pins):
1701 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1702 spin_lock_irqsave(&ioapic_lock
, flags
);
1703 reg_01
.raw
= io_apic_read(apic
, 1);
1704 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1705 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1707 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1709 /* See if any of the pins is in ExtINT mode */
1710 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1711 struct IO_APIC_route_entry entry
;
1712 entry
= ioapic_read_entry(apic
, pin
);
1715 /* If the interrupt line is enabled and in ExtInt mode
1716 * I have found the pin where the i8259 is connected.
1718 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1719 ioapic_i8259
.apic
= apic
;
1720 ioapic_i8259
.pin
= pin
;
1726 /* Look to see what if the MP table has reported the ExtINT */
1727 /* If we could not find the appropriate pin by looking at the ioapic
1728 * the i8259 probably is not connected the ioapic but give the
1729 * mptable a chance anyway.
1731 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1732 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1733 /* Trust the MP table if nothing is setup in the hardware */
1734 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1735 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1736 ioapic_i8259
.pin
= i8259_pin
;
1737 ioapic_i8259
.apic
= i8259_apic
;
1739 /* Complain if the MP table and the hardware disagree */
1740 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1741 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1743 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1747 * Do not trust the IO-APIC being empty at bootup
1753 * Not an __init, needed by the reboot code
1755 void disable_IO_APIC(void)
1758 * Clear the IO-APIC before rebooting:
1763 * If the i8259 is routed through an IOAPIC
1764 * Put that IOAPIC in virtual wire mode
1765 * so legacy interrupts can be delivered.
1767 if (ioapic_i8259
.pin
!= -1) {
1768 struct IO_APIC_route_entry entry
;
1770 memset(&entry
, 0, sizeof(entry
));
1771 entry
.mask
= 0; /* Enabled */
1772 entry
.trigger
= 0; /* Edge */
1774 entry
.polarity
= 0; /* High */
1775 entry
.delivery_status
= 0;
1776 entry
.dest_mode
= 0; /* Physical */
1777 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1779 entry
.dest
.physical
.physical_dest
=
1780 GET_APIC_ID(apic_read(APIC_ID
));
1783 * Add it to the IO-APIC irq-routing table:
1785 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1787 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1791 * function to set the IO-APIC physical IDs based on the
1792 * values stored in the MPC table.
1794 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1797 #ifndef CONFIG_X86_NUMAQ
1798 static void __init
setup_ioapic_ids_from_mpc(void)
1800 union IO_APIC_reg_00 reg_00
;
1801 physid_mask_t phys_id_present_map
;
1804 unsigned char old_id
;
1805 unsigned long flags
;
1808 * Don't check I/O APIC IDs for xAPIC systems. They have
1809 * no meaning without the serial APIC bus.
1811 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1812 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1815 * This is broken; anything with a real cpu count has to
1816 * circumvent this idiocy regardless.
1818 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1821 * Set the IOAPIC ID to the value stored in the MPC table.
1823 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1825 /* Read the register 0 value */
1826 spin_lock_irqsave(&ioapic_lock
, flags
);
1827 reg_00
.raw
= io_apic_read(apic
, 0);
1828 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1830 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1832 if (mp_ioapics
[apic
].mpc_apicid
>= get_physical_broadcast()) {
1833 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1834 apic
, mp_ioapics
[apic
].mpc_apicid
);
1835 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1837 mp_ioapics
[apic
].mpc_apicid
= reg_00
.bits
.ID
;
1841 * Sanity check, is the ID really free? Every APIC in a
1842 * system must have a unique ID or we get lots of nice
1843 * 'stuck on smp_invalidate_needed IPI wait' messages.
1845 if (check_apicid_used(phys_id_present_map
,
1846 mp_ioapics
[apic
].mpc_apicid
)) {
1847 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1848 apic
, mp_ioapics
[apic
].mpc_apicid
);
1849 for (i
= 0; i
< get_physical_broadcast(); i
++)
1850 if (!physid_isset(i
, phys_id_present_map
))
1852 if (i
>= get_physical_broadcast())
1853 panic("Max APIC ID exceeded!\n");
1854 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1856 physid_set(i
, phys_id_present_map
);
1857 mp_ioapics
[apic
].mpc_apicid
= i
;
1860 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mpc_apicid
);
1861 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1862 "phys_id_present_map\n",
1863 mp_ioapics
[apic
].mpc_apicid
);
1864 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1869 * We need to adjust the IRQ routing table
1870 * if the ID changed.
1872 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1873 for (i
= 0; i
< mp_irq_entries
; i
++)
1874 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1875 mp_irqs
[i
].mpc_dstapic
1876 = mp_ioapics
[apic
].mpc_apicid
;
1879 * Read the right value from the MPC table and
1880 * write it into the ID register.
1882 apic_printk(APIC_VERBOSE
, KERN_INFO
1883 "...changing IO-APIC physical APIC ID to %d ...",
1884 mp_ioapics
[apic
].mpc_apicid
);
1886 reg_00
.bits
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1887 spin_lock_irqsave(&ioapic_lock
, flags
);
1888 io_apic_write(apic
, 0, reg_00
.raw
);
1889 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1894 spin_lock_irqsave(&ioapic_lock
, flags
);
1895 reg_00
.raw
= io_apic_read(apic
, 0);
1896 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1897 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1898 printk("could not set ID!\n");
1900 apic_printk(APIC_VERBOSE
, " ok.\n");
1904 static void __init
setup_ioapic_ids_from_mpc(void) { }
1908 * There is a nasty bug in some older SMP boards, their mptable lies
1909 * about the timer IRQ. We do the following to work around the situation:
1911 * - timer IRQ defaults to IO-APIC IRQ
1912 * - if this function detects that timer IRQs are defunct, then we fall
1913 * back to ISA timer IRQs
1915 static int __init
timer_irq_works(void)
1917 unsigned long t1
= jiffies
;
1920 /* Let ten ticks pass... */
1921 mdelay((10 * 1000) / HZ
);
1924 * Expect a few ticks at least, to be sure some possible
1925 * glue logic does not lock up after one or two first
1926 * ticks in a non-ExtINT mode. Also the local APIC
1927 * might have cached one ExtINT interrupt. Finally, at
1928 * least one tick may be lost due to delays.
1930 if (jiffies
- t1
> 4)
1937 * In the SMP+IOAPIC case it might happen that there are an unspecified
1938 * number of pending IRQ events unhandled. These cases are very rare,
1939 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1940 * better to do it this way as thus we do not have to be aware of
1941 * 'pending' interrupts in the IRQ path, except at this point.
1944 * Edge triggered needs to resend any interrupt
1945 * that was delayed but this is now handled in the device
1952 * Starting up a edge-triggered IO-APIC interrupt is
1953 * nasty - we need to make sure that we get the edge.
1954 * If it is already asserted for some reason, we need
1955 * return 1 to indicate that is was pending.
1957 * This is not complete - we should be able to fake
1958 * an edge even if it isn't on the 8259A...
1960 * (We do this for level-triggered IRQs too - it cannot hurt.)
1962 static unsigned int startup_ioapic_irq(unsigned int irq
)
1964 int was_pending
= 0;
1965 unsigned long flags
;
1967 spin_lock_irqsave(&ioapic_lock
, flags
);
1969 disable_8259A_irq(irq
);
1970 if (i8259A_irq_pending(irq
))
1973 __unmask_IO_APIC_irq(irq
);
1974 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1979 static void ack_ioapic_irq(unsigned int irq
)
1981 move_native_irq(irq
);
1985 static void ack_ioapic_quirk_irq(unsigned int irq
)
1990 move_native_irq(irq
);
1992 * It appears there is an erratum which affects at least version 0x11
1993 * of I/O APIC (that's the 82093AA and cores integrated into various
1994 * chipsets). Under certain conditions a level-triggered interrupt is
1995 * erroneously delivered as edge-triggered one but the respective IRR
1996 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1997 * message but it will never arrive and further interrupts are blocked
1998 * from the source. The exact reason is so far unknown, but the
1999 * phenomenon was observed when two consecutive interrupt requests
2000 * from a given source get delivered to the same CPU and the source is
2001 * temporarily disabled in between.
2003 * A workaround is to simulate an EOI message manually. We achieve it
2004 * by setting the trigger mode to edge and then to level when the edge
2005 * trigger mode gets detected in the TMR of a local APIC for a
2006 * level-triggered interrupt. We mask the source for the time of the
2007 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2008 * The idea is from Manfred Spraul. --macro
2010 i
= irq_vector
[irq
];
2012 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2016 if (!(v
& (1 << (i
& 0x1f)))) {
2017 atomic_inc(&irq_mis_count
);
2018 spin_lock(&ioapic_lock
);
2019 __mask_and_edge_IO_APIC_irq(irq
);
2020 __unmask_and_level_IO_APIC_irq(irq
);
2021 spin_unlock(&ioapic_lock
);
2025 static int ioapic_retrigger_irq(unsigned int irq
)
2027 send_IPI_self(irq_vector
[irq
]);
2032 static struct irq_chip ioapic_chip __read_mostly
= {
2034 .startup
= startup_ioapic_irq
,
2035 .mask
= mask_IO_APIC_irq
,
2036 .unmask
= unmask_IO_APIC_irq
,
2037 .ack
= ack_ioapic_irq
,
2038 .eoi
= ack_ioapic_quirk_irq
,
2040 .set_affinity
= set_ioapic_affinity_irq
,
2042 .retrigger
= ioapic_retrigger_irq
,
2046 static inline void init_IO_APIC_traps(void)
2051 * NOTE! The local APIC isn't very good at handling
2052 * multiple interrupts at the same interrupt level.
2053 * As the interrupt level is determined by taking the
2054 * vector number and shifting that right by 4, we
2055 * want to spread these out a bit so that they don't
2056 * all fall in the same interrupt level.
2058 * Also, we've got to be careful not to trash gate
2059 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2061 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
2063 if (IO_APIC_IRQ(tmp
) && !irq_vector
[tmp
]) {
2065 * Hmm.. We don't have an entry for this,
2066 * so default to an old-fashioned 8259
2067 * interrupt if we can..
2070 make_8259A_irq(irq
);
2072 /* Strange. Oh, well.. */
2073 irq_desc
[irq
].chip
= &no_irq_chip
;
2079 * The local APIC irq-chip implementation:
2082 static void ack_apic(unsigned int irq
)
2087 static void mask_lapic_irq (unsigned int irq
)
2091 v
= apic_read(APIC_LVT0
);
2092 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2095 static void unmask_lapic_irq (unsigned int irq
)
2099 v
= apic_read(APIC_LVT0
);
2100 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2103 static struct irq_chip lapic_chip __read_mostly
= {
2104 .name
= "local-APIC-edge",
2105 .mask
= mask_lapic_irq
,
2106 .unmask
= unmask_lapic_irq
,
2110 static void setup_nmi (void)
2113 * Dirty trick to enable the NMI watchdog ...
2114 * We put the 8259A master into AEOI mode and
2115 * unmask on all local APICs LVT0 as NMI.
2117 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2118 * is from Maciej W. Rozycki - so we do not have to EOI from
2119 * the NMI handler or the timer interrupt.
2121 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2123 on_each_cpu(enable_NMI_through_LVT0
, NULL
, 1, 1);
2125 apic_printk(APIC_VERBOSE
, " done.\n");
2129 * This looks a bit hackish but it's about the only one way of sending
2130 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2131 * not support the ExtINT mode, unfortunately. We need to send these
2132 * cycles as some i82489DX-based boards have glue logic that keeps the
2133 * 8259A interrupt line asserted until INTA. --macro
2135 static inline void unlock_ExtINT_logic(void)
2138 struct IO_APIC_route_entry entry0
, entry1
;
2139 unsigned char save_control
, save_freq_select
;
2141 pin
= find_isa_irq_pin(8, mp_INT
);
2142 apic
= find_isa_irq_apic(8, mp_INT
);
2146 entry0
= ioapic_read_entry(apic
, pin
);
2147 clear_IO_APIC_pin(apic
, pin
);
2149 memset(&entry1
, 0, sizeof(entry1
));
2151 entry1
.dest_mode
= 0; /* physical delivery */
2152 entry1
.mask
= 0; /* unmask IRQ now */
2153 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2154 entry1
.delivery_mode
= dest_ExtINT
;
2155 entry1
.polarity
= entry0
.polarity
;
2159 ioapic_write_entry(apic
, pin
, entry1
);
2161 save_control
= CMOS_READ(RTC_CONTROL
);
2162 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2163 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2165 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2170 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2174 CMOS_WRITE(save_control
, RTC_CONTROL
);
2175 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2176 clear_IO_APIC_pin(apic
, pin
);
2178 ioapic_write_entry(apic
, pin
, entry0
);
2181 int timer_uses_ioapic_pin_0
;
2184 * This code may look a bit paranoid, but it's supposed to cooperate with
2185 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2186 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2187 * fanatically on his truly buggy board.
2189 static inline void check_timer(void)
2191 int apic1
, pin1
, apic2
, pin2
;
2195 * get/set the timer IRQ vector:
2197 disable_8259A_irq(0);
2198 vector
= assign_irq_vector(0);
2199 set_intr_gate(vector
, interrupt
[0]);
2202 * Subtle, code in do_timer_interrupt() expects an AEOI
2203 * mode for the 8259A whenever interrupts are routed
2204 * through I/O APICs. Also IRQ0 has to be enabled in
2205 * the 8259A which implies the virtual wire has to be
2206 * disabled in the local APIC.
2208 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2211 if (timer_over_8254
> 0)
2212 enable_8259A_irq(0);
2214 pin1
= find_isa_irq_pin(0, mp_INT
);
2215 apic1
= find_isa_irq_apic(0, mp_INT
);
2216 pin2
= ioapic_i8259
.pin
;
2217 apic2
= ioapic_i8259
.apic
;
2220 timer_uses_ioapic_pin_0
= 1;
2222 printk(KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2223 vector
, apic1
, pin1
, apic2
, pin2
);
2227 * Ok, does IRQ0 through the IOAPIC work?
2229 unmask_IO_APIC_irq(0);
2230 if (timer_irq_works()) {
2231 if (nmi_watchdog
== NMI_IO_APIC
) {
2232 disable_8259A_irq(0);
2234 enable_8259A_irq(0);
2236 if (disable_timer_pin_1
> 0)
2237 clear_IO_APIC_pin(0, pin1
);
2240 clear_IO_APIC_pin(apic1
, pin1
);
2241 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to "
2245 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
2247 printk("\n..... (found pin %d) ...", pin2
);
2249 * legacy devices should be connected to IO APIC #0
2251 setup_ExtINT_IRQ0_pin(apic2
, pin2
, vector
);
2252 if (timer_irq_works()) {
2255 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2257 add_pin_to_irq(0, apic2
, pin2
);
2258 if (nmi_watchdog
== NMI_IO_APIC
) {
2264 * Cleanup, just in case ...
2266 clear_IO_APIC_pin(apic2
, pin2
);
2268 printk(" failed.\n");
2270 if (nmi_watchdog
== NMI_IO_APIC
) {
2271 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2275 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
2277 disable_8259A_irq(0);
2278 set_irq_chip_and_handler_name(0, &lapic_chip
, handle_fasteoi_irq
,
2280 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2281 enable_8259A_irq(0);
2283 if (timer_irq_works()) {
2284 printk(" works.\n");
2287 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2288 printk(" failed.\n");
2290 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
2295 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
2297 unlock_ExtINT_logic();
2299 if (timer_irq_works()) {
2300 printk(" works.\n");
2303 printk(" failed :(.\n");
2304 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2305 "report. Then try booting with the 'noapic' option");
2310 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2311 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2312 * Linux doesn't really care, as it's not actually used
2313 * for any interrupt handling anyway.
2315 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2317 void __init
setup_IO_APIC(void)
2322 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
2324 io_apic_irqs
= ~PIC_IRQS
;
2326 printk("ENABLING IO-APIC IRQs\n");
2329 * Set up IO-APIC IRQ routing.
2332 setup_ioapic_ids_from_mpc();
2334 setup_IO_APIC_irqs();
2335 init_IO_APIC_traps();
2341 static int __init
setup_disable_8254_timer(char *s
)
2343 timer_over_8254
= -1;
2346 static int __init
setup_enable_8254_timer(char *s
)
2348 timer_over_8254
= 2;
2352 __setup("disable_8254_timer", setup_disable_8254_timer
);
2353 __setup("enable_8254_timer", setup_enable_8254_timer
);
2356 * Called after all the initialization is done. If we didnt find any
2357 * APIC bugs then we can allow the modify fast path
2360 static int __init
io_apic_bug_finalize(void)
2362 if(sis_apic_bug
== -1)
2367 late_initcall(io_apic_bug_finalize
);
2369 struct sysfs_ioapic_data
{
2370 struct sys_device dev
;
2371 struct IO_APIC_route_entry entry
[0];
2373 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2375 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2377 struct IO_APIC_route_entry
*entry
;
2378 struct sysfs_ioapic_data
*data
;
2381 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2382 entry
= data
->entry
;
2383 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2384 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2389 static int ioapic_resume(struct sys_device
*dev
)
2391 struct IO_APIC_route_entry
*entry
;
2392 struct sysfs_ioapic_data
*data
;
2393 unsigned long flags
;
2394 union IO_APIC_reg_00 reg_00
;
2397 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2398 entry
= data
->entry
;
2400 spin_lock_irqsave(&ioapic_lock
, flags
);
2401 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2402 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
2403 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
2404 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2406 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2407 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2408 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2413 static struct sysdev_class ioapic_sysdev_class
= {
2414 set_kset_name("ioapic"),
2415 .suspend
= ioapic_suspend
,
2416 .resume
= ioapic_resume
,
2419 static int __init
ioapic_init_sysfs(void)
2421 struct sys_device
* dev
;
2422 int i
, size
, error
= 0;
2424 error
= sysdev_class_register(&ioapic_sysdev_class
);
2428 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2429 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2430 * sizeof(struct IO_APIC_route_entry
);
2431 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
2432 if (!mp_ioapic_data
[i
]) {
2433 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2436 memset(mp_ioapic_data
[i
], 0, size
);
2437 dev
= &mp_ioapic_data
[i
]->dev
;
2439 dev
->cls
= &ioapic_sysdev_class
;
2440 error
= sysdev_register(dev
);
2442 kfree(mp_ioapic_data
[i
]);
2443 mp_ioapic_data
[i
] = NULL
;
2444 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2452 device_initcall(ioapic_init_sysfs
);
2455 * Dynamic irq allocate and deallocation
2457 int create_irq(void)
2459 /* Allocate an unused irq */
2460 int irq
, new, vector
;
2461 unsigned long flags
;
2464 spin_lock_irqsave(&vector_lock
, flags
);
2465 for (new = (NR_IRQS
- 1); new >= 0; new--) {
2466 if (platform_legacy_irq(new))
2468 if (irq_vector
[new] != 0)
2470 vector
= __assign_irq_vector(new);
2471 if (likely(vector
> 0))
2475 spin_unlock_irqrestore(&vector_lock
, flags
);
2478 set_intr_gate(vector
, interrupt
[irq
]);
2479 dynamic_irq_init(irq
);
2484 void destroy_irq(unsigned int irq
)
2486 unsigned long flags
;
2488 dynamic_irq_cleanup(irq
);
2490 spin_lock_irqsave(&vector_lock
, flags
);
2491 irq_vector
[irq
] = 0;
2492 spin_unlock_irqrestore(&vector_lock
, flags
);
2496 * MSI mesage composition
2498 #ifdef CONFIG_PCI_MSI
2499 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2504 vector
= assign_irq_vector(irq
);
2506 dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2508 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2511 ((INT_DEST_MODE
== 0) ?
2512 MSI_ADDR_DEST_MODE_PHYSICAL
:
2513 MSI_ADDR_DEST_MODE_LOGICAL
) |
2514 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2515 MSI_ADDR_REDIRECTION_CPU
:
2516 MSI_ADDR_REDIRECTION_LOWPRI
) |
2517 MSI_ADDR_DEST_ID(dest
);
2520 MSI_DATA_TRIGGER_EDGE
|
2521 MSI_DATA_LEVEL_ASSERT
|
2522 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2523 MSI_DATA_DELIVERY_FIXED
:
2524 MSI_DATA_DELIVERY_LOWPRI
) |
2525 MSI_DATA_VECTOR(vector
);
2531 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2538 cpus_and(tmp
, mask
, cpu_online_map
);
2539 if (cpus_empty(tmp
))
2542 vector
= assign_irq_vector(irq
);
2546 dest
= cpu_mask_to_apicid(mask
);
2548 read_msi_msg(irq
, &msg
);
2550 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2551 msg
.data
|= MSI_DATA_VECTOR(vector
);
2552 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2553 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2555 write_msi_msg(irq
, &msg
);
2556 set_native_irq_info(irq
, mask
);
2558 #endif /* CONFIG_SMP */
2561 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2562 * which implement the MSI or MSI-X Capability Structure.
2564 static struct irq_chip msi_chip
= {
2566 .unmask
= unmask_msi_irq
,
2567 .mask
= mask_msi_irq
,
2568 .ack
= ack_ioapic_irq
,
2570 .set_affinity
= set_msi_irq_affinity
,
2572 .retrigger
= ioapic_retrigger_irq
,
2575 int arch_setup_msi_irq(unsigned int irq
, struct pci_dev
*dev
)
2579 ret
= msi_compose_msg(dev
, irq
, &msg
);
2583 write_msi_msg(irq
, &msg
);
2585 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
,
2591 void arch_teardown_msi_irq(unsigned int irq
)
2596 #endif /* CONFIG_PCI_MSI */
2599 * Hypertransport interrupt support
2601 #ifdef CONFIG_HT_IRQ
2605 static void target_ht_irq(unsigned int irq
, unsigned int dest
)
2608 low
= read_ht_irq_low(irq
);
2609 high
= read_ht_irq_high(irq
);
2611 low
&= ~(HT_IRQ_LOW_DEST_ID_MASK
);
2612 high
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2614 low
|= HT_IRQ_LOW_DEST_ID(dest
);
2615 high
|= HT_IRQ_HIGH_DEST_ID(dest
);
2617 write_ht_irq_low(irq
, low
);
2618 write_ht_irq_high(irq
, high
);
2621 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2626 cpus_and(tmp
, mask
, cpu_online_map
);
2627 if (cpus_empty(tmp
))
2630 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
2632 dest
= cpu_mask_to_apicid(mask
);
2634 target_ht_irq(irq
, dest
);
2635 set_native_irq_info(irq
, mask
);
2639 static struct irq_chip ht_irq_chip
= {
2641 .mask
= mask_ht_irq
,
2642 .unmask
= unmask_ht_irq
,
2643 .ack
= ack_ioapic_irq
,
2645 .set_affinity
= set_ht_irq_affinity
,
2647 .retrigger
= ioapic_retrigger_irq
,
2650 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2654 vector
= assign_irq_vector(irq
);
2661 cpu_set(vector
>> 8, tmp
);
2662 dest
= cpu_mask_to_apicid(tmp
);
2664 high
= HT_IRQ_HIGH_DEST_ID(dest
);
2666 low
= HT_IRQ_LOW_BASE
|
2667 HT_IRQ_LOW_DEST_ID(dest
) |
2668 HT_IRQ_LOW_VECTOR(vector
) |
2669 ((INT_DEST_MODE
== 0) ?
2670 HT_IRQ_LOW_DM_PHYSICAL
:
2671 HT_IRQ_LOW_DM_LOGICAL
) |
2672 HT_IRQ_LOW_RQEOI_EDGE
|
2673 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2674 HT_IRQ_LOW_MT_FIXED
:
2675 HT_IRQ_LOW_MT_ARBITRATED
) |
2676 HT_IRQ_LOW_IRQ_MASKED
;
2678 write_ht_irq_low(irq
, low
);
2679 write_ht_irq_high(irq
, high
);
2681 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2682 handle_edge_irq
, "edge");
2686 #endif /* CONFIG_HT_IRQ */
2688 /* --------------------------------------------------------------------------
2689 ACPI-based IOAPIC Configuration
2690 -------------------------------------------------------------------------- */
2694 int __init
io_apic_get_unique_id (int ioapic
, int apic_id
)
2696 union IO_APIC_reg_00 reg_00
;
2697 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2699 unsigned long flags
;
2703 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2704 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2705 * supports up to 16 on one shared APIC bus.
2707 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2708 * advantage of new APIC bus architecture.
2711 if (physids_empty(apic_id_map
))
2712 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2714 spin_lock_irqsave(&ioapic_lock
, flags
);
2715 reg_00
.raw
= io_apic_read(ioapic
, 0);
2716 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2718 if (apic_id
>= get_physical_broadcast()) {
2719 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2720 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2721 apic_id
= reg_00
.bits
.ID
;
2725 * Every APIC in a system must have a unique ID or we get lots of nice
2726 * 'stuck on smp_invalidate_needed IPI wait' messages.
2728 if (check_apicid_used(apic_id_map
, apic_id
)) {
2730 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2731 if (!check_apicid_used(apic_id_map
, i
))
2735 if (i
== get_physical_broadcast())
2736 panic("Max apic_id exceeded!\n");
2738 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2739 "trying %d\n", ioapic
, apic_id
, i
);
2744 tmp
= apicid_to_cpu_present(apic_id
);
2745 physids_or(apic_id_map
, apic_id_map
, tmp
);
2747 if (reg_00
.bits
.ID
!= apic_id
) {
2748 reg_00
.bits
.ID
= apic_id
;
2750 spin_lock_irqsave(&ioapic_lock
, flags
);
2751 io_apic_write(ioapic
, 0, reg_00
.raw
);
2752 reg_00
.raw
= io_apic_read(ioapic
, 0);
2753 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2756 if (reg_00
.bits
.ID
!= apic_id
) {
2757 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2762 apic_printk(APIC_VERBOSE
, KERN_INFO
2763 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2769 int __init
io_apic_get_version (int ioapic
)
2771 union IO_APIC_reg_01 reg_01
;
2772 unsigned long flags
;
2774 spin_lock_irqsave(&ioapic_lock
, flags
);
2775 reg_01
.raw
= io_apic_read(ioapic
, 1);
2776 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2778 return reg_01
.bits
.version
;
2782 int __init
io_apic_get_redir_entries (int ioapic
)
2784 union IO_APIC_reg_01 reg_01
;
2785 unsigned long flags
;
2787 spin_lock_irqsave(&ioapic_lock
, flags
);
2788 reg_01
.raw
= io_apic_read(ioapic
, 1);
2789 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2791 return reg_01
.bits
.entries
;
2795 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2797 struct IO_APIC_route_entry entry
;
2798 unsigned long flags
;
2800 if (!IO_APIC_IRQ(irq
)) {
2801 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2807 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2808 * Note that we mask (disable) IRQs now -- these get enabled when the
2809 * corresponding device driver registers for this IRQ.
2812 memset(&entry
,0,sizeof(entry
));
2814 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2815 entry
.dest_mode
= INT_DEST_MODE
;
2816 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2817 entry
.trigger
= edge_level
;
2818 entry
.polarity
= active_high_low
;
2822 * IRQs < 16 are already in the irq_2_pin[] map
2825 add_pin_to_irq(irq
, ioapic
, pin
);
2827 entry
.vector
= assign_irq_vector(irq
);
2829 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2830 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2831 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
,
2832 edge_level
, active_high_low
);
2834 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2836 if (!ioapic
&& (irq
< 16))
2837 disable_8259A_irq(irq
);
2839 ioapic_write_entry(ioapic
, pin
, entry
);
2840 spin_lock_irqsave(&ioapic_lock
, flags
);
2841 set_native_irq_info(irq
, TARGET_CPUS
);
2842 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2847 #endif /* CONFIG_ACPI */
2849 static int __init
parse_disable_timer_pin_1(char *arg
)
2851 disable_timer_pin_1
= 1;
2854 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2856 static int __init
parse_enable_timer_pin_1(char *arg
)
2858 disable_timer_pin_1
= -1;
2861 early_param("enable_timer_pin_1", parse_enable_timer_pin_1
);
2863 static int __init
parse_noapic(char *arg
)
2865 /* disable IO-APIC */
2866 disable_ioapic_setup();
2869 early_param("noapic", parse_noapic
);