2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
41 #include <asm/timer.h>
42 #include <asm/i8259.h>
44 #include <asm/msidef.h>
45 #include <asm/hypertransport.h>
47 #include <mach_apic.h>
48 #include <mach_apicdef.h>
52 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
53 atomic_t irq_mis_count
;
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
58 static DEFINE_SPINLOCK(ioapic_lock
);
59 static DEFINE_SPINLOCK(vector_lock
);
61 int timer_over_8254 __initdata
= 1;
64 * Is the SiS APIC rmw bug present ?
65 * -1 = don't know, 0 = no, 1 = yes
67 int sis_apic_bug
= -1;
70 * # of IRQ routing registers
72 int nr_ioapic_registers
[MAX_IO_APICS
];
74 static int disable_timer_pin_1 __initdata
;
77 * Rough estimation of how many shared IRQs there are, can
80 #define MAX_PLUS_SHARED_IRQS NR_IRQS
81 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
84 * This is performance-critical, we want to do it O(1)
86 * the indexing order of this array favors 1:1 mappings
87 * between pins and IRQs.
90 static struct irq_pin_list
{
92 } irq_2_pin
[PIN_MAP_SIZE
];
95 struct { u32 w1
, w2
; };
96 struct IO_APIC_route_entry entry
;
99 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
101 union entry_union eu
;
103 spin_lock_irqsave(&ioapic_lock
, flags
);
104 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
105 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
106 spin_unlock_irqrestore(&ioapic_lock
, flags
);
110 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
113 union entry_union eu
;
115 spin_lock_irqsave(&ioapic_lock
, flags
);
116 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
117 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
118 spin_unlock_irqrestore(&ioapic_lock
, flags
);
122 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
123 * shared ISA-space IRQs, so we have to support them. We are super
124 * fast in the common case, and fast for shared ISA-space IRQs.
126 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
128 static int first_free_entry
= NR_IRQS
;
129 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
132 entry
= irq_2_pin
+ entry
->next
;
134 if (entry
->pin
!= -1) {
135 entry
->next
= first_free_entry
;
136 entry
= irq_2_pin
+ entry
->next
;
137 if (++first_free_entry
>= PIN_MAP_SIZE
)
138 panic("io_apic.c: whoops");
145 * Reroute an IRQ to a different pin.
147 static void __init
replace_pin_at_irq(unsigned int irq
,
148 int oldapic
, int oldpin
,
149 int newapic
, int newpin
)
151 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
154 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
155 entry
->apic
= newapic
;
160 entry
= irq_2_pin
+ entry
->next
;
164 static void __modify_IO_APIC_irq (unsigned int irq
, unsigned long enable
, unsigned long disable
)
166 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
167 unsigned int pin
, reg
;
173 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
176 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
179 entry
= irq_2_pin
+ entry
->next
;
184 static void __mask_IO_APIC_irq (unsigned int irq
)
186 __modify_IO_APIC_irq(irq
, 0x00010000, 0);
190 static void __unmask_IO_APIC_irq (unsigned int irq
)
192 __modify_IO_APIC_irq(irq
, 0, 0x00010000);
195 /* mask = 1, trigger = 0 */
196 static void __mask_and_edge_IO_APIC_irq (unsigned int irq
)
198 __modify_IO_APIC_irq(irq
, 0x00010000, 0x00008000);
201 /* mask = 0, trigger = 1 */
202 static void __unmask_and_level_IO_APIC_irq (unsigned int irq
)
204 __modify_IO_APIC_irq(irq
, 0x00008000, 0x00010000);
207 static void mask_IO_APIC_irq (unsigned int irq
)
211 spin_lock_irqsave(&ioapic_lock
, flags
);
212 __mask_IO_APIC_irq(irq
);
213 spin_unlock_irqrestore(&ioapic_lock
, flags
);
216 static void unmask_IO_APIC_irq (unsigned int irq
)
220 spin_lock_irqsave(&ioapic_lock
, flags
);
221 __unmask_IO_APIC_irq(irq
);
222 spin_unlock_irqrestore(&ioapic_lock
, flags
);
225 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
227 struct IO_APIC_route_entry entry
;
229 /* Check delivery_mode to be sure we're not clearing an SMI pin */
230 entry
= ioapic_read_entry(apic
, pin
);
231 if (entry
.delivery_mode
== dest_SMI
)
235 * Disable it in the IO-APIC irq-routing table:
237 memset(&entry
, 0, sizeof(entry
));
239 ioapic_write_entry(apic
, pin
, entry
);
242 static void clear_IO_APIC (void)
246 for (apic
= 0; apic
< nr_ioapics
; apic
++)
247 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
248 clear_IO_APIC_pin(apic
, pin
);
252 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
256 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
257 unsigned int apicid_value
;
260 cpus_and(tmp
, cpumask
, cpu_online_map
);
264 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
266 apicid_value
= cpu_mask_to_apicid(cpumask
);
267 /* Prepare to do the io_apic_write */
268 apicid_value
= apicid_value
<< 24;
269 spin_lock_irqsave(&ioapic_lock
, flags
);
274 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
277 entry
= irq_2_pin
+ entry
->next
;
279 set_native_irq_info(irq
, cpumask
);
280 spin_unlock_irqrestore(&ioapic_lock
, flags
);
283 #if defined(CONFIG_IRQBALANCE)
284 # include <asm/processor.h> /* kernel_thread() */
285 # include <linux/kernel_stat.h> /* kstat */
286 # include <linux/slab.h> /* kmalloc() */
287 # include <linux/timer.h> /* time_after() */
289 #ifdef CONFIG_BALANCED_IRQ_DEBUG
290 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
291 # define Dprintk(x...) do { TDprintk(x); } while (0)
293 # define TDprintk(x...)
294 # define Dprintk(x...)
297 #define IRQBALANCE_CHECK_ARCH -999
298 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
299 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
300 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
301 #define BALANCED_IRQ_LESS_DELTA (HZ)
303 static int irqbalance_disabled __read_mostly
= IRQBALANCE_CHECK_ARCH
;
304 static int physical_balance __read_mostly
;
305 static long balanced_irq_interval __read_mostly
= MAX_BALANCED_IRQ_INTERVAL
;
307 static struct irq_cpu_info
{
308 unsigned long * last_irq
;
309 unsigned long * irq_delta
;
311 } irq_cpu_data
[NR_CPUS
];
313 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
314 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
315 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
317 #define IDLE_ENOUGH(cpu,now) \
318 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
320 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
322 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
324 static cpumask_t balance_irq_affinity
[NR_IRQS
] = {
325 [0 ... NR_IRQS
-1] = CPU_MASK_ALL
328 void set_balance_irq_affinity(unsigned int irq
, cpumask_t mask
)
330 balance_irq_affinity
[irq
] = mask
;
333 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
334 unsigned long now
, int direction
)
342 if (unlikely(cpu
== curr_cpu
))
345 if (direction
== 1) {
354 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
,allowed_mask
) ||
355 (search_idle
&& !IDLE_ENOUGH(cpu
,now
)));
360 static inline void balance_irq(int cpu
, int irq
)
362 unsigned long now
= jiffies
;
363 cpumask_t allowed_mask
;
364 unsigned int new_cpu
;
366 if (irqbalance_disabled
)
369 cpus_and(allowed_mask
, cpu_online_map
, balance_irq_affinity
[irq
]);
370 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
371 if (cpu
!= new_cpu
) {
372 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
376 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
379 Dprintk("Rotating IRQs among CPUs.\n");
380 for_each_online_cpu(i
) {
381 for (j
= 0; j
< NR_IRQS
; j
++) {
382 if (!irq_desc
[j
].action
)
384 /* Is it a significant load ? */
385 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
),j
) <
386 useful_load_threshold
)
391 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
392 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
396 static void do_irq_balance(void)
399 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
400 unsigned long move_this_load
= 0;
401 int max_loaded
= 0, min_loaded
= 0;
403 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
405 int tmp_loaded
, first_attempt
= 1;
406 unsigned long tmp_cpu_irq
;
407 unsigned long imbalance
= 0;
408 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
410 for_each_possible_cpu(i
) {
415 package_index
= CPU_TO_PACKAGEINDEX(i
);
416 for (j
= 0; j
< NR_IRQS
; j
++) {
417 unsigned long value_now
, delta
;
418 /* Is this an active IRQ? */
419 if (!irq_desc
[j
].action
)
421 if ( package_index
== i
)
422 IRQ_DELTA(package_index
,j
) = 0;
423 /* Determine the total count per processor per IRQ */
424 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
426 /* Determine the activity per processor per IRQ */
427 delta
= value_now
- LAST_CPU_IRQ(i
,j
);
429 /* Update last_cpu_irq[][] for the next time */
430 LAST_CPU_IRQ(i
,j
) = value_now
;
432 /* Ignore IRQs whose rate is less than the clock */
433 if (delta
< useful_load_threshold
)
435 /* update the load for the processor or package total */
436 IRQ_DELTA(package_index
,j
) += delta
;
438 /* Keep track of the higher numbered sibling as well */
439 if (i
!= package_index
)
442 * We have sibling A and sibling B in the package
444 * cpu_irq[A] = load for cpu A + load for cpu B
445 * cpu_irq[B] = load for cpu B
447 CPU_IRQ(package_index
) += delta
;
450 /* Find the least loaded processor package */
451 for_each_online_cpu(i
) {
452 if (i
!= CPU_TO_PACKAGEINDEX(i
))
454 if (min_cpu_irq
> CPU_IRQ(i
)) {
455 min_cpu_irq
= CPU_IRQ(i
);
459 max_cpu_irq
= ULONG_MAX
;
462 /* Look for heaviest loaded processor.
463 * We may come back to get the next heaviest loaded processor.
464 * Skip processors with trivial loads.
468 for_each_online_cpu(i
) {
469 if (i
!= CPU_TO_PACKAGEINDEX(i
))
471 if (max_cpu_irq
<= CPU_IRQ(i
))
473 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
474 tmp_cpu_irq
= CPU_IRQ(i
);
479 if (tmp_loaded
== -1) {
480 /* In the case of small number of heavy interrupt sources,
481 * loading some of the cpus too much. We use Ingo's original
482 * approach to rotate them around.
484 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
485 rotate_irqs_among_cpus(useful_load_threshold
);
488 goto not_worth_the_effort
;
491 first_attempt
= 0; /* heaviest search */
492 max_cpu_irq
= tmp_cpu_irq
; /* load */
493 max_loaded
= tmp_loaded
; /* processor */
494 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
496 Dprintk("max_loaded cpu = %d\n", max_loaded
);
497 Dprintk("min_loaded cpu = %d\n", min_loaded
);
498 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq
);
499 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq
);
500 Dprintk("load imbalance = %lu\n", imbalance
);
502 /* if imbalance is less than approx 10% of max load, then
503 * observe diminishing returns action. - quit
505 if (imbalance
< (max_cpu_irq
>> 3)) {
506 Dprintk("Imbalance too trivial\n");
507 goto not_worth_the_effort
;
511 /* if we select an IRQ to move that can't go where we want, then
512 * see if there is another one to try.
516 for (j
= 0; j
< NR_IRQS
; j
++) {
517 /* Is this an active IRQ? */
518 if (!irq_desc
[j
].action
)
520 if (imbalance
<= IRQ_DELTA(max_loaded
,j
))
522 /* Try to find the IRQ that is closest to the imbalance
523 * without going over.
525 if (move_this_load
< IRQ_DELTA(max_loaded
,j
)) {
526 move_this_load
= IRQ_DELTA(max_loaded
,j
);
530 if (selected_irq
== -1) {
534 imbalance
= move_this_load
;
536 /* For physical_balance case, we accumlated both load
537 * values in the one of the siblings cpu_irq[],
538 * to use the same code for physical and logical processors
539 * as much as possible.
541 * NOTE: the cpu_irq[] array holds the sum of the load for
542 * sibling A and sibling B in the slot for the lowest numbered
543 * sibling (A), _AND_ the load for sibling B in the slot for
544 * the higher numbered sibling.
546 * We seek the least loaded sibling by making the comparison
549 load
= CPU_IRQ(min_loaded
) >> 1;
550 for_each_cpu_mask(j
, cpu_sibling_map
[min_loaded
]) {
551 if (load
> CPU_IRQ(j
)) {
552 /* This won't change cpu_sibling_map[min_loaded] */
558 cpus_and(allowed_mask
,
560 balance_irq_affinity
[selected_irq
]);
561 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
562 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
564 if (!cpus_empty(tmp
)) {
566 Dprintk("irq = %d moved to cpu = %d\n",
567 selected_irq
, min_loaded
);
568 /* mark for change destination */
569 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
571 /* Since we made a change, come back sooner to
572 * check for more variation.
574 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
575 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
580 not_worth_the_effort
:
582 * if we did not find an IRQ to move, then adjust the time interval
585 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
586 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
587 Dprintk("IRQ worth rotating not found\n");
591 static int balanced_irq(void *unused
)
594 unsigned long prev_balance_time
= jiffies
;
595 long time_remaining
= balanced_irq_interval
;
599 /* push everything to CPU 0 to give us a starting point. */
600 for (i
= 0 ; i
< NR_IRQS
; i
++) {
601 irq_desc
[i
].pending_mask
= cpumask_of_cpu(0);
602 set_pending_irq(i
, cpumask_of_cpu(0));
606 time_remaining
= schedule_timeout_interruptible(time_remaining
);
608 if (time_after(jiffies
,
609 prev_balance_time
+balanced_irq_interval
)) {
612 prev_balance_time
= jiffies
;
613 time_remaining
= balanced_irq_interval
;
620 static int __init
balanced_irq_init(void)
623 struct cpuinfo_x86
*c
;
626 cpus_shift_right(tmp
, cpu_online_map
, 2);
628 /* When not overwritten by the command line ask subarchitecture. */
629 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
630 irqbalance_disabled
= NO_BALANCE_IRQ
;
631 if (irqbalance_disabled
)
634 /* disable irqbalance completely if there is only one processor online */
635 if (num_online_cpus() < 2) {
636 irqbalance_disabled
= 1;
640 * Enable physical balance only if more than 1 physical processor
643 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
644 physical_balance
= 1;
646 for_each_online_cpu(i
) {
647 irq_cpu_data
[i
].irq_delta
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
648 irq_cpu_data
[i
].last_irq
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
649 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
650 printk(KERN_ERR
"balanced_irq_init: out of memory");
653 memset(irq_cpu_data
[i
].irq_delta
,0,sizeof(unsigned long) * NR_IRQS
);
654 memset(irq_cpu_data
[i
].last_irq
,0,sizeof(unsigned long) * NR_IRQS
);
657 printk(KERN_INFO
"Starting balanced_irq\n");
658 if (kernel_thread(balanced_irq
, NULL
, CLONE_KERNEL
) >= 0)
661 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
663 for_each_possible_cpu(i
) {
664 kfree(irq_cpu_data
[i
].irq_delta
);
665 irq_cpu_data
[i
].irq_delta
= NULL
;
666 kfree(irq_cpu_data
[i
].last_irq
);
667 irq_cpu_data
[i
].last_irq
= NULL
;
672 int __init
irqbalance_disable(char *str
)
674 irqbalance_disabled
= 1;
678 __setup("noirqbalance", irqbalance_disable
);
680 late_initcall(balanced_irq_init
);
681 #endif /* CONFIG_IRQBALANCE */
682 #endif /* CONFIG_SMP */
685 void fastcall
send_IPI_self(int vector
)
692 apic_wait_icr_idle();
693 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
695 * Send the IPI. The write to APIC_ICR fires this off.
697 apic_write_around(APIC_ICR
, cfg
);
699 #endif /* !CONFIG_SMP */
703 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
704 * specific CPU-side IRQs.
708 static int pirq_entries
[MAX_PIRQS
];
709 static int pirqs_enabled
;
710 int skip_ioapic_setup
;
712 static int __init
ioapic_setup(char *str
)
714 skip_ioapic_setup
= 1;
718 __setup("noapic", ioapic_setup
);
720 static int __init
ioapic_pirq_setup(char *str
)
723 int ints
[MAX_PIRQS
+1];
725 get_options(str
, ARRAY_SIZE(ints
), ints
);
727 for (i
= 0; i
< MAX_PIRQS
; i
++)
728 pirq_entries
[i
] = -1;
731 apic_printk(APIC_VERBOSE
, KERN_INFO
732 "PIRQ redirection, working around broken MP-BIOS.\n");
734 if (ints
[0] < MAX_PIRQS
)
737 for (i
= 0; i
< max
; i
++) {
738 apic_printk(APIC_VERBOSE
, KERN_DEBUG
739 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
741 * PIRQs are mapped upside down, usually.
743 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
748 __setup("pirq=", ioapic_pirq_setup
);
751 * Find the IRQ entry number of a certain pin.
753 static int find_irq_entry(int apic
, int pin
, int type
)
757 for (i
= 0; i
< mp_irq_entries
; i
++)
758 if (mp_irqs
[i
].mpc_irqtype
== type
&&
759 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
760 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
761 mp_irqs
[i
].mpc_dstirq
== pin
)
768 * Find the pin to which IRQ[irq] (ISA) is connected
770 static int __init
find_isa_irq_pin(int irq
, int type
)
774 for (i
= 0; i
< mp_irq_entries
; i
++) {
775 int lbus
= mp_irqs
[i
].mpc_srcbus
;
777 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
778 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
779 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
||
780 mp_bus_id_to_type
[lbus
] == MP_BUS_NEC98
782 (mp_irqs
[i
].mpc_irqtype
== type
) &&
783 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
785 return mp_irqs
[i
].mpc_dstirq
;
790 static int __init
find_isa_irq_apic(int irq
, int type
)
794 for (i
= 0; i
< mp_irq_entries
; i
++) {
795 int lbus
= mp_irqs
[i
].mpc_srcbus
;
797 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
798 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
799 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
||
800 mp_bus_id_to_type
[lbus
] == MP_BUS_NEC98
802 (mp_irqs
[i
].mpc_irqtype
== type
) &&
803 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
806 if (i
< mp_irq_entries
) {
808 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
809 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
818 * Find a specific PCI IRQ entry.
819 * Not an __init, possibly needed by modules
821 static int pin_2_irq(int idx
, int apic
, int pin
);
823 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
825 int apic
, i
, best_guess
= -1;
827 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
828 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
829 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
830 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
833 for (i
= 0; i
< mp_irq_entries
; i
++) {
834 int lbus
= mp_irqs
[i
].mpc_srcbus
;
836 for (apic
= 0; apic
< nr_ioapics
; apic
++)
837 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
838 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
841 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
842 !mp_irqs
[i
].mpc_irqtype
&&
844 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
845 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
847 if (!(apic
|| IO_APIC_IRQ(irq
)))
850 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
853 * Use the first all-but-pin matching entry as a
854 * best-guess fuzzy result for broken mptables.
862 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
865 * This function currently is only a helper for the i386 smp boot process where
866 * we need to reprogram the ioredtbls to cater for the cpus which have come online
867 * so mask in all cases should simply be TARGET_CPUS
870 void __init
setup_ioapic_dest(void)
872 int pin
, ioapic
, irq
, irq_entry
;
874 if (skip_ioapic_setup
== 1)
877 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
878 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
879 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
882 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
883 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
891 * EISA Edge/Level control register, ELCR
893 static int EISA_ELCR(unsigned int irq
)
896 unsigned int port
= 0x4d0 + (irq
>> 3);
897 return (inb(port
) >> (irq
& 7)) & 1;
899 apic_printk(APIC_VERBOSE
, KERN_INFO
900 "Broken MPtable reports ISA irq %d\n", irq
);
904 /* EISA interrupts are always polarity zero and can be edge or level
905 * trigger depending on the ELCR value. If an interrupt is listed as
906 * EISA conforming in the MP table, that means its trigger type must
907 * be read in from the ELCR */
909 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
910 #define default_EISA_polarity(idx) (0)
912 /* ISA interrupts are always polarity zero edge triggered,
913 * when listed as conforming in the MP table. */
915 #define default_ISA_trigger(idx) (0)
916 #define default_ISA_polarity(idx) (0)
918 /* PCI interrupts are always polarity one level triggered,
919 * when listed as conforming in the MP table. */
921 #define default_PCI_trigger(idx) (1)
922 #define default_PCI_polarity(idx) (1)
924 /* MCA interrupts are always polarity zero level triggered,
925 * when listed as conforming in the MP table. */
927 #define default_MCA_trigger(idx) (1)
928 #define default_MCA_polarity(idx) (0)
930 /* NEC98 interrupts are always polarity zero edge triggered,
931 * when listed as conforming in the MP table. */
933 #define default_NEC98_trigger(idx) (0)
934 #define default_NEC98_polarity(idx) (0)
936 static int __init
MPBIOS_polarity(int idx
)
938 int bus
= mp_irqs
[idx
].mpc_srcbus
;
942 * Determine IRQ line polarity (high active or low active):
944 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
946 case 0: /* conforms, ie. bus-type dependent polarity */
948 switch (mp_bus_id_to_type
[bus
])
950 case MP_BUS_ISA
: /* ISA pin */
952 polarity
= default_ISA_polarity(idx
);
955 case MP_BUS_EISA
: /* EISA pin */
957 polarity
= default_EISA_polarity(idx
);
960 case MP_BUS_PCI
: /* PCI pin */
962 polarity
= default_PCI_polarity(idx
);
965 case MP_BUS_MCA
: /* MCA pin */
967 polarity
= default_MCA_polarity(idx
);
970 case MP_BUS_NEC98
: /* NEC 98 pin */
972 polarity
= default_NEC98_polarity(idx
);
977 printk(KERN_WARNING
"broken BIOS!!\n");
984 case 1: /* high active */
989 case 2: /* reserved */
991 printk(KERN_WARNING
"broken BIOS!!\n");
995 case 3: /* low active */
1000 default: /* invalid */
1002 printk(KERN_WARNING
"broken BIOS!!\n");
1010 static int MPBIOS_trigger(int idx
)
1012 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1016 * Determine IRQ trigger mode (edge or level sensitive):
1018 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
1020 case 0: /* conforms, ie. bus-type dependent */
1022 switch (mp_bus_id_to_type
[bus
])
1024 case MP_BUS_ISA
: /* ISA pin */
1026 trigger
= default_ISA_trigger(idx
);
1029 case MP_BUS_EISA
: /* EISA pin */
1031 trigger
= default_EISA_trigger(idx
);
1034 case MP_BUS_PCI
: /* PCI pin */
1036 trigger
= default_PCI_trigger(idx
);
1039 case MP_BUS_MCA
: /* MCA pin */
1041 trigger
= default_MCA_trigger(idx
);
1044 case MP_BUS_NEC98
: /* NEC 98 pin */
1046 trigger
= default_NEC98_trigger(idx
);
1051 printk(KERN_WARNING
"broken BIOS!!\n");
1063 case 2: /* reserved */
1065 printk(KERN_WARNING
"broken BIOS!!\n");
1074 default: /* invalid */
1076 printk(KERN_WARNING
"broken BIOS!!\n");
1084 static inline int irq_polarity(int idx
)
1086 return MPBIOS_polarity(idx
);
1089 static inline int irq_trigger(int idx
)
1091 return MPBIOS_trigger(idx
);
1094 static int pin_2_irq(int idx
, int apic
, int pin
)
1097 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1100 * Debugging check, we are in big trouble if this message pops up!
1102 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
1103 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1105 switch (mp_bus_id_to_type
[bus
])
1107 case MP_BUS_ISA
: /* ISA pin */
1112 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
1115 case MP_BUS_PCI
: /* PCI pin */
1118 * PCI IRQs are mapped in order
1122 irq
+= nr_ioapic_registers
[i
++];
1126 * For MPS mode, so far only needed by ES7000 platform
1128 if (ioapic_renumber_irq
)
1129 irq
= ioapic_renumber_irq(apic
, irq
);
1135 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
1142 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1144 if ((pin
>= 16) && (pin
<= 23)) {
1145 if (pirq_entries
[pin
-16] != -1) {
1146 if (!pirq_entries
[pin
-16]) {
1147 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1148 "disabling PIRQ%d\n", pin
-16);
1150 irq
= pirq_entries
[pin
-16];
1151 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1152 "using PIRQ%d -> IRQ %d\n",
1160 static inline int IO_APIC_irq_trigger(int irq
)
1164 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1165 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1166 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1167 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
1168 return irq_trigger(idx
);
1172 * nonexistent IRQs are edge default
1177 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1178 u8 irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_DEVICE_VECTOR
, 0 };
1180 static int __assign_irq_vector(int irq
)
1182 static int current_vector
= FIRST_DEVICE_VECTOR
, offset
= 0;
1185 BUG_ON((unsigned)irq
>= NR_IRQ_VECTORS
);
1187 if (IO_APIC_VECTOR(irq
) > 0)
1188 return IO_APIC_VECTOR(irq
);
1190 current_vector
+= 8;
1191 if (current_vector
== SYSCALL_VECTOR
)
1192 current_vector
+= 8;
1194 if (current_vector
>= FIRST_SYSTEM_VECTOR
) {
1198 current_vector
= FIRST_DEVICE_VECTOR
+ offset
;
1201 vector
= current_vector
;
1202 IO_APIC_VECTOR(irq
) = vector
;
1207 static int assign_irq_vector(int irq
)
1209 unsigned long flags
;
1212 spin_lock_irqsave(&vector_lock
, flags
);
1213 vector
= __assign_irq_vector(irq
);
1214 spin_unlock_irqrestore(&vector_lock
, flags
);
1218 static struct irq_chip ioapic_chip
;
1220 #define IOAPIC_AUTO -1
1221 #define IOAPIC_EDGE 0
1222 #define IOAPIC_LEVEL 1
1224 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1226 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1227 trigger
== IOAPIC_LEVEL
)
1228 set_irq_chip_and_handler(irq
, &ioapic_chip
,
1229 handle_fasteoi_irq
);
1231 set_irq_chip_and_handler(irq
, &ioapic_chip
,
1233 set_intr_gate(vector
, interrupt
[irq
]);
1236 static void __init
setup_IO_APIC_irqs(void)
1238 struct IO_APIC_route_entry entry
;
1239 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1240 unsigned long flags
;
1242 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1244 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1245 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1248 * add it to the IO-APIC irq-routing table:
1250 memset(&entry
,0,sizeof(entry
));
1252 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1253 entry
.dest_mode
= INT_DEST_MODE
;
1254 entry
.mask
= 0; /* enable IRQ */
1255 entry
.dest
.logical
.logical_dest
=
1256 cpu_mask_to_apicid(TARGET_CPUS
);
1258 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1261 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1262 " IO-APIC (apicid-pin) %d-%d",
1263 mp_ioapics
[apic
].mpc_apicid
,
1267 apic_printk(APIC_VERBOSE
, ", %d-%d",
1268 mp_ioapics
[apic
].mpc_apicid
, pin
);
1272 entry
.trigger
= irq_trigger(idx
);
1273 entry
.polarity
= irq_polarity(idx
);
1275 if (irq_trigger(idx
)) {
1280 irq
= pin_2_irq(idx
, apic
, pin
);
1282 * skip adding the timer int on secondary nodes, which causes
1283 * a small but painful rift in the time-space continuum
1285 if (multi_timer_check(apic
, irq
))
1288 add_pin_to_irq(irq
, apic
, pin
);
1290 if (!apic
&& !IO_APIC_IRQ(irq
))
1293 if (IO_APIC_IRQ(irq
)) {
1294 vector
= assign_irq_vector(irq
);
1295 entry
.vector
= vector
;
1296 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1298 if (!apic
&& (irq
< 16))
1299 disable_8259A_irq(irq
);
1301 ioapic_write_entry(apic
, pin
, entry
);
1302 spin_lock_irqsave(&ioapic_lock
, flags
);
1303 set_native_irq_info(irq
, TARGET_CPUS
);
1304 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1309 apic_printk(APIC_VERBOSE
, " not connected.\n");
1313 * Set up the 8259A-master output pin:
1315 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
1317 struct IO_APIC_route_entry entry
;
1319 memset(&entry
,0,sizeof(entry
));
1321 disable_8259A_irq(0);
1324 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1327 * We use logical delivery to get the timer IRQ
1330 entry
.dest_mode
= INT_DEST_MODE
;
1331 entry
.mask
= 0; /* unmask IRQ now */
1332 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1333 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1336 entry
.vector
= vector
;
1339 * The timer IRQ doesn't have to know that behind the
1340 * scene we have a 8259A-master in AEOI mode ...
1342 irq_desc
[0].chip
= &ioapic_chip
;
1343 set_irq_handler(0, handle_edge_irq
);
1346 * Add it to the IO-APIC irq-routing table:
1348 ioapic_write_entry(apic
, pin
, entry
);
1350 enable_8259A_irq(0);
1353 static inline void UNEXPECTED_IO_APIC(void)
1357 void __init
print_IO_APIC(void)
1360 union IO_APIC_reg_00 reg_00
;
1361 union IO_APIC_reg_01 reg_01
;
1362 union IO_APIC_reg_02 reg_02
;
1363 union IO_APIC_reg_03 reg_03
;
1364 unsigned long flags
;
1366 if (apic_verbosity
== APIC_QUIET
)
1369 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1370 for (i
= 0; i
< nr_ioapics
; i
++)
1371 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1372 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
1375 * We are a bit conservative about what we expect. We have to
1376 * know about every hardware change ASAP.
1378 printk(KERN_INFO
"testing the IO APIC.......................\n");
1380 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1382 spin_lock_irqsave(&ioapic_lock
, flags
);
1383 reg_00
.raw
= io_apic_read(apic
, 0);
1384 reg_01
.raw
= io_apic_read(apic
, 1);
1385 if (reg_01
.bits
.version
>= 0x10)
1386 reg_02
.raw
= io_apic_read(apic
, 2);
1387 if (reg_01
.bits
.version
>= 0x20)
1388 reg_03
.raw
= io_apic_read(apic
, 3);
1389 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1391 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
1392 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1393 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1394 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1395 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1396 if (reg_00
.bits
.ID
>= get_physical_broadcast())
1397 UNEXPECTED_IO_APIC();
1398 if (reg_00
.bits
.__reserved_1
|| reg_00
.bits
.__reserved_2
)
1399 UNEXPECTED_IO_APIC();
1401 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1402 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1403 if ( (reg_01
.bits
.entries
!= 0x0f) && /* older (Neptune) boards */
1404 (reg_01
.bits
.entries
!= 0x17) && /* typical ISA+PCI boards */
1405 (reg_01
.bits
.entries
!= 0x1b) && /* Compaq Proliant boards */
1406 (reg_01
.bits
.entries
!= 0x1f) && /* dual Xeon boards */
1407 (reg_01
.bits
.entries
!= 0x22) && /* bigger Xeon boards */
1408 (reg_01
.bits
.entries
!= 0x2E) &&
1409 (reg_01
.bits
.entries
!= 0x3F)
1411 UNEXPECTED_IO_APIC();
1413 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1414 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1415 if ( (reg_01
.bits
.version
!= 0x01) && /* 82489DX IO-APICs */
1416 (reg_01
.bits
.version
!= 0x10) && /* oldest IO-APICs */
1417 (reg_01
.bits
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
1418 (reg_01
.bits
.version
!= 0x13) && /* Xeon IO-APICs */
1419 (reg_01
.bits
.version
!= 0x20) /* Intel P64H (82806 AA) */
1421 UNEXPECTED_IO_APIC();
1422 if (reg_01
.bits
.__reserved_1
|| reg_01
.bits
.__reserved_2
)
1423 UNEXPECTED_IO_APIC();
1426 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1427 * but the value of reg_02 is read as the previous read register
1428 * value, so ignore it if reg_02 == reg_01.
1430 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1431 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1432 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1433 if (reg_02
.bits
.__reserved_1
|| reg_02
.bits
.__reserved_2
)
1434 UNEXPECTED_IO_APIC();
1438 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1439 * or reg_03, but the value of reg_0[23] is read as the previous read
1440 * register value, so ignore it if reg_03 == reg_0[12].
1442 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1443 reg_03
.raw
!= reg_01
.raw
) {
1444 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1445 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1446 if (reg_03
.bits
.__reserved_1
)
1447 UNEXPECTED_IO_APIC();
1450 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1452 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1453 " Stat Dest Deli Vect: \n");
1455 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1456 struct IO_APIC_route_entry entry
;
1458 entry
= ioapic_read_entry(apic
, i
);
1460 printk(KERN_DEBUG
" %02x %03X %02X ",
1462 entry
.dest
.logical
.logical_dest
,
1463 entry
.dest
.physical
.physical_dest
1466 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1471 entry
.delivery_status
,
1473 entry
.delivery_mode
,
1478 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1479 for (i
= 0; i
< NR_IRQS
; i
++) {
1480 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1483 printk(KERN_DEBUG
"IRQ%d ", i
);
1485 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1488 entry
= irq_2_pin
+ entry
->next
;
1493 printk(KERN_INFO
".................................... done.\n");
1500 static void print_APIC_bitfield (int base
)
1505 if (apic_verbosity
== APIC_QUIET
)
1508 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1509 for (i
= 0; i
< 8; i
++) {
1510 v
= apic_read(base
+ i
*0x10);
1511 for (j
= 0; j
< 32; j
++) {
1521 void /*__init*/ print_local_APIC(void * dummy
)
1523 unsigned int v
, ver
, maxlvt
;
1525 if (apic_verbosity
== APIC_QUIET
)
1528 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1529 smp_processor_id(), hard_smp_processor_id());
1530 v
= apic_read(APIC_ID
);
1531 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
1532 v
= apic_read(APIC_LVR
);
1533 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1534 ver
= GET_APIC_VERSION(v
);
1535 maxlvt
= get_maxlvt();
1537 v
= apic_read(APIC_TASKPRI
);
1538 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1540 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1541 v
= apic_read(APIC_ARBPRI
);
1542 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1543 v
& APIC_ARBPRI_MASK
);
1544 v
= apic_read(APIC_PROCPRI
);
1545 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1548 v
= apic_read(APIC_EOI
);
1549 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1550 v
= apic_read(APIC_RRR
);
1551 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1552 v
= apic_read(APIC_LDR
);
1553 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1554 v
= apic_read(APIC_DFR
);
1555 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1556 v
= apic_read(APIC_SPIV
);
1557 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1559 printk(KERN_DEBUG
"... APIC ISR field:\n");
1560 print_APIC_bitfield(APIC_ISR
);
1561 printk(KERN_DEBUG
"... APIC TMR field:\n");
1562 print_APIC_bitfield(APIC_TMR
);
1563 printk(KERN_DEBUG
"... APIC IRR field:\n");
1564 print_APIC_bitfield(APIC_IRR
);
1566 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1567 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1568 apic_write(APIC_ESR
, 0);
1569 v
= apic_read(APIC_ESR
);
1570 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1573 v
= apic_read(APIC_ICR
);
1574 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1575 v
= apic_read(APIC_ICR2
);
1576 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1578 v
= apic_read(APIC_LVTT
);
1579 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1581 if (maxlvt
> 3) { /* PC is LVT#4. */
1582 v
= apic_read(APIC_LVTPC
);
1583 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1585 v
= apic_read(APIC_LVT0
);
1586 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1587 v
= apic_read(APIC_LVT1
);
1588 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1590 if (maxlvt
> 2) { /* ERR is LVT#3. */
1591 v
= apic_read(APIC_LVTERR
);
1592 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1595 v
= apic_read(APIC_TMICT
);
1596 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1597 v
= apic_read(APIC_TMCCT
);
1598 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1599 v
= apic_read(APIC_TDCR
);
1600 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1604 void print_all_local_APICs (void)
1606 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1609 void /*__init*/ print_PIC(void)
1612 unsigned long flags
;
1614 if (apic_verbosity
== APIC_QUIET
)
1617 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1619 spin_lock_irqsave(&i8259A_lock
, flags
);
1621 v
= inb(0xa1) << 8 | inb(0x21);
1622 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1624 v
= inb(0xa0) << 8 | inb(0x20);
1625 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1629 v
= inb(0xa0) << 8 | inb(0x20);
1633 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1635 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1637 v
= inb(0x4d1) << 8 | inb(0x4d0);
1638 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1643 static void __init
enable_IO_APIC(void)
1645 union IO_APIC_reg_01 reg_01
;
1646 int i8259_apic
, i8259_pin
;
1648 unsigned long flags
;
1650 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1651 irq_2_pin
[i
].pin
= -1;
1652 irq_2_pin
[i
].next
= 0;
1655 for (i
= 0; i
< MAX_PIRQS
; i
++)
1656 pirq_entries
[i
] = -1;
1659 * The number of IO-APIC IRQ registers (== #pins):
1661 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1662 spin_lock_irqsave(&ioapic_lock
, flags
);
1663 reg_01
.raw
= io_apic_read(apic
, 1);
1664 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1665 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1667 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1669 /* See if any of the pins is in ExtINT mode */
1670 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1671 struct IO_APIC_route_entry entry
;
1672 entry
= ioapic_read_entry(apic
, pin
);
1675 /* If the interrupt line is enabled and in ExtInt mode
1676 * I have found the pin where the i8259 is connected.
1678 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1679 ioapic_i8259
.apic
= apic
;
1680 ioapic_i8259
.pin
= pin
;
1686 /* Look to see what if the MP table has reported the ExtINT */
1687 /* If we could not find the appropriate pin by looking at the ioapic
1688 * the i8259 probably is not connected the ioapic but give the
1689 * mptable a chance anyway.
1691 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1692 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1693 /* Trust the MP table if nothing is setup in the hardware */
1694 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1695 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1696 ioapic_i8259
.pin
= i8259_pin
;
1697 ioapic_i8259
.apic
= i8259_apic
;
1699 /* Complain if the MP table and the hardware disagree */
1700 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1701 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1703 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1707 * Do not trust the IO-APIC being empty at bootup
1713 * Not an __init, needed by the reboot code
1715 void disable_IO_APIC(void)
1718 * Clear the IO-APIC before rebooting:
1723 * If the i8259 is routed through an IOAPIC
1724 * Put that IOAPIC in virtual wire mode
1725 * so legacy interrupts can be delivered.
1727 if (ioapic_i8259
.pin
!= -1) {
1728 struct IO_APIC_route_entry entry
;
1730 memset(&entry
, 0, sizeof(entry
));
1731 entry
.mask
= 0; /* Enabled */
1732 entry
.trigger
= 0; /* Edge */
1734 entry
.polarity
= 0; /* High */
1735 entry
.delivery_status
= 0;
1736 entry
.dest_mode
= 0; /* Physical */
1737 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1739 entry
.dest
.physical
.physical_dest
=
1740 GET_APIC_ID(apic_read(APIC_ID
));
1743 * Add it to the IO-APIC irq-routing table:
1745 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1747 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1751 * function to set the IO-APIC physical IDs based on the
1752 * values stored in the MPC table.
1754 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1757 #ifndef CONFIG_X86_NUMAQ
1758 static void __init
setup_ioapic_ids_from_mpc(void)
1760 union IO_APIC_reg_00 reg_00
;
1761 physid_mask_t phys_id_present_map
;
1764 unsigned char old_id
;
1765 unsigned long flags
;
1768 * Don't check I/O APIC IDs for xAPIC systems. They have
1769 * no meaning without the serial APIC bus.
1771 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1772 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1775 * This is broken; anything with a real cpu count has to
1776 * circumvent this idiocy regardless.
1778 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1781 * Set the IOAPIC ID to the value stored in the MPC table.
1783 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1785 /* Read the register 0 value */
1786 spin_lock_irqsave(&ioapic_lock
, flags
);
1787 reg_00
.raw
= io_apic_read(apic
, 0);
1788 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1790 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1792 if (mp_ioapics
[apic
].mpc_apicid
>= get_physical_broadcast()) {
1793 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1794 apic
, mp_ioapics
[apic
].mpc_apicid
);
1795 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1797 mp_ioapics
[apic
].mpc_apicid
= reg_00
.bits
.ID
;
1801 * Sanity check, is the ID really free? Every APIC in a
1802 * system must have a unique ID or we get lots of nice
1803 * 'stuck on smp_invalidate_needed IPI wait' messages.
1805 if (check_apicid_used(phys_id_present_map
,
1806 mp_ioapics
[apic
].mpc_apicid
)) {
1807 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1808 apic
, mp_ioapics
[apic
].mpc_apicid
);
1809 for (i
= 0; i
< get_physical_broadcast(); i
++)
1810 if (!physid_isset(i
, phys_id_present_map
))
1812 if (i
>= get_physical_broadcast())
1813 panic("Max APIC ID exceeded!\n");
1814 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1816 physid_set(i
, phys_id_present_map
);
1817 mp_ioapics
[apic
].mpc_apicid
= i
;
1820 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mpc_apicid
);
1821 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1822 "phys_id_present_map\n",
1823 mp_ioapics
[apic
].mpc_apicid
);
1824 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1829 * We need to adjust the IRQ routing table
1830 * if the ID changed.
1832 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1833 for (i
= 0; i
< mp_irq_entries
; i
++)
1834 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1835 mp_irqs
[i
].mpc_dstapic
1836 = mp_ioapics
[apic
].mpc_apicid
;
1839 * Read the right value from the MPC table and
1840 * write it into the ID register.
1842 apic_printk(APIC_VERBOSE
, KERN_INFO
1843 "...changing IO-APIC physical APIC ID to %d ...",
1844 mp_ioapics
[apic
].mpc_apicid
);
1846 reg_00
.bits
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1847 spin_lock_irqsave(&ioapic_lock
, flags
);
1848 io_apic_write(apic
, 0, reg_00
.raw
);
1849 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1854 spin_lock_irqsave(&ioapic_lock
, flags
);
1855 reg_00
.raw
= io_apic_read(apic
, 0);
1856 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1857 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1858 printk("could not set ID!\n");
1860 apic_printk(APIC_VERBOSE
, " ok.\n");
1864 static void __init
setup_ioapic_ids_from_mpc(void) { }
1868 * There is a nasty bug in some older SMP boards, their mptable lies
1869 * about the timer IRQ. We do the following to work around the situation:
1871 * - timer IRQ defaults to IO-APIC IRQ
1872 * - if this function detects that timer IRQs are defunct, then we fall
1873 * back to ISA timer IRQs
1875 static int __init
timer_irq_works(void)
1877 unsigned long t1
= jiffies
;
1880 /* Let ten ticks pass... */
1881 mdelay((10 * 1000) / HZ
);
1884 * Expect a few ticks at least, to be sure some possible
1885 * glue logic does not lock up after one or two first
1886 * ticks in a non-ExtINT mode. Also the local APIC
1887 * might have cached one ExtINT interrupt. Finally, at
1888 * least one tick may be lost due to delays.
1890 if (jiffies
- t1
> 4)
1897 * In the SMP+IOAPIC case it might happen that there are an unspecified
1898 * number of pending IRQ events unhandled. These cases are very rare,
1899 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1900 * better to do it this way as thus we do not have to be aware of
1901 * 'pending' interrupts in the IRQ path, except at this point.
1904 * Edge triggered needs to resend any interrupt
1905 * that was delayed but this is now handled in the device
1912 * Starting up a edge-triggered IO-APIC interrupt is
1913 * nasty - we need to make sure that we get the edge.
1914 * If it is already asserted for some reason, we need
1915 * return 1 to indicate that is was pending.
1917 * This is not complete - we should be able to fake
1918 * an edge even if it isn't on the 8259A...
1920 * (We do this for level-triggered IRQs too - it cannot hurt.)
1922 static unsigned int startup_ioapic_irq(unsigned int irq
)
1924 int was_pending
= 0;
1925 unsigned long flags
;
1927 spin_lock_irqsave(&ioapic_lock
, flags
);
1929 disable_8259A_irq(irq
);
1930 if (i8259A_irq_pending(irq
))
1933 __unmask_IO_APIC_irq(irq
);
1934 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1939 static void ack_ioapic_irq(unsigned int irq
)
1941 move_native_irq(irq
);
1945 static void ack_ioapic_quirk_irq(unsigned int irq
)
1950 move_native_irq(irq
);
1952 * It appears there is an erratum which affects at least version 0x11
1953 * of I/O APIC (that's the 82093AA and cores integrated into various
1954 * chipsets). Under certain conditions a level-triggered interrupt is
1955 * erroneously delivered as edge-triggered one but the respective IRR
1956 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1957 * message but it will never arrive and further interrupts are blocked
1958 * from the source. The exact reason is so far unknown, but the
1959 * phenomenon was observed when two consecutive interrupt requests
1960 * from a given source get delivered to the same CPU and the source is
1961 * temporarily disabled in between.
1963 * A workaround is to simulate an EOI message manually. We achieve it
1964 * by setting the trigger mode to edge and then to level when the edge
1965 * trigger mode gets detected in the TMR of a local APIC for a
1966 * level-triggered interrupt. We mask the source for the time of the
1967 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1968 * The idea is from Manfred Spraul. --macro
1970 i
= IO_APIC_VECTOR(irq
);
1972 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1976 if (!(v
& (1 << (i
& 0x1f)))) {
1977 atomic_inc(&irq_mis_count
);
1978 spin_lock(&ioapic_lock
);
1979 __mask_and_edge_IO_APIC_irq(irq
);
1980 __unmask_and_level_IO_APIC_irq(irq
);
1981 spin_unlock(&ioapic_lock
);
1985 static int ioapic_retrigger_irq(unsigned int irq
)
1987 send_IPI_self(IO_APIC_VECTOR(irq
));
1992 static struct irq_chip ioapic_chip __read_mostly
= {
1994 .startup
= startup_ioapic_irq
,
1995 .mask
= mask_IO_APIC_irq
,
1996 .unmask
= unmask_IO_APIC_irq
,
1997 .ack
= ack_ioapic_irq
,
1998 .eoi
= ack_ioapic_quirk_irq
,
2000 .set_affinity
= set_ioapic_affinity_irq
,
2002 .retrigger
= ioapic_retrigger_irq
,
2006 static inline void init_IO_APIC_traps(void)
2011 * NOTE! The local APIC isn't very good at handling
2012 * multiple interrupts at the same interrupt level.
2013 * As the interrupt level is determined by taking the
2014 * vector number and shifting that right by 4, we
2015 * want to spread these out a bit so that they don't
2016 * all fall in the same interrupt level.
2018 * Also, we've got to be careful not to trash gate
2019 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2021 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
2023 if (IO_APIC_IRQ(tmp
) && !IO_APIC_VECTOR(tmp
)) {
2025 * Hmm.. We don't have an entry for this,
2026 * so default to an old-fashioned 8259
2027 * interrupt if we can..
2030 make_8259A_irq(irq
);
2032 /* Strange. Oh, well.. */
2033 irq_desc
[irq
].chip
= &no_irq_chip
;
2039 * The local APIC irq-chip implementation:
2042 static void ack_apic(unsigned int irq
)
2047 static void mask_lapic_irq (unsigned int irq
)
2051 v
= apic_read(APIC_LVT0
);
2052 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2055 static void unmask_lapic_irq (unsigned int irq
)
2059 v
= apic_read(APIC_LVT0
);
2060 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2063 static struct irq_chip lapic_chip __read_mostly
= {
2064 .name
= "local-APIC-edge",
2065 .mask
= mask_lapic_irq
,
2066 .unmask
= unmask_lapic_irq
,
2070 static void setup_nmi (void)
2073 * Dirty trick to enable the NMI watchdog ...
2074 * We put the 8259A master into AEOI mode and
2075 * unmask on all local APICs LVT0 as NMI.
2077 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2078 * is from Maciej W. Rozycki - so we do not have to EOI from
2079 * the NMI handler or the timer interrupt.
2081 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2083 on_each_cpu(enable_NMI_through_LVT0
, NULL
, 1, 1);
2085 apic_printk(APIC_VERBOSE
, " done.\n");
2089 * This looks a bit hackish but it's about the only one way of sending
2090 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2091 * not support the ExtINT mode, unfortunately. We need to send these
2092 * cycles as some i82489DX-based boards have glue logic that keeps the
2093 * 8259A interrupt line asserted until INTA. --macro
2095 static inline void unlock_ExtINT_logic(void)
2098 struct IO_APIC_route_entry entry0
, entry1
;
2099 unsigned char save_control
, save_freq_select
;
2101 pin
= find_isa_irq_pin(8, mp_INT
);
2102 apic
= find_isa_irq_apic(8, mp_INT
);
2106 entry0
= ioapic_read_entry(apic
, pin
);
2107 clear_IO_APIC_pin(apic
, pin
);
2109 memset(&entry1
, 0, sizeof(entry1
));
2111 entry1
.dest_mode
= 0; /* physical delivery */
2112 entry1
.mask
= 0; /* unmask IRQ now */
2113 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2114 entry1
.delivery_mode
= dest_ExtINT
;
2115 entry1
.polarity
= entry0
.polarity
;
2119 ioapic_write_entry(apic
, pin
, entry1
);
2121 save_control
= CMOS_READ(RTC_CONTROL
);
2122 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2123 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2125 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2130 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2134 CMOS_WRITE(save_control
, RTC_CONTROL
);
2135 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2136 clear_IO_APIC_pin(apic
, pin
);
2138 ioapic_write_entry(apic
, pin
, entry0
);
2141 int timer_uses_ioapic_pin_0
;
2144 * This code may look a bit paranoid, but it's supposed to cooperate with
2145 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2146 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2147 * fanatically on his truly buggy board.
2149 static inline void check_timer(void)
2151 int apic1
, pin1
, apic2
, pin2
;
2155 * get/set the timer IRQ vector:
2157 disable_8259A_irq(0);
2158 vector
= assign_irq_vector(0);
2159 set_intr_gate(vector
, interrupt
[0]);
2162 * Subtle, code in do_timer_interrupt() expects an AEOI
2163 * mode for the 8259A whenever interrupts are routed
2164 * through I/O APICs. Also IRQ0 has to be enabled in
2165 * the 8259A which implies the virtual wire has to be
2166 * disabled in the local APIC.
2168 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2171 if (timer_over_8254
> 0)
2172 enable_8259A_irq(0);
2174 pin1
= find_isa_irq_pin(0, mp_INT
);
2175 apic1
= find_isa_irq_apic(0, mp_INT
);
2176 pin2
= ioapic_i8259
.pin
;
2177 apic2
= ioapic_i8259
.apic
;
2180 timer_uses_ioapic_pin_0
= 1;
2182 printk(KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2183 vector
, apic1
, pin1
, apic2
, pin2
);
2187 * Ok, does IRQ0 through the IOAPIC work?
2189 unmask_IO_APIC_irq(0);
2190 if (timer_irq_works()) {
2191 if (nmi_watchdog
== NMI_IO_APIC
) {
2192 disable_8259A_irq(0);
2194 enable_8259A_irq(0);
2196 if (disable_timer_pin_1
> 0)
2197 clear_IO_APIC_pin(0, pin1
);
2200 clear_IO_APIC_pin(apic1
, pin1
);
2201 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to "
2205 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
2207 printk("\n..... (found pin %d) ...", pin2
);
2209 * legacy devices should be connected to IO APIC #0
2211 setup_ExtINT_IRQ0_pin(apic2
, pin2
, vector
);
2212 if (timer_irq_works()) {
2215 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2217 add_pin_to_irq(0, apic2
, pin2
);
2218 if (nmi_watchdog
== NMI_IO_APIC
) {
2224 * Cleanup, just in case ...
2226 clear_IO_APIC_pin(apic2
, pin2
);
2228 printk(" failed.\n");
2230 if (nmi_watchdog
== NMI_IO_APIC
) {
2231 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2235 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
2237 disable_8259A_irq(0);
2238 set_irq_chip_and_handler(0, &lapic_chip
, handle_fasteoi_irq
);
2239 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2240 enable_8259A_irq(0);
2242 if (timer_irq_works()) {
2243 printk(" works.\n");
2246 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2247 printk(" failed.\n");
2249 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
2254 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
2256 unlock_ExtINT_logic();
2258 if (timer_irq_works()) {
2259 printk(" works.\n");
2262 printk(" failed :(.\n");
2263 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2264 "report. Then try booting with the 'noapic' option");
2269 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2270 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2271 * Linux doesn't really care, as it's not actually used
2272 * for any interrupt handling anyway.
2274 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2276 void __init
setup_IO_APIC(void)
2281 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
2283 io_apic_irqs
= ~PIC_IRQS
;
2285 printk("ENABLING IO-APIC IRQs\n");
2288 * Set up IO-APIC IRQ routing.
2291 setup_ioapic_ids_from_mpc();
2293 setup_IO_APIC_irqs();
2294 init_IO_APIC_traps();
2300 static int __init
setup_disable_8254_timer(char *s
)
2302 timer_over_8254
= -1;
2305 static int __init
setup_enable_8254_timer(char *s
)
2307 timer_over_8254
= 2;
2311 __setup("disable_8254_timer", setup_disable_8254_timer
);
2312 __setup("enable_8254_timer", setup_enable_8254_timer
);
2315 * Called after all the initialization is done. If we didnt find any
2316 * APIC bugs then we can allow the modify fast path
2319 static int __init
io_apic_bug_finalize(void)
2321 if(sis_apic_bug
== -1)
2326 late_initcall(io_apic_bug_finalize
);
2328 struct sysfs_ioapic_data
{
2329 struct sys_device dev
;
2330 struct IO_APIC_route_entry entry
[0];
2332 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2334 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2336 struct IO_APIC_route_entry
*entry
;
2337 struct sysfs_ioapic_data
*data
;
2340 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2341 entry
= data
->entry
;
2342 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2343 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2348 static int ioapic_resume(struct sys_device
*dev
)
2350 struct IO_APIC_route_entry
*entry
;
2351 struct sysfs_ioapic_data
*data
;
2352 unsigned long flags
;
2353 union IO_APIC_reg_00 reg_00
;
2356 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2357 entry
= data
->entry
;
2359 spin_lock_irqsave(&ioapic_lock
, flags
);
2360 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2361 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
2362 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
2363 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2365 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2366 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2367 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2372 static struct sysdev_class ioapic_sysdev_class
= {
2373 set_kset_name("ioapic"),
2374 .suspend
= ioapic_suspend
,
2375 .resume
= ioapic_resume
,
2378 static int __init
ioapic_init_sysfs(void)
2380 struct sys_device
* dev
;
2381 int i
, size
, error
= 0;
2383 error
= sysdev_class_register(&ioapic_sysdev_class
);
2387 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2388 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2389 * sizeof(struct IO_APIC_route_entry
);
2390 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
2391 if (!mp_ioapic_data
[i
]) {
2392 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2395 memset(mp_ioapic_data
[i
], 0, size
);
2396 dev
= &mp_ioapic_data
[i
]->dev
;
2398 dev
->cls
= &ioapic_sysdev_class
;
2399 error
= sysdev_register(dev
);
2401 kfree(mp_ioapic_data
[i
]);
2402 mp_ioapic_data
[i
] = NULL
;
2403 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2411 device_initcall(ioapic_init_sysfs
);
2414 * Dynamic irq allocate and deallocation
2416 int create_irq(void)
2418 /* Allocate an unused irq */
2419 int irq
, new, vector
;
2420 unsigned long flags
;
2423 spin_lock_irqsave(&vector_lock
, flags
);
2424 for (new = (NR_IRQS
- 1); new >= 0; new--) {
2425 if (platform_legacy_irq(new))
2427 if (irq_vector
[new] != 0)
2429 vector
= __assign_irq_vector(new);
2430 if (likely(vector
> 0))
2434 spin_unlock_irqrestore(&vector_lock
, flags
);
2437 set_intr_gate(vector
, interrupt
[irq
]);
2438 dynamic_irq_init(irq
);
2443 void destroy_irq(unsigned int irq
)
2445 unsigned long flags
;
2447 dynamic_irq_cleanup(irq
);
2449 spin_lock_irqsave(&vector_lock
, flags
);
2450 irq_vector
[irq
] = 0;
2451 spin_unlock_irqrestore(&vector_lock
, flags
);
2455 * MSI mesage composition
2457 #ifdef CONFIG_PCI_MSI
2458 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2463 vector
= assign_irq_vector(irq
);
2465 dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2467 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2470 ((INT_DEST_MODE
== 0) ?
2471 MSI_ADDR_DEST_MODE_PHYSICAL
:
2472 MSI_ADDR_DEST_MODE_LOGICAL
) |
2473 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2474 MSI_ADDR_REDIRECTION_CPU
:
2475 MSI_ADDR_REDIRECTION_LOWPRI
) |
2476 MSI_ADDR_DEST_ID(dest
);
2479 MSI_DATA_TRIGGER_EDGE
|
2480 MSI_DATA_LEVEL_ASSERT
|
2481 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2482 MSI_DATA_DELIVERY_FIXED
:
2483 MSI_DATA_DELIVERY_LOWPRI
) |
2484 MSI_DATA_VECTOR(vector
);
2490 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2497 cpus_and(tmp
, mask
, cpu_online_map
);
2498 if (cpus_empty(tmp
))
2501 vector
= assign_irq_vector(irq
);
2505 dest
= cpu_mask_to_apicid(mask
);
2507 read_msi_msg(irq
, &msg
);
2509 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2510 msg
.data
|= MSI_DATA_VECTOR(vector
);
2511 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2512 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2514 write_msi_msg(irq
, &msg
);
2515 set_native_irq_info(irq
, mask
);
2517 #endif /* CONFIG_SMP */
2520 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2521 * which implement the MSI or MSI-X Capability Structure.
2523 static struct irq_chip msi_chip
= {
2525 .unmask
= unmask_msi_irq
,
2526 .mask
= mask_msi_irq
,
2527 .ack
= ack_ioapic_irq
,
2529 .set_affinity
= set_msi_irq_affinity
,
2531 .retrigger
= ioapic_retrigger_irq
,
2534 int arch_setup_msi_irq(unsigned int irq
, struct pci_dev
*dev
)
2538 ret
= msi_compose_msg(dev
, irq
, &msg
);
2542 write_msi_msg(irq
, &msg
);
2544 set_irq_chip_and_handler(irq
, &msi_chip
, handle_edge_irq
);
2549 void arch_teardown_msi_irq(unsigned int irq
)
2554 #endif /* CONFIG_PCI_MSI */
2557 * Hypertransport interrupt support
2559 #ifdef CONFIG_HT_IRQ
2563 static void target_ht_irq(unsigned int irq
, unsigned int dest
)
2566 low
= read_ht_irq_low(irq
);
2567 high
= read_ht_irq_high(irq
);
2569 low
&= ~(HT_IRQ_LOW_DEST_ID_MASK
);
2570 high
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2572 low
|= HT_IRQ_LOW_DEST_ID(dest
);
2573 high
|= HT_IRQ_HIGH_DEST_ID(dest
);
2575 write_ht_irq_low(irq
, low
);
2576 write_ht_irq_high(irq
, high
);
2579 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2584 cpus_and(tmp
, mask
, cpu_online_map
);
2585 if (cpus_empty(tmp
))
2588 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
2590 dest
= cpu_mask_to_apicid(mask
);
2592 target_ht_irq(irq
, dest
);
2593 set_native_irq_info(irq
, mask
);
2597 static struct hw_interrupt_type ht_irq_chip
= {
2599 .mask
= mask_ht_irq
,
2600 .unmask
= unmask_ht_irq
,
2601 .ack
= ack_ioapic_irq
,
2603 .set_affinity
= set_ht_irq_affinity
,
2605 .retrigger
= ioapic_retrigger_irq
,
2608 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2612 vector
= assign_irq_vector(irq
);
2619 cpu_set(vector
>> 8, tmp
);
2620 dest
= cpu_mask_to_apicid(tmp
);
2622 high
= HT_IRQ_HIGH_DEST_ID(dest
);
2624 low
= HT_IRQ_LOW_BASE
|
2625 HT_IRQ_LOW_DEST_ID(dest
) |
2626 HT_IRQ_LOW_VECTOR(vector
) |
2627 ((INT_DEST_MODE
== 0) ?
2628 HT_IRQ_LOW_DM_PHYSICAL
:
2629 HT_IRQ_LOW_DM_LOGICAL
) |
2630 HT_IRQ_LOW_RQEOI_EDGE
|
2631 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2632 HT_IRQ_LOW_MT_FIXED
:
2633 HT_IRQ_LOW_MT_ARBITRATED
) |
2634 HT_IRQ_LOW_IRQ_MASKED
;
2636 write_ht_irq_low(irq
, low
);
2637 write_ht_irq_high(irq
, high
);
2639 set_irq_chip_and_handler(irq
, &ht_irq_chip
, handle_edge_irq
);
2643 #endif /* CONFIG_HT_IRQ */
2645 /* --------------------------------------------------------------------------
2646 ACPI-based IOAPIC Configuration
2647 -------------------------------------------------------------------------- */
2651 int __init
io_apic_get_unique_id (int ioapic
, int apic_id
)
2653 union IO_APIC_reg_00 reg_00
;
2654 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2656 unsigned long flags
;
2660 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2661 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2662 * supports up to 16 on one shared APIC bus.
2664 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2665 * advantage of new APIC bus architecture.
2668 if (physids_empty(apic_id_map
))
2669 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2671 spin_lock_irqsave(&ioapic_lock
, flags
);
2672 reg_00
.raw
= io_apic_read(ioapic
, 0);
2673 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2675 if (apic_id
>= get_physical_broadcast()) {
2676 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2677 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2678 apic_id
= reg_00
.bits
.ID
;
2682 * Every APIC in a system must have a unique ID or we get lots of nice
2683 * 'stuck on smp_invalidate_needed IPI wait' messages.
2685 if (check_apicid_used(apic_id_map
, apic_id
)) {
2687 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2688 if (!check_apicid_used(apic_id_map
, i
))
2692 if (i
== get_physical_broadcast())
2693 panic("Max apic_id exceeded!\n");
2695 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2696 "trying %d\n", ioapic
, apic_id
, i
);
2701 tmp
= apicid_to_cpu_present(apic_id
);
2702 physids_or(apic_id_map
, apic_id_map
, tmp
);
2704 if (reg_00
.bits
.ID
!= apic_id
) {
2705 reg_00
.bits
.ID
= apic_id
;
2707 spin_lock_irqsave(&ioapic_lock
, flags
);
2708 io_apic_write(ioapic
, 0, reg_00
.raw
);
2709 reg_00
.raw
= io_apic_read(ioapic
, 0);
2710 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2713 if (reg_00
.bits
.ID
!= apic_id
) {
2714 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2719 apic_printk(APIC_VERBOSE
, KERN_INFO
2720 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2726 int __init
io_apic_get_version (int ioapic
)
2728 union IO_APIC_reg_01 reg_01
;
2729 unsigned long flags
;
2731 spin_lock_irqsave(&ioapic_lock
, flags
);
2732 reg_01
.raw
= io_apic_read(ioapic
, 1);
2733 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2735 return reg_01
.bits
.version
;
2739 int __init
io_apic_get_redir_entries (int ioapic
)
2741 union IO_APIC_reg_01 reg_01
;
2742 unsigned long flags
;
2744 spin_lock_irqsave(&ioapic_lock
, flags
);
2745 reg_01
.raw
= io_apic_read(ioapic
, 1);
2746 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2748 return reg_01
.bits
.entries
;
2752 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2754 struct IO_APIC_route_entry entry
;
2755 unsigned long flags
;
2757 if (!IO_APIC_IRQ(irq
)) {
2758 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2764 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2765 * Note that we mask (disable) IRQs now -- these get enabled when the
2766 * corresponding device driver registers for this IRQ.
2769 memset(&entry
,0,sizeof(entry
));
2771 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2772 entry
.dest_mode
= INT_DEST_MODE
;
2773 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2774 entry
.trigger
= edge_level
;
2775 entry
.polarity
= active_high_low
;
2779 * IRQs < 16 are already in the irq_2_pin[] map
2782 add_pin_to_irq(irq
, ioapic
, pin
);
2784 entry
.vector
= assign_irq_vector(irq
);
2786 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2787 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2788 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
,
2789 edge_level
, active_high_low
);
2791 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2793 if (!ioapic
&& (irq
< 16))
2794 disable_8259A_irq(irq
);
2796 ioapic_write_entry(ioapic
, pin
, entry
);
2797 spin_lock_irqsave(&ioapic_lock
, flags
);
2798 set_native_irq_info(irq
, TARGET_CPUS
);
2799 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2804 #endif /* CONFIG_ACPI */
2806 static int __init
parse_disable_timer_pin_1(char *arg
)
2808 disable_timer_pin_1
= 1;
2811 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2813 static int __init
parse_enable_timer_pin_1(char *arg
)
2815 disable_timer_pin_1
= -1;
2818 early_param("enable_timer_pin_1", parse_enable_timer_pin_1
);
2820 static int __init
parse_noapic(char *arg
)
2822 /* disable IO-APIC */
2823 disable_ioapic_setup();
2826 early_param("noapic", parse_noapic
);