2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
42 #include <asm/timer.h>
43 #include <asm/i8259.h>
45 #include <asm/msidef.h>
46 #include <asm/hypertransport.h>
48 #include <mach_apic.h>
49 #include <mach_apicdef.h>
53 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
54 atomic_t irq_mis_count
;
56 /* Where if anywhere is the i8259 connect in external int mode */
57 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
59 static DEFINE_SPINLOCK(ioapic_lock
);
60 static DEFINE_SPINLOCK(vector_lock
);
62 int timer_over_8254 __initdata
= 1;
65 * Is the SiS APIC rmw bug present ?
66 * -1 = don't know, 0 = no, 1 = yes
68 int sis_apic_bug
= -1;
71 * # of IRQ routing registers
73 int nr_ioapic_registers
[MAX_IO_APICS
];
75 static int disable_timer_pin_1 __initdata
;
78 * Rough estimation of how many shared IRQs there are, can
81 #define MAX_PLUS_SHARED_IRQS NR_IRQS
82 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
85 * This is performance-critical, we want to do it O(1)
87 * the indexing order of this array favors 1:1 mappings
88 * between pins and IRQs.
91 static struct irq_pin_list
{
93 } irq_2_pin
[PIN_MAP_SIZE
];
97 unsigned int unused
[3];
101 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
103 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
104 + (mp_ioapics
[idx
].mpc_apicaddr
& ~PAGE_MASK
);
107 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
109 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
110 writel(reg
, &io_apic
->index
);
111 return readl(&io_apic
->data
);
114 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
116 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
117 writel(reg
, &io_apic
->index
);
118 writel(value
, &io_apic
->data
);
122 * Re-write a value: to be used for read-modify-write
123 * cycles where the read already set up the index register.
125 * Older SiS APIC requires we rewrite the index register
127 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
129 volatile struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
131 writel(reg
, &io_apic
->index
);
132 writel(value
, &io_apic
->data
);
136 struct { u32 w1
, w2
; };
137 struct IO_APIC_route_entry entry
;
140 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
142 union entry_union eu
;
144 spin_lock_irqsave(&ioapic_lock
, flags
);
145 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
146 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
147 spin_unlock_irqrestore(&ioapic_lock
, flags
);
152 * When we write a new IO APIC routing entry, we need to write the high
153 * word first! If the mask bit in the low word is clear, we will enable
154 * the interrupt, and we need to make sure the entry is fully populated
155 * before that happens.
158 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
160 union entry_union eu
;
162 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
163 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
166 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
169 spin_lock_irqsave(&ioapic_lock
, flags
);
170 __ioapic_write_entry(apic
, pin
, e
);
171 spin_unlock_irqrestore(&ioapic_lock
, flags
);
175 * When we mask an IO APIC routing entry, we need to write the low
176 * word first, in order to set the mask bit before we change the
179 static void ioapic_mask_entry(int apic
, int pin
)
182 union entry_union eu
= { .entry
.mask
= 1 };
184 spin_lock_irqsave(&ioapic_lock
, flags
);
185 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
186 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
187 spin_unlock_irqrestore(&ioapic_lock
, flags
);
191 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
192 * shared ISA-space IRQs, so we have to support them. We are super
193 * fast in the common case, and fast for shared ISA-space IRQs.
195 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
197 static int first_free_entry
= NR_IRQS
;
198 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
201 entry
= irq_2_pin
+ entry
->next
;
203 if (entry
->pin
!= -1) {
204 entry
->next
= first_free_entry
;
205 entry
= irq_2_pin
+ entry
->next
;
206 if (++first_free_entry
>= PIN_MAP_SIZE
)
207 panic("io_apic.c: whoops");
214 * Reroute an IRQ to a different pin.
216 static void __init
replace_pin_at_irq(unsigned int irq
,
217 int oldapic
, int oldpin
,
218 int newapic
, int newpin
)
220 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
223 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
224 entry
->apic
= newapic
;
229 entry
= irq_2_pin
+ entry
->next
;
233 static void __modify_IO_APIC_irq (unsigned int irq
, unsigned long enable
, unsigned long disable
)
235 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
236 unsigned int pin
, reg
;
242 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
245 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
248 entry
= irq_2_pin
+ entry
->next
;
253 static void __mask_IO_APIC_irq (unsigned int irq
)
255 __modify_IO_APIC_irq(irq
, 0x00010000, 0);
259 static void __unmask_IO_APIC_irq (unsigned int irq
)
261 __modify_IO_APIC_irq(irq
, 0, 0x00010000);
264 /* mask = 1, trigger = 0 */
265 static void __mask_and_edge_IO_APIC_irq (unsigned int irq
)
267 __modify_IO_APIC_irq(irq
, 0x00010000, 0x00008000);
270 /* mask = 0, trigger = 1 */
271 static void __unmask_and_level_IO_APIC_irq (unsigned int irq
)
273 __modify_IO_APIC_irq(irq
, 0x00008000, 0x00010000);
276 static void mask_IO_APIC_irq (unsigned int irq
)
280 spin_lock_irqsave(&ioapic_lock
, flags
);
281 __mask_IO_APIC_irq(irq
);
282 spin_unlock_irqrestore(&ioapic_lock
, flags
);
285 static void unmask_IO_APIC_irq (unsigned int irq
)
289 spin_lock_irqsave(&ioapic_lock
, flags
);
290 __unmask_IO_APIC_irq(irq
);
291 spin_unlock_irqrestore(&ioapic_lock
, flags
);
294 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
296 struct IO_APIC_route_entry entry
;
298 /* Check delivery_mode to be sure we're not clearing an SMI pin */
299 entry
= ioapic_read_entry(apic
, pin
);
300 if (entry
.delivery_mode
== dest_SMI
)
304 * Disable it in the IO-APIC irq-routing table:
306 ioapic_mask_entry(apic
, pin
);
309 static void clear_IO_APIC (void)
313 for (apic
= 0; apic
< nr_ioapics
; apic
++)
314 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
315 clear_IO_APIC_pin(apic
, pin
);
319 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
323 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
324 unsigned int apicid_value
;
327 cpus_and(tmp
, cpumask
, cpu_online_map
);
331 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
333 apicid_value
= cpu_mask_to_apicid(cpumask
);
334 /* Prepare to do the io_apic_write */
335 apicid_value
= apicid_value
<< 24;
336 spin_lock_irqsave(&ioapic_lock
, flags
);
341 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
344 entry
= irq_2_pin
+ entry
->next
;
346 irq_desc
[irq
].affinity
= cpumask
;
347 spin_unlock_irqrestore(&ioapic_lock
, flags
);
350 #if defined(CONFIG_IRQBALANCE)
351 # include <asm/processor.h> /* kernel_thread() */
352 # include <linux/kernel_stat.h> /* kstat */
353 # include <linux/slab.h> /* kmalloc() */
354 # include <linux/timer.h> /* time_after() */
356 #ifdef CONFIG_BALANCED_IRQ_DEBUG
357 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
358 # define Dprintk(x...) do { TDprintk(x); } while (0)
360 # define TDprintk(x...)
361 # define Dprintk(x...)
364 #define IRQBALANCE_CHECK_ARCH -999
365 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
366 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
367 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
368 #define BALANCED_IRQ_LESS_DELTA (HZ)
370 static int irqbalance_disabled __read_mostly
= IRQBALANCE_CHECK_ARCH
;
371 static int physical_balance __read_mostly
;
372 static long balanced_irq_interval __read_mostly
= MAX_BALANCED_IRQ_INTERVAL
;
374 static struct irq_cpu_info
{
375 unsigned long * last_irq
;
376 unsigned long * irq_delta
;
378 } irq_cpu_data
[NR_CPUS
];
380 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
381 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
382 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
384 #define IDLE_ENOUGH(cpu,now) \
385 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
387 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
389 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
391 static cpumask_t balance_irq_affinity
[NR_IRQS
] = {
392 [0 ... NR_IRQS
-1] = CPU_MASK_ALL
395 void set_balance_irq_affinity(unsigned int irq
, cpumask_t mask
)
397 balance_irq_affinity
[irq
] = mask
;
400 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
401 unsigned long now
, int direction
)
409 if (unlikely(cpu
== curr_cpu
))
412 if (direction
== 1) {
421 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
,allowed_mask
) ||
422 (search_idle
&& !IDLE_ENOUGH(cpu
,now
)));
427 static inline void balance_irq(int cpu
, int irq
)
429 unsigned long now
= jiffies
;
430 cpumask_t allowed_mask
;
431 unsigned int new_cpu
;
433 if (irqbalance_disabled
)
436 cpus_and(allowed_mask
, cpu_online_map
, balance_irq_affinity
[irq
]);
437 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
438 if (cpu
!= new_cpu
) {
439 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
443 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
446 Dprintk("Rotating IRQs among CPUs.\n");
447 for_each_online_cpu(i
) {
448 for (j
= 0; j
< NR_IRQS
; j
++) {
449 if (!irq_desc
[j
].action
)
451 /* Is it a significant load ? */
452 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
),j
) <
453 useful_load_threshold
)
458 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
459 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
463 static void do_irq_balance(void)
466 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
467 unsigned long move_this_load
= 0;
468 int max_loaded
= 0, min_loaded
= 0;
470 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
472 int tmp_loaded
, first_attempt
= 1;
473 unsigned long tmp_cpu_irq
;
474 unsigned long imbalance
= 0;
475 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
477 for_each_possible_cpu(i
) {
482 package_index
= CPU_TO_PACKAGEINDEX(i
);
483 for (j
= 0; j
< NR_IRQS
; j
++) {
484 unsigned long value_now
, delta
;
485 /* Is this an active IRQ or balancing disabled ? */
486 if (!irq_desc
[j
].action
|| irq_balancing_disabled(j
))
488 if ( package_index
== i
)
489 IRQ_DELTA(package_index
,j
) = 0;
490 /* Determine the total count per processor per IRQ */
491 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
493 /* Determine the activity per processor per IRQ */
494 delta
= value_now
- LAST_CPU_IRQ(i
,j
);
496 /* Update last_cpu_irq[][] for the next time */
497 LAST_CPU_IRQ(i
,j
) = value_now
;
499 /* Ignore IRQs whose rate is less than the clock */
500 if (delta
< useful_load_threshold
)
502 /* update the load for the processor or package total */
503 IRQ_DELTA(package_index
,j
) += delta
;
505 /* Keep track of the higher numbered sibling as well */
506 if (i
!= package_index
)
509 * We have sibling A and sibling B in the package
511 * cpu_irq[A] = load for cpu A + load for cpu B
512 * cpu_irq[B] = load for cpu B
514 CPU_IRQ(package_index
) += delta
;
517 /* Find the least loaded processor package */
518 for_each_online_cpu(i
) {
519 if (i
!= CPU_TO_PACKAGEINDEX(i
))
521 if (min_cpu_irq
> CPU_IRQ(i
)) {
522 min_cpu_irq
= CPU_IRQ(i
);
526 max_cpu_irq
= ULONG_MAX
;
529 /* Look for heaviest loaded processor.
530 * We may come back to get the next heaviest loaded processor.
531 * Skip processors with trivial loads.
535 for_each_online_cpu(i
) {
536 if (i
!= CPU_TO_PACKAGEINDEX(i
))
538 if (max_cpu_irq
<= CPU_IRQ(i
))
540 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
541 tmp_cpu_irq
= CPU_IRQ(i
);
546 if (tmp_loaded
== -1) {
547 /* In the case of small number of heavy interrupt sources,
548 * loading some of the cpus too much. We use Ingo's original
549 * approach to rotate them around.
551 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
552 rotate_irqs_among_cpus(useful_load_threshold
);
555 goto not_worth_the_effort
;
558 first_attempt
= 0; /* heaviest search */
559 max_cpu_irq
= tmp_cpu_irq
; /* load */
560 max_loaded
= tmp_loaded
; /* processor */
561 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
563 Dprintk("max_loaded cpu = %d\n", max_loaded
);
564 Dprintk("min_loaded cpu = %d\n", min_loaded
);
565 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq
);
566 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq
);
567 Dprintk("load imbalance = %lu\n", imbalance
);
569 /* if imbalance is less than approx 10% of max load, then
570 * observe diminishing returns action. - quit
572 if (imbalance
< (max_cpu_irq
>> 3)) {
573 Dprintk("Imbalance too trivial\n");
574 goto not_worth_the_effort
;
578 /* if we select an IRQ to move that can't go where we want, then
579 * see if there is another one to try.
583 for (j
= 0; j
< NR_IRQS
; j
++) {
584 /* Is this an active IRQ? */
585 if (!irq_desc
[j
].action
)
587 if (imbalance
<= IRQ_DELTA(max_loaded
,j
))
589 /* Try to find the IRQ that is closest to the imbalance
590 * without going over.
592 if (move_this_load
< IRQ_DELTA(max_loaded
,j
)) {
593 move_this_load
= IRQ_DELTA(max_loaded
,j
);
597 if (selected_irq
== -1) {
601 imbalance
= move_this_load
;
603 /* For physical_balance case, we accumlated both load
604 * values in the one of the siblings cpu_irq[],
605 * to use the same code for physical and logical processors
606 * as much as possible.
608 * NOTE: the cpu_irq[] array holds the sum of the load for
609 * sibling A and sibling B in the slot for the lowest numbered
610 * sibling (A), _AND_ the load for sibling B in the slot for
611 * the higher numbered sibling.
613 * We seek the least loaded sibling by making the comparison
616 load
= CPU_IRQ(min_loaded
) >> 1;
617 for_each_cpu_mask(j
, cpu_sibling_map
[min_loaded
]) {
618 if (load
> CPU_IRQ(j
)) {
619 /* This won't change cpu_sibling_map[min_loaded] */
625 cpus_and(allowed_mask
,
627 balance_irq_affinity
[selected_irq
]);
628 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
629 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
631 if (!cpus_empty(tmp
)) {
633 Dprintk("irq = %d moved to cpu = %d\n",
634 selected_irq
, min_loaded
);
635 /* mark for change destination */
636 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
638 /* Since we made a change, come back sooner to
639 * check for more variation.
641 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
642 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
647 not_worth_the_effort
:
649 * if we did not find an IRQ to move, then adjust the time interval
652 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
653 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
654 Dprintk("IRQ worth rotating not found\n");
658 static int balanced_irq(void *unused
)
661 unsigned long prev_balance_time
= jiffies
;
662 long time_remaining
= balanced_irq_interval
;
666 /* push everything to CPU 0 to give us a starting point. */
667 for (i
= 0 ; i
< NR_IRQS
; i
++) {
668 irq_desc
[i
].pending_mask
= cpumask_of_cpu(0);
669 set_pending_irq(i
, cpumask_of_cpu(0));
673 time_remaining
= schedule_timeout_interruptible(time_remaining
);
675 if (time_after(jiffies
,
676 prev_balance_time
+balanced_irq_interval
)) {
679 prev_balance_time
= jiffies
;
680 time_remaining
= balanced_irq_interval
;
687 static int __init
balanced_irq_init(void)
690 struct cpuinfo_x86
*c
;
693 cpus_shift_right(tmp
, cpu_online_map
, 2);
695 /* When not overwritten by the command line ask subarchitecture. */
696 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
697 irqbalance_disabled
= NO_BALANCE_IRQ
;
698 if (irqbalance_disabled
)
701 /* disable irqbalance completely if there is only one processor online */
702 if (num_online_cpus() < 2) {
703 irqbalance_disabled
= 1;
707 * Enable physical balance only if more than 1 physical processor
710 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
711 physical_balance
= 1;
713 for_each_online_cpu(i
) {
714 irq_cpu_data
[i
].irq_delta
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
715 irq_cpu_data
[i
].last_irq
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
716 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
717 printk(KERN_ERR
"balanced_irq_init: out of memory");
720 memset(irq_cpu_data
[i
].irq_delta
,0,sizeof(unsigned long) * NR_IRQS
);
721 memset(irq_cpu_data
[i
].last_irq
,0,sizeof(unsigned long) * NR_IRQS
);
724 printk(KERN_INFO
"Starting balanced_irq\n");
725 if (kernel_thread(balanced_irq
, NULL
, CLONE_KERNEL
) >= 0)
728 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
730 for_each_possible_cpu(i
) {
731 kfree(irq_cpu_data
[i
].irq_delta
);
732 irq_cpu_data
[i
].irq_delta
= NULL
;
733 kfree(irq_cpu_data
[i
].last_irq
);
734 irq_cpu_data
[i
].last_irq
= NULL
;
739 int __init
irqbalance_disable(char *str
)
741 irqbalance_disabled
= 1;
745 __setup("noirqbalance", irqbalance_disable
);
747 late_initcall(balanced_irq_init
);
748 #endif /* CONFIG_IRQBALANCE */
749 #endif /* CONFIG_SMP */
752 void fastcall
send_IPI_self(int vector
)
759 apic_wait_icr_idle();
760 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
762 * Send the IPI. The write to APIC_ICR fires this off.
764 apic_write_around(APIC_ICR
, cfg
);
766 #endif /* !CONFIG_SMP */
770 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
771 * specific CPU-side IRQs.
775 static int pirq_entries
[MAX_PIRQS
];
776 static int pirqs_enabled
;
777 int skip_ioapic_setup
;
779 static int __init
ioapic_setup(char *str
)
781 skip_ioapic_setup
= 1;
785 __setup("noapic", ioapic_setup
);
787 static int __init
ioapic_pirq_setup(char *str
)
790 int ints
[MAX_PIRQS
+1];
792 get_options(str
, ARRAY_SIZE(ints
), ints
);
794 for (i
= 0; i
< MAX_PIRQS
; i
++)
795 pirq_entries
[i
] = -1;
798 apic_printk(APIC_VERBOSE
, KERN_INFO
799 "PIRQ redirection, working around broken MP-BIOS.\n");
801 if (ints
[0] < MAX_PIRQS
)
804 for (i
= 0; i
< max
; i
++) {
805 apic_printk(APIC_VERBOSE
, KERN_DEBUG
806 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
808 * PIRQs are mapped upside down, usually.
810 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
815 __setup("pirq=", ioapic_pirq_setup
);
818 * Find the IRQ entry number of a certain pin.
820 static int find_irq_entry(int apic
, int pin
, int type
)
824 for (i
= 0; i
< mp_irq_entries
; i
++)
825 if (mp_irqs
[i
].mpc_irqtype
== type
&&
826 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
827 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
828 mp_irqs
[i
].mpc_dstirq
== pin
)
835 * Find the pin to which IRQ[irq] (ISA) is connected
837 static int __init
find_isa_irq_pin(int irq
, int type
)
841 for (i
= 0; i
< mp_irq_entries
; i
++) {
842 int lbus
= mp_irqs
[i
].mpc_srcbus
;
844 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
845 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
846 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
848 (mp_irqs
[i
].mpc_irqtype
== type
) &&
849 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
851 return mp_irqs
[i
].mpc_dstirq
;
856 static int __init
find_isa_irq_apic(int irq
, int type
)
860 for (i
= 0; i
< mp_irq_entries
; i
++) {
861 int lbus
= mp_irqs
[i
].mpc_srcbus
;
863 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
864 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
865 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
867 (mp_irqs
[i
].mpc_irqtype
== type
) &&
868 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
871 if (i
< mp_irq_entries
) {
873 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
874 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
883 * Find a specific PCI IRQ entry.
884 * Not an __init, possibly needed by modules
886 static int pin_2_irq(int idx
, int apic
, int pin
);
888 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
890 int apic
, i
, best_guess
= -1;
892 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
893 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
894 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
895 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
898 for (i
= 0; i
< mp_irq_entries
; i
++) {
899 int lbus
= mp_irqs
[i
].mpc_srcbus
;
901 for (apic
= 0; apic
< nr_ioapics
; apic
++)
902 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
903 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
906 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
907 !mp_irqs
[i
].mpc_irqtype
&&
909 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
910 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
912 if (!(apic
|| IO_APIC_IRQ(irq
)))
915 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
918 * Use the first all-but-pin matching entry as a
919 * best-guess fuzzy result for broken mptables.
927 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
930 * This function currently is only a helper for the i386 smp boot process where
931 * we need to reprogram the ioredtbls to cater for the cpus which have come online
932 * so mask in all cases should simply be TARGET_CPUS
935 void __init
setup_ioapic_dest(void)
937 int pin
, ioapic
, irq
, irq_entry
;
939 if (skip_ioapic_setup
== 1)
942 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
943 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
944 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
947 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
948 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
956 * EISA Edge/Level control register, ELCR
958 static int EISA_ELCR(unsigned int irq
)
961 unsigned int port
= 0x4d0 + (irq
>> 3);
962 return (inb(port
) >> (irq
& 7)) & 1;
964 apic_printk(APIC_VERBOSE
, KERN_INFO
965 "Broken MPtable reports ISA irq %d\n", irq
);
969 /* EISA interrupts are always polarity zero and can be edge or level
970 * trigger depending on the ELCR value. If an interrupt is listed as
971 * EISA conforming in the MP table, that means its trigger type must
972 * be read in from the ELCR */
974 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
975 #define default_EISA_polarity(idx) (0)
977 /* ISA interrupts are always polarity zero edge triggered,
978 * when listed as conforming in the MP table. */
980 #define default_ISA_trigger(idx) (0)
981 #define default_ISA_polarity(idx) (0)
983 /* PCI interrupts are always polarity one level triggered,
984 * when listed as conforming in the MP table. */
986 #define default_PCI_trigger(idx) (1)
987 #define default_PCI_polarity(idx) (1)
989 /* MCA interrupts are always polarity zero level triggered,
990 * when listed as conforming in the MP table. */
992 #define default_MCA_trigger(idx) (1)
993 #define default_MCA_polarity(idx) (0)
995 static int __init
MPBIOS_polarity(int idx
)
997 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1001 * Determine IRQ line polarity (high active or low active):
1003 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
1005 case 0: /* conforms, ie. bus-type dependent polarity */
1007 switch (mp_bus_id_to_type
[bus
])
1009 case MP_BUS_ISA
: /* ISA pin */
1011 polarity
= default_ISA_polarity(idx
);
1014 case MP_BUS_EISA
: /* EISA pin */
1016 polarity
= default_EISA_polarity(idx
);
1019 case MP_BUS_PCI
: /* PCI pin */
1021 polarity
= default_PCI_polarity(idx
);
1024 case MP_BUS_MCA
: /* MCA pin */
1026 polarity
= default_MCA_polarity(idx
);
1031 printk(KERN_WARNING
"broken BIOS!!\n");
1038 case 1: /* high active */
1043 case 2: /* reserved */
1045 printk(KERN_WARNING
"broken BIOS!!\n");
1049 case 3: /* low active */
1054 default: /* invalid */
1056 printk(KERN_WARNING
"broken BIOS!!\n");
1064 static int MPBIOS_trigger(int idx
)
1066 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1070 * Determine IRQ trigger mode (edge or level sensitive):
1072 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
1074 case 0: /* conforms, ie. bus-type dependent */
1076 switch (mp_bus_id_to_type
[bus
])
1078 case MP_BUS_ISA
: /* ISA pin */
1080 trigger
= default_ISA_trigger(idx
);
1083 case MP_BUS_EISA
: /* EISA pin */
1085 trigger
= default_EISA_trigger(idx
);
1088 case MP_BUS_PCI
: /* PCI pin */
1090 trigger
= default_PCI_trigger(idx
);
1093 case MP_BUS_MCA
: /* MCA pin */
1095 trigger
= default_MCA_trigger(idx
);
1100 printk(KERN_WARNING
"broken BIOS!!\n");
1112 case 2: /* reserved */
1114 printk(KERN_WARNING
"broken BIOS!!\n");
1123 default: /* invalid */
1125 printk(KERN_WARNING
"broken BIOS!!\n");
1133 static inline int irq_polarity(int idx
)
1135 return MPBIOS_polarity(idx
);
1138 static inline int irq_trigger(int idx
)
1140 return MPBIOS_trigger(idx
);
1143 static int pin_2_irq(int idx
, int apic
, int pin
)
1146 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1149 * Debugging check, we are in big trouble if this message pops up!
1151 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
1152 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1154 switch (mp_bus_id_to_type
[bus
])
1156 case MP_BUS_ISA
: /* ISA pin */
1160 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
1163 case MP_BUS_PCI
: /* PCI pin */
1166 * PCI IRQs are mapped in order
1170 irq
+= nr_ioapic_registers
[i
++];
1174 * For MPS mode, so far only needed by ES7000 platform
1176 if (ioapic_renumber_irq
)
1177 irq
= ioapic_renumber_irq(apic
, irq
);
1183 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
1190 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1192 if ((pin
>= 16) && (pin
<= 23)) {
1193 if (pirq_entries
[pin
-16] != -1) {
1194 if (!pirq_entries
[pin
-16]) {
1195 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1196 "disabling PIRQ%d\n", pin
-16);
1198 irq
= pirq_entries
[pin
-16];
1199 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1200 "using PIRQ%d -> IRQ %d\n",
1208 static inline int IO_APIC_irq_trigger(int irq
)
1212 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1213 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1214 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1215 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
1216 return irq_trigger(idx
);
1220 * nonexistent IRQs are edge default
1225 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1226 static u8 irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_DEVICE_VECTOR
, 0 };
1228 static int __assign_irq_vector(int irq
)
1230 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1231 int vector
, offset
, i
;
1233 BUG_ON((unsigned)irq
>= NR_IRQ_VECTORS
);
1235 if (irq_vector
[irq
] > 0)
1236 return irq_vector
[irq
];
1238 vector
= current_vector
;
1239 offset
= current_offset
;
1242 if (vector
>= FIRST_SYSTEM_VECTOR
) {
1243 offset
= (offset
+ 1) % 8;
1244 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1246 if (vector
== current_vector
)
1248 if (vector
== SYSCALL_VECTOR
)
1250 for (i
= 0; i
< NR_IRQ_VECTORS
; i
++)
1251 if (irq_vector
[i
] == vector
)
1254 current_vector
= vector
;
1255 current_offset
= offset
;
1256 irq_vector
[irq
] = vector
;
1261 static int assign_irq_vector(int irq
)
1263 unsigned long flags
;
1266 spin_lock_irqsave(&vector_lock
, flags
);
1267 vector
= __assign_irq_vector(irq
);
1268 spin_unlock_irqrestore(&vector_lock
, flags
);
1272 static struct irq_chip ioapic_chip
;
1274 #define IOAPIC_AUTO -1
1275 #define IOAPIC_EDGE 0
1276 #define IOAPIC_LEVEL 1
1278 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1280 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1281 trigger
== IOAPIC_LEVEL
)
1282 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1283 handle_fasteoi_irq
, "fasteoi");
1285 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1286 handle_edge_irq
, "edge");
1287 set_intr_gate(vector
, interrupt
[irq
]);
1290 static void __init
setup_IO_APIC_irqs(void)
1292 struct IO_APIC_route_entry entry
;
1293 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1294 unsigned long flags
;
1296 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1298 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1299 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1302 * add it to the IO-APIC irq-routing table:
1304 memset(&entry
,0,sizeof(entry
));
1306 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1307 entry
.dest_mode
= INT_DEST_MODE
;
1308 entry
.mask
= 0; /* enable IRQ */
1309 entry
.dest
.logical
.logical_dest
=
1310 cpu_mask_to_apicid(TARGET_CPUS
);
1312 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1315 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1316 " IO-APIC (apicid-pin) %d-%d",
1317 mp_ioapics
[apic
].mpc_apicid
,
1321 apic_printk(APIC_VERBOSE
, ", %d-%d",
1322 mp_ioapics
[apic
].mpc_apicid
, pin
);
1326 entry
.trigger
= irq_trigger(idx
);
1327 entry
.polarity
= irq_polarity(idx
);
1329 if (irq_trigger(idx
)) {
1334 irq
= pin_2_irq(idx
, apic
, pin
);
1336 * skip adding the timer int on secondary nodes, which causes
1337 * a small but painful rift in the time-space continuum
1339 if (multi_timer_check(apic
, irq
))
1342 add_pin_to_irq(irq
, apic
, pin
);
1344 if (!apic
&& !IO_APIC_IRQ(irq
))
1347 if (IO_APIC_IRQ(irq
)) {
1348 vector
= assign_irq_vector(irq
);
1349 entry
.vector
= vector
;
1350 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1352 if (!apic
&& (irq
< 16))
1353 disable_8259A_irq(irq
);
1355 spin_lock_irqsave(&ioapic_lock
, flags
);
1356 __ioapic_write_entry(apic
, pin
, entry
);
1357 irq_desc
[irq
].affinity
= TARGET_CPUS
;
1358 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1363 apic_printk(APIC_VERBOSE
, " not connected.\n");
1367 * Set up the 8259A-master output pin:
1369 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
1371 struct IO_APIC_route_entry entry
;
1373 memset(&entry
,0,sizeof(entry
));
1375 disable_8259A_irq(0);
1378 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1381 * We use logical delivery to get the timer IRQ
1384 entry
.dest_mode
= INT_DEST_MODE
;
1385 entry
.mask
= 0; /* unmask IRQ now */
1386 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1387 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1390 entry
.vector
= vector
;
1393 * The timer IRQ doesn't have to know that behind the
1394 * scene we have a 8259A-master in AEOI mode ...
1396 irq_desc
[0].chip
= &ioapic_chip
;
1397 set_irq_handler(0, handle_edge_irq
);
1400 * Add it to the IO-APIC irq-routing table:
1402 ioapic_write_entry(apic
, pin
, entry
);
1404 enable_8259A_irq(0);
1407 static inline void UNEXPECTED_IO_APIC(void)
1411 void __init
print_IO_APIC(void)
1414 union IO_APIC_reg_00 reg_00
;
1415 union IO_APIC_reg_01 reg_01
;
1416 union IO_APIC_reg_02 reg_02
;
1417 union IO_APIC_reg_03 reg_03
;
1418 unsigned long flags
;
1420 if (apic_verbosity
== APIC_QUIET
)
1423 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1424 for (i
= 0; i
< nr_ioapics
; i
++)
1425 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1426 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
1429 * We are a bit conservative about what we expect. We have to
1430 * know about every hardware change ASAP.
1432 printk(KERN_INFO
"testing the IO APIC.......................\n");
1434 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1436 spin_lock_irqsave(&ioapic_lock
, flags
);
1437 reg_00
.raw
= io_apic_read(apic
, 0);
1438 reg_01
.raw
= io_apic_read(apic
, 1);
1439 if (reg_01
.bits
.version
>= 0x10)
1440 reg_02
.raw
= io_apic_read(apic
, 2);
1441 if (reg_01
.bits
.version
>= 0x20)
1442 reg_03
.raw
= io_apic_read(apic
, 3);
1443 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1445 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
1446 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1447 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1448 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1449 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1450 if (reg_00
.bits
.ID
>= get_physical_broadcast())
1451 UNEXPECTED_IO_APIC();
1452 if (reg_00
.bits
.__reserved_1
|| reg_00
.bits
.__reserved_2
)
1453 UNEXPECTED_IO_APIC();
1455 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1456 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1457 if ( (reg_01
.bits
.entries
!= 0x0f) && /* older (Neptune) boards */
1458 (reg_01
.bits
.entries
!= 0x17) && /* typical ISA+PCI boards */
1459 (reg_01
.bits
.entries
!= 0x1b) && /* Compaq Proliant boards */
1460 (reg_01
.bits
.entries
!= 0x1f) && /* dual Xeon boards */
1461 (reg_01
.bits
.entries
!= 0x22) && /* bigger Xeon boards */
1462 (reg_01
.bits
.entries
!= 0x2E) &&
1463 (reg_01
.bits
.entries
!= 0x3F)
1465 UNEXPECTED_IO_APIC();
1467 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1468 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1469 if ( (reg_01
.bits
.version
!= 0x01) && /* 82489DX IO-APICs */
1470 (reg_01
.bits
.version
!= 0x10) && /* oldest IO-APICs */
1471 (reg_01
.bits
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
1472 (reg_01
.bits
.version
!= 0x13) && /* Xeon IO-APICs */
1473 (reg_01
.bits
.version
!= 0x20) /* Intel P64H (82806 AA) */
1475 UNEXPECTED_IO_APIC();
1476 if (reg_01
.bits
.__reserved_1
|| reg_01
.bits
.__reserved_2
)
1477 UNEXPECTED_IO_APIC();
1480 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1481 * but the value of reg_02 is read as the previous read register
1482 * value, so ignore it if reg_02 == reg_01.
1484 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1485 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1486 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1487 if (reg_02
.bits
.__reserved_1
|| reg_02
.bits
.__reserved_2
)
1488 UNEXPECTED_IO_APIC();
1492 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1493 * or reg_03, but the value of reg_0[23] is read as the previous read
1494 * register value, so ignore it if reg_03 == reg_0[12].
1496 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1497 reg_03
.raw
!= reg_01
.raw
) {
1498 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1499 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1500 if (reg_03
.bits
.__reserved_1
)
1501 UNEXPECTED_IO_APIC();
1504 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1506 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1507 " Stat Dest Deli Vect: \n");
1509 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1510 struct IO_APIC_route_entry entry
;
1512 entry
= ioapic_read_entry(apic
, i
);
1514 printk(KERN_DEBUG
" %02x %03X %02X ",
1516 entry
.dest
.logical
.logical_dest
,
1517 entry
.dest
.physical
.physical_dest
1520 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1525 entry
.delivery_status
,
1527 entry
.delivery_mode
,
1532 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1533 for (i
= 0; i
< NR_IRQS
; i
++) {
1534 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1537 printk(KERN_DEBUG
"IRQ%d ", i
);
1539 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1542 entry
= irq_2_pin
+ entry
->next
;
1547 printk(KERN_INFO
".................................... done.\n");
1554 static void print_APIC_bitfield (int base
)
1559 if (apic_verbosity
== APIC_QUIET
)
1562 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1563 for (i
= 0; i
< 8; i
++) {
1564 v
= apic_read(base
+ i
*0x10);
1565 for (j
= 0; j
< 32; j
++) {
1575 void /*__init*/ print_local_APIC(void * dummy
)
1577 unsigned int v
, ver
, maxlvt
;
1579 if (apic_verbosity
== APIC_QUIET
)
1582 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1583 smp_processor_id(), hard_smp_processor_id());
1584 v
= apic_read(APIC_ID
);
1585 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
1586 v
= apic_read(APIC_LVR
);
1587 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1588 ver
= GET_APIC_VERSION(v
);
1589 maxlvt
= lapic_get_maxlvt();
1591 v
= apic_read(APIC_TASKPRI
);
1592 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1594 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1595 v
= apic_read(APIC_ARBPRI
);
1596 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1597 v
& APIC_ARBPRI_MASK
);
1598 v
= apic_read(APIC_PROCPRI
);
1599 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1602 v
= apic_read(APIC_EOI
);
1603 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1604 v
= apic_read(APIC_RRR
);
1605 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1606 v
= apic_read(APIC_LDR
);
1607 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1608 v
= apic_read(APIC_DFR
);
1609 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1610 v
= apic_read(APIC_SPIV
);
1611 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1613 printk(KERN_DEBUG
"... APIC ISR field:\n");
1614 print_APIC_bitfield(APIC_ISR
);
1615 printk(KERN_DEBUG
"... APIC TMR field:\n");
1616 print_APIC_bitfield(APIC_TMR
);
1617 printk(KERN_DEBUG
"... APIC IRR field:\n");
1618 print_APIC_bitfield(APIC_IRR
);
1620 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1621 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1622 apic_write(APIC_ESR
, 0);
1623 v
= apic_read(APIC_ESR
);
1624 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1627 v
= apic_read(APIC_ICR
);
1628 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1629 v
= apic_read(APIC_ICR2
);
1630 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1632 v
= apic_read(APIC_LVTT
);
1633 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1635 if (maxlvt
> 3) { /* PC is LVT#4. */
1636 v
= apic_read(APIC_LVTPC
);
1637 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1639 v
= apic_read(APIC_LVT0
);
1640 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1641 v
= apic_read(APIC_LVT1
);
1642 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1644 if (maxlvt
> 2) { /* ERR is LVT#3. */
1645 v
= apic_read(APIC_LVTERR
);
1646 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1649 v
= apic_read(APIC_TMICT
);
1650 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1651 v
= apic_read(APIC_TMCCT
);
1652 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1653 v
= apic_read(APIC_TDCR
);
1654 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1658 void print_all_local_APICs (void)
1660 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1663 void /*__init*/ print_PIC(void)
1666 unsigned long flags
;
1668 if (apic_verbosity
== APIC_QUIET
)
1671 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1673 spin_lock_irqsave(&i8259A_lock
, flags
);
1675 v
= inb(0xa1) << 8 | inb(0x21);
1676 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1678 v
= inb(0xa0) << 8 | inb(0x20);
1679 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1683 v
= inb(0xa0) << 8 | inb(0x20);
1687 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1689 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1691 v
= inb(0x4d1) << 8 | inb(0x4d0);
1692 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1697 static void __init
enable_IO_APIC(void)
1699 union IO_APIC_reg_01 reg_01
;
1700 int i8259_apic
, i8259_pin
;
1702 unsigned long flags
;
1704 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1705 irq_2_pin
[i
].pin
= -1;
1706 irq_2_pin
[i
].next
= 0;
1709 for (i
= 0; i
< MAX_PIRQS
; i
++)
1710 pirq_entries
[i
] = -1;
1713 * The number of IO-APIC IRQ registers (== #pins):
1715 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1716 spin_lock_irqsave(&ioapic_lock
, flags
);
1717 reg_01
.raw
= io_apic_read(apic
, 1);
1718 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1719 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1721 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1723 /* See if any of the pins is in ExtINT mode */
1724 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1725 struct IO_APIC_route_entry entry
;
1726 entry
= ioapic_read_entry(apic
, pin
);
1729 /* If the interrupt line is enabled and in ExtInt mode
1730 * I have found the pin where the i8259 is connected.
1732 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1733 ioapic_i8259
.apic
= apic
;
1734 ioapic_i8259
.pin
= pin
;
1740 /* Look to see what if the MP table has reported the ExtINT */
1741 /* If we could not find the appropriate pin by looking at the ioapic
1742 * the i8259 probably is not connected the ioapic but give the
1743 * mptable a chance anyway.
1745 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1746 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1747 /* Trust the MP table if nothing is setup in the hardware */
1748 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1749 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1750 ioapic_i8259
.pin
= i8259_pin
;
1751 ioapic_i8259
.apic
= i8259_apic
;
1753 /* Complain if the MP table and the hardware disagree */
1754 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1755 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1757 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1761 * Do not trust the IO-APIC being empty at bootup
1767 * Not an __init, needed by the reboot code
1769 void disable_IO_APIC(void)
1772 * Clear the IO-APIC before rebooting:
1777 * If the i8259 is routed through an IOAPIC
1778 * Put that IOAPIC in virtual wire mode
1779 * so legacy interrupts can be delivered.
1781 if (ioapic_i8259
.pin
!= -1) {
1782 struct IO_APIC_route_entry entry
;
1784 memset(&entry
, 0, sizeof(entry
));
1785 entry
.mask
= 0; /* Enabled */
1786 entry
.trigger
= 0; /* Edge */
1788 entry
.polarity
= 0; /* High */
1789 entry
.delivery_status
= 0;
1790 entry
.dest_mode
= 0; /* Physical */
1791 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1793 entry
.dest
.physical
.physical_dest
=
1794 GET_APIC_ID(apic_read(APIC_ID
));
1797 * Add it to the IO-APIC irq-routing table:
1799 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1801 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1805 * function to set the IO-APIC physical IDs based on the
1806 * values stored in the MPC table.
1808 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1811 #ifndef CONFIG_X86_NUMAQ
1812 static void __init
setup_ioapic_ids_from_mpc(void)
1814 union IO_APIC_reg_00 reg_00
;
1815 physid_mask_t phys_id_present_map
;
1818 unsigned char old_id
;
1819 unsigned long flags
;
1822 * Don't check I/O APIC IDs for xAPIC systems. They have
1823 * no meaning without the serial APIC bus.
1825 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1826 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1829 * This is broken; anything with a real cpu count has to
1830 * circumvent this idiocy regardless.
1832 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1835 * Set the IOAPIC ID to the value stored in the MPC table.
1837 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1839 /* Read the register 0 value */
1840 spin_lock_irqsave(&ioapic_lock
, flags
);
1841 reg_00
.raw
= io_apic_read(apic
, 0);
1842 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1844 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1846 if (mp_ioapics
[apic
].mpc_apicid
>= get_physical_broadcast()) {
1847 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1848 apic
, mp_ioapics
[apic
].mpc_apicid
);
1849 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1851 mp_ioapics
[apic
].mpc_apicid
= reg_00
.bits
.ID
;
1855 * Sanity check, is the ID really free? Every APIC in a
1856 * system must have a unique ID or we get lots of nice
1857 * 'stuck on smp_invalidate_needed IPI wait' messages.
1859 if (check_apicid_used(phys_id_present_map
,
1860 mp_ioapics
[apic
].mpc_apicid
)) {
1861 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1862 apic
, mp_ioapics
[apic
].mpc_apicid
);
1863 for (i
= 0; i
< get_physical_broadcast(); i
++)
1864 if (!physid_isset(i
, phys_id_present_map
))
1866 if (i
>= get_physical_broadcast())
1867 panic("Max APIC ID exceeded!\n");
1868 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1870 physid_set(i
, phys_id_present_map
);
1871 mp_ioapics
[apic
].mpc_apicid
= i
;
1874 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mpc_apicid
);
1875 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1876 "phys_id_present_map\n",
1877 mp_ioapics
[apic
].mpc_apicid
);
1878 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1883 * We need to adjust the IRQ routing table
1884 * if the ID changed.
1886 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1887 for (i
= 0; i
< mp_irq_entries
; i
++)
1888 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1889 mp_irqs
[i
].mpc_dstapic
1890 = mp_ioapics
[apic
].mpc_apicid
;
1893 * Read the right value from the MPC table and
1894 * write it into the ID register.
1896 apic_printk(APIC_VERBOSE
, KERN_INFO
1897 "...changing IO-APIC physical APIC ID to %d ...",
1898 mp_ioapics
[apic
].mpc_apicid
);
1900 reg_00
.bits
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1901 spin_lock_irqsave(&ioapic_lock
, flags
);
1902 io_apic_write(apic
, 0, reg_00
.raw
);
1903 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1908 spin_lock_irqsave(&ioapic_lock
, flags
);
1909 reg_00
.raw
= io_apic_read(apic
, 0);
1910 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1911 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1912 printk("could not set ID!\n");
1914 apic_printk(APIC_VERBOSE
, " ok.\n");
1918 static void __init
setup_ioapic_ids_from_mpc(void) { }
1921 int no_timer_check __initdata
;
1923 static int __init
notimercheck(char *s
)
1928 __setup("no_timer_check", notimercheck
);
1931 * There is a nasty bug in some older SMP boards, their mptable lies
1932 * about the timer IRQ. We do the following to work around the situation:
1934 * - timer IRQ defaults to IO-APIC IRQ
1935 * - if this function detects that timer IRQs are defunct, then we fall
1936 * back to ISA timer IRQs
1938 int __init
timer_irq_works(void)
1940 unsigned long t1
= jiffies
;
1946 /* Let ten ticks pass... */
1947 mdelay((10 * 1000) / HZ
);
1950 * Expect a few ticks at least, to be sure some possible
1951 * glue logic does not lock up after one or two first
1952 * ticks in a non-ExtINT mode. Also the local APIC
1953 * might have cached one ExtINT interrupt. Finally, at
1954 * least one tick may be lost due to delays.
1956 if (jiffies
- t1
> 4)
1963 * In the SMP+IOAPIC case it might happen that there are an unspecified
1964 * number of pending IRQ events unhandled. These cases are very rare,
1965 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1966 * better to do it this way as thus we do not have to be aware of
1967 * 'pending' interrupts in the IRQ path, except at this point.
1970 * Edge triggered needs to resend any interrupt
1971 * that was delayed but this is now handled in the device
1978 * Starting up a edge-triggered IO-APIC interrupt is
1979 * nasty - we need to make sure that we get the edge.
1980 * If it is already asserted for some reason, we need
1981 * return 1 to indicate that is was pending.
1983 * This is not complete - we should be able to fake
1984 * an edge even if it isn't on the 8259A...
1986 * (We do this for level-triggered IRQs too - it cannot hurt.)
1988 static unsigned int startup_ioapic_irq(unsigned int irq
)
1990 int was_pending
= 0;
1991 unsigned long flags
;
1993 spin_lock_irqsave(&ioapic_lock
, flags
);
1995 disable_8259A_irq(irq
);
1996 if (i8259A_irq_pending(irq
))
1999 __unmask_IO_APIC_irq(irq
);
2000 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2005 static void ack_ioapic_irq(unsigned int irq
)
2007 move_native_irq(irq
);
2011 static void ack_ioapic_quirk_irq(unsigned int irq
)
2016 move_native_irq(irq
);
2018 * It appears there is an erratum which affects at least version 0x11
2019 * of I/O APIC (that's the 82093AA and cores integrated into various
2020 * chipsets). Under certain conditions a level-triggered interrupt is
2021 * erroneously delivered as edge-triggered one but the respective IRR
2022 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2023 * message but it will never arrive and further interrupts are blocked
2024 * from the source. The exact reason is so far unknown, but the
2025 * phenomenon was observed when two consecutive interrupt requests
2026 * from a given source get delivered to the same CPU and the source is
2027 * temporarily disabled in between.
2029 * A workaround is to simulate an EOI message manually. We achieve it
2030 * by setting the trigger mode to edge and then to level when the edge
2031 * trigger mode gets detected in the TMR of a local APIC for a
2032 * level-triggered interrupt. We mask the source for the time of the
2033 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2034 * The idea is from Manfred Spraul. --macro
2036 i
= irq_vector
[irq
];
2038 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2042 if (!(v
& (1 << (i
& 0x1f)))) {
2043 atomic_inc(&irq_mis_count
);
2044 spin_lock(&ioapic_lock
);
2045 __mask_and_edge_IO_APIC_irq(irq
);
2046 __unmask_and_level_IO_APIC_irq(irq
);
2047 spin_unlock(&ioapic_lock
);
2051 static int ioapic_retrigger_irq(unsigned int irq
)
2053 send_IPI_self(irq_vector
[irq
]);
2058 static struct irq_chip ioapic_chip __read_mostly
= {
2060 .startup
= startup_ioapic_irq
,
2061 .mask
= mask_IO_APIC_irq
,
2062 .unmask
= unmask_IO_APIC_irq
,
2063 .ack
= ack_ioapic_irq
,
2064 .eoi
= ack_ioapic_quirk_irq
,
2066 .set_affinity
= set_ioapic_affinity_irq
,
2068 .retrigger
= ioapic_retrigger_irq
,
2072 static inline void init_IO_APIC_traps(void)
2077 * NOTE! The local APIC isn't very good at handling
2078 * multiple interrupts at the same interrupt level.
2079 * As the interrupt level is determined by taking the
2080 * vector number and shifting that right by 4, we
2081 * want to spread these out a bit so that they don't
2082 * all fall in the same interrupt level.
2084 * Also, we've got to be careful not to trash gate
2085 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2087 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
2089 if (IO_APIC_IRQ(tmp
) && !irq_vector
[tmp
]) {
2091 * Hmm.. We don't have an entry for this,
2092 * so default to an old-fashioned 8259
2093 * interrupt if we can..
2096 make_8259A_irq(irq
);
2098 /* Strange. Oh, well.. */
2099 irq_desc
[irq
].chip
= &no_irq_chip
;
2105 * The local APIC irq-chip implementation:
2108 static void ack_apic(unsigned int irq
)
2113 static void mask_lapic_irq (unsigned int irq
)
2117 v
= apic_read(APIC_LVT0
);
2118 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2121 static void unmask_lapic_irq (unsigned int irq
)
2125 v
= apic_read(APIC_LVT0
);
2126 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2129 static struct irq_chip lapic_chip __read_mostly
= {
2130 .name
= "local-APIC-edge",
2131 .mask
= mask_lapic_irq
,
2132 .unmask
= unmask_lapic_irq
,
2136 static void setup_nmi (void)
2139 * Dirty trick to enable the NMI watchdog ...
2140 * We put the 8259A master into AEOI mode and
2141 * unmask on all local APICs LVT0 as NMI.
2143 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2144 * is from Maciej W. Rozycki - so we do not have to EOI from
2145 * the NMI handler or the timer interrupt.
2147 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2149 on_each_cpu(enable_NMI_through_LVT0
, NULL
, 1, 1);
2151 apic_printk(APIC_VERBOSE
, " done.\n");
2155 * This looks a bit hackish but it's about the only one way of sending
2156 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2157 * not support the ExtINT mode, unfortunately. We need to send these
2158 * cycles as some i82489DX-based boards have glue logic that keeps the
2159 * 8259A interrupt line asserted until INTA. --macro
2161 static inline void unlock_ExtINT_logic(void)
2164 struct IO_APIC_route_entry entry0
, entry1
;
2165 unsigned char save_control
, save_freq_select
;
2167 pin
= find_isa_irq_pin(8, mp_INT
);
2172 apic
= find_isa_irq_apic(8, mp_INT
);
2178 entry0
= ioapic_read_entry(apic
, pin
);
2179 clear_IO_APIC_pin(apic
, pin
);
2181 memset(&entry1
, 0, sizeof(entry1
));
2183 entry1
.dest_mode
= 0; /* physical delivery */
2184 entry1
.mask
= 0; /* unmask IRQ now */
2185 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2186 entry1
.delivery_mode
= dest_ExtINT
;
2187 entry1
.polarity
= entry0
.polarity
;
2191 ioapic_write_entry(apic
, pin
, entry1
);
2193 save_control
= CMOS_READ(RTC_CONTROL
);
2194 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2195 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2197 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2202 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2206 CMOS_WRITE(save_control
, RTC_CONTROL
);
2207 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2208 clear_IO_APIC_pin(apic
, pin
);
2210 ioapic_write_entry(apic
, pin
, entry0
);
2213 int timer_uses_ioapic_pin_0
;
2216 * This code may look a bit paranoid, but it's supposed to cooperate with
2217 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2218 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2219 * fanatically on his truly buggy board.
2221 static inline void __init
check_timer(void)
2223 int apic1
, pin1
, apic2
, pin2
;
2227 * get/set the timer IRQ vector:
2229 disable_8259A_irq(0);
2230 vector
= assign_irq_vector(0);
2231 set_intr_gate(vector
, interrupt
[0]);
2234 * Subtle, code in do_timer_interrupt() expects an AEOI
2235 * mode for the 8259A whenever interrupts are routed
2236 * through I/O APICs. Also IRQ0 has to be enabled in
2237 * the 8259A which implies the virtual wire has to be
2238 * disabled in the local APIC.
2240 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2243 if (timer_over_8254
> 0)
2244 enable_8259A_irq(0);
2246 pin1
= find_isa_irq_pin(0, mp_INT
);
2247 apic1
= find_isa_irq_apic(0, mp_INT
);
2248 pin2
= ioapic_i8259
.pin
;
2249 apic2
= ioapic_i8259
.apic
;
2252 timer_uses_ioapic_pin_0
= 1;
2254 printk(KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2255 vector
, apic1
, pin1
, apic2
, pin2
);
2259 * Ok, does IRQ0 through the IOAPIC work?
2261 unmask_IO_APIC_irq(0);
2262 if (timer_irq_works()) {
2263 if (nmi_watchdog
== NMI_IO_APIC
) {
2264 disable_8259A_irq(0);
2266 enable_8259A_irq(0);
2268 if (disable_timer_pin_1
> 0)
2269 clear_IO_APIC_pin(0, pin1
);
2272 clear_IO_APIC_pin(apic1
, pin1
);
2273 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to "
2277 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
2279 printk("\n..... (found pin %d) ...", pin2
);
2281 * legacy devices should be connected to IO APIC #0
2283 setup_ExtINT_IRQ0_pin(apic2
, pin2
, vector
);
2284 if (timer_irq_works()) {
2287 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2289 add_pin_to_irq(0, apic2
, pin2
);
2290 if (nmi_watchdog
== NMI_IO_APIC
) {
2296 * Cleanup, just in case ...
2298 clear_IO_APIC_pin(apic2
, pin2
);
2300 printk(" failed.\n");
2302 if (nmi_watchdog
== NMI_IO_APIC
) {
2303 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2307 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
2309 disable_8259A_irq(0);
2310 set_irq_chip_and_handler_name(0, &lapic_chip
, handle_fasteoi_irq
,
2312 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2313 enable_8259A_irq(0);
2315 if (timer_irq_works()) {
2316 printk(" works.\n");
2319 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2320 printk(" failed.\n");
2322 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
2327 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
2329 unlock_ExtINT_logic();
2331 if (timer_irq_works()) {
2332 printk(" works.\n");
2335 printk(" failed :(.\n");
2336 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2337 "report. Then try booting with the 'noapic' option");
2342 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2343 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2344 * Linux doesn't really care, as it's not actually used
2345 * for any interrupt handling anyway.
2347 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2349 void __init
setup_IO_APIC(void)
2354 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
2356 io_apic_irqs
= ~PIC_IRQS
;
2358 printk("ENABLING IO-APIC IRQs\n");
2361 * Set up IO-APIC IRQ routing.
2364 setup_ioapic_ids_from_mpc();
2366 setup_IO_APIC_irqs();
2367 init_IO_APIC_traps();
2373 static int __init
setup_disable_8254_timer(char *s
)
2375 timer_over_8254
= -1;
2378 static int __init
setup_enable_8254_timer(char *s
)
2380 timer_over_8254
= 2;
2384 __setup("disable_8254_timer", setup_disable_8254_timer
);
2385 __setup("enable_8254_timer", setup_enable_8254_timer
);
2388 * Called after all the initialization is done. If we didnt find any
2389 * APIC bugs then we can allow the modify fast path
2392 static int __init
io_apic_bug_finalize(void)
2394 if(sis_apic_bug
== -1)
2399 late_initcall(io_apic_bug_finalize
);
2401 struct sysfs_ioapic_data
{
2402 struct sys_device dev
;
2403 struct IO_APIC_route_entry entry
[0];
2405 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2407 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2409 struct IO_APIC_route_entry
*entry
;
2410 struct sysfs_ioapic_data
*data
;
2413 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2414 entry
= data
->entry
;
2415 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2416 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2421 static int ioapic_resume(struct sys_device
*dev
)
2423 struct IO_APIC_route_entry
*entry
;
2424 struct sysfs_ioapic_data
*data
;
2425 unsigned long flags
;
2426 union IO_APIC_reg_00 reg_00
;
2429 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2430 entry
= data
->entry
;
2432 spin_lock_irqsave(&ioapic_lock
, flags
);
2433 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2434 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
2435 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
2436 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2438 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2439 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2440 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2445 static struct sysdev_class ioapic_sysdev_class
= {
2446 set_kset_name("ioapic"),
2447 .suspend
= ioapic_suspend
,
2448 .resume
= ioapic_resume
,
2451 static int __init
ioapic_init_sysfs(void)
2453 struct sys_device
* dev
;
2454 int i
, size
, error
= 0;
2456 error
= sysdev_class_register(&ioapic_sysdev_class
);
2460 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2461 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2462 * sizeof(struct IO_APIC_route_entry
);
2463 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
2464 if (!mp_ioapic_data
[i
]) {
2465 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2468 memset(mp_ioapic_data
[i
], 0, size
);
2469 dev
= &mp_ioapic_data
[i
]->dev
;
2471 dev
->cls
= &ioapic_sysdev_class
;
2472 error
= sysdev_register(dev
);
2474 kfree(mp_ioapic_data
[i
]);
2475 mp_ioapic_data
[i
] = NULL
;
2476 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2484 device_initcall(ioapic_init_sysfs
);
2487 * Dynamic irq allocate and deallocation
2489 int create_irq(void)
2491 /* Allocate an unused irq */
2492 int irq
, new, vector
= 0;
2493 unsigned long flags
;
2496 spin_lock_irqsave(&vector_lock
, flags
);
2497 for (new = (NR_IRQS
- 1); new >= 0; new--) {
2498 if (platform_legacy_irq(new))
2500 if (irq_vector
[new] != 0)
2502 vector
= __assign_irq_vector(new);
2503 if (likely(vector
> 0))
2507 spin_unlock_irqrestore(&vector_lock
, flags
);
2510 set_intr_gate(vector
, interrupt
[irq
]);
2511 dynamic_irq_init(irq
);
2516 void destroy_irq(unsigned int irq
)
2518 unsigned long flags
;
2520 dynamic_irq_cleanup(irq
);
2522 spin_lock_irqsave(&vector_lock
, flags
);
2523 irq_vector
[irq
] = 0;
2524 spin_unlock_irqrestore(&vector_lock
, flags
);
2528 * MSI mesage composition
2530 #ifdef CONFIG_PCI_MSI
2531 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2536 vector
= assign_irq_vector(irq
);
2538 dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2540 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2543 ((INT_DEST_MODE
== 0) ?
2544 MSI_ADDR_DEST_MODE_PHYSICAL
:
2545 MSI_ADDR_DEST_MODE_LOGICAL
) |
2546 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2547 MSI_ADDR_REDIRECTION_CPU
:
2548 MSI_ADDR_REDIRECTION_LOWPRI
) |
2549 MSI_ADDR_DEST_ID(dest
);
2552 MSI_DATA_TRIGGER_EDGE
|
2553 MSI_DATA_LEVEL_ASSERT
|
2554 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2555 MSI_DATA_DELIVERY_FIXED
:
2556 MSI_DATA_DELIVERY_LOWPRI
) |
2557 MSI_DATA_VECTOR(vector
);
2563 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2570 cpus_and(tmp
, mask
, cpu_online_map
);
2571 if (cpus_empty(tmp
))
2574 vector
= assign_irq_vector(irq
);
2578 dest
= cpu_mask_to_apicid(mask
);
2580 read_msi_msg(irq
, &msg
);
2582 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2583 msg
.data
|= MSI_DATA_VECTOR(vector
);
2584 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2585 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2587 write_msi_msg(irq
, &msg
);
2588 irq_desc
[irq
].affinity
= mask
;
2590 #endif /* CONFIG_SMP */
2593 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2594 * which implement the MSI or MSI-X Capability Structure.
2596 static struct irq_chip msi_chip
= {
2598 .unmask
= unmask_msi_irq
,
2599 .mask
= mask_msi_irq
,
2600 .ack
= ack_ioapic_irq
,
2602 .set_affinity
= set_msi_irq_affinity
,
2604 .retrigger
= ioapic_retrigger_irq
,
2607 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2615 set_irq_msi(irq
, desc
);
2616 ret
= msi_compose_msg(dev
, irq
, &msg
);
2622 write_msi_msg(irq
, &msg
);
2624 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
,
2630 void arch_teardown_msi_irq(unsigned int irq
)
2635 #endif /* CONFIG_PCI_MSI */
2638 * Hypertransport interrupt support
2640 #ifdef CONFIG_HT_IRQ
2644 static void target_ht_irq(unsigned int irq
, unsigned int dest
)
2646 struct ht_irq_msg msg
;
2647 fetch_ht_irq_msg(irq
, &msg
);
2649 msg
.address_lo
&= ~(HT_IRQ_LOW_DEST_ID_MASK
);
2650 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2652 msg
.address_lo
|= HT_IRQ_LOW_DEST_ID(dest
);
2653 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2655 write_ht_irq_msg(irq
, &msg
);
2658 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2663 cpus_and(tmp
, mask
, cpu_online_map
);
2664 if (cpus_empty(tmp
))
2667 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
2669 dest
= cpu_mask_to_apicid(mask
);
2671 target_ht_irq(irq
, dest
);
2672 irq_desc
[irq
].affinity
= mask
;
2676 static struct irq_chip ht_irq_chip
= {
2678 .mask
= mask_ht_irq
,
2679 .unmask
= unmask_ht_irq
,
2680 .ack
= ack_ioapic_irq
,
2682 .set_affinity
= set_ht_irq_affinity
,
2684 .retrigger
= ioapic_retrigger_irq
,
2687 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2691 vector
= assign_irq_vector(irq
);
2693 struct ht_irq_msg msg
;
2698 cpu_set(vector
>> 8, tmp
);
2699 dest
= cpu_mask_to_apicid(tmp
);
2701 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2705 HT_IRQ_LOW_DEST_ID(dest
) |
2706 HT_IRQ_LOW_VECTOR(vector
) |
2707 ((INT_DEST_MODE
== 0) ?
2708 HT_IRQ_LOW_DM_PHYSICAL
:
2709 HT_IRQ_LOW_DM_LOGICAL
) |
2710 HT_IRQ_LOW_RQEOI_EDGE
|
2711 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2712 HT_IRQ_LOW_MT_FIXED
:
2713 HT_IRQ_LOW_MT_ARBITRATED
) |
2714 HT_IRQ_LOW_IRQ_MASKED
;
2716 write_ht_irq_msg(irq
, &msg
);
2718 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2719 handle_edge_irq
, "edge");
2723 #endif /* CONFIG_HT_IRQ */
2725 /* --------------------------------------------------------------------------
2726 ACPI-based IOAPIC Configuration
2727 -------------------------------------------------------------------------- */
2731 int __init
io_apic_get_unique_id (int ioapic
, int apic_id
)
2733 union IO_APIC_reg_00 reg_00
;
2734 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2736 unsigned long flags
;
2740 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2741 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2742 * supports up to 16 on one shared APIC bus.
2744 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2745 * advantage of new APIC bus architecture.
2748 if (physids_empty(apic_id_map
))
2749 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2751 spin_lock_irqsave(&ioapic_lock
, flags
);
2752 reg_00
.raw
= io_apic_read(ioapic
, 0);
2753 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2755 if (apic_id
>= get_physical_broadcast()) {
2756 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2757 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2758 apic_id
= reg_00
.bits
.ID
;
2762 * Every APIC in a system must have a unique ID or we get lots of nice
2763 * 'stuck on smp_invalidate_needed IPI wait' messages.
2765 if (check_apicid_used(apic_id_map
, apic_id
)) {
2767 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2768 if (!check_apicid_used(apic_id_map
, i
))
2772 if (i
== get_physical_broadcast())
2773 panic("Max apic_id exceeded!\n");
2775 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2776 "trying %d\n", ioapic
, apic_id
, i
);
2781 tmp
= apicid_to_cpu_present(apic_id
);
2782 physids_or(apic_id_map
, apic_id_map
, tmp
);
2784 if (reg_00
.bits
.ID
!= apic_id
) {
2785 reg_00
.bits
.ID
= apic_id
;
2787 spin_lock_irqsave(&ioapic_lock
, flags
);
2788 io_apic_write(ioapic
, 0, reg_00
.raw
);
2789 reg_00
.raw
= io_apic_read(ioapic
, 0);
2790 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2793 if (reg_00
.bits
.ID
!= apic_id
) {
2794 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2799 apic_printk(APIC_VERBOSE
, KERN_INFO
2800 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2806 int __init
io_apic_get_version (int ioapic
)
2808 union IO_APIC_reg_01 reg_01
;
2809 unsigned long flags
;
2811 spin_lock_irqsave(&ioapic_lock
, flags
);
2812 reg_01
.raw
= io_apic_read(ioapic
, 1);
2813 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2815 return reg_01
.bits
.version
;
2819 int __init
io_apic_get_redir_entries (int ioapic
)
2821 union IO_APIC_reg_01 reg_01
;
2822 unsigned long flags
;
2824 spin_lock_irqsave(&ioapic_lock
, flags
);
2825 reg_01
.raw
= io_apic_read(ioapic
, 1);
2826 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2828 return reg_01
.bits
.entries
;
2832 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2834 struct IO_APIC_route_entry entry
;
2835 unsigned long flags
;
2837 if (!IO_APIC_IRQ(irq
)) {
2838 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2844 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2845 * Note that we mask (disable) IRQs now -- these get enabled when the
2846 * corresponding device driver registers for this IRQ.
2849 memset(&entry
,0,sizeof(entry
));
2851 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2852 entry
.dest_mode
= INT_DEST_MODE
;
2853 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2854 entry
.trigger
= edge_level
;
2855 entry
.polarity
= active_high_low
;
2859 * IRQs < 16 are already in the irq_2_pin[] map
2862 add_pin_to_irq(irq
, ioapic
, pin
);
2864 entry
.vector
= assign_irq_vector(irq
);
2866 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2867 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2868 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
,
2869 edge_level
, active_high_low
);
2871 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2873 if (!ioapic
&& (irq
< 16))
2874 disable_8259A_irq(irq
);
2876 spin_lock_irqsave(&ioapic_lock
, flags
);
2877 __ioapic_write_entry(ioapic
, pin
, entry
);
2878 irq_desc
[irq
].affinity
= TARGET_CPUS
;
2879 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2884 #endif /* CONFIG_ACPI */
2886 static int __init
parse_disable_timer_pin_1(char *arg
)
2888 disable_timer_pin_1
= 1;
2891 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2893 static int __init
parse_enable_timer_pin_1(char *arg
)
2895 disable_timer_pin_1
= -1;
2898 early_param("enable_timer_pin_1", parse_enable_timer_pin_1
);
2900 static int __init
parse_noapic(char *arg
)
2902 /* disable IO-APIC */
2903 disable_ioapic_setup();
2906 early_param("noapic", parse_noapic
);