2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
38 #include <asm/timer.h>
39 #include <asm/i8259.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
47 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
48 atomic_t irq_mis_count
;
50 /* Where if anywhere is the i8259 connect in external int mode */
51 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
53 static DEFINE_SPINLOCK(ioapic_lock
);
54 static DEFINE_SPINLOCK(vector_lock
);
56 int timer_over_8254 __initdata
= 1;
59 * Is the SiS APIC rmw bug present ?
60 * -1 = don't know, 0 = no, 1 = yes
62 int sis_apic_bug
= -1;
65 * # of IRQ routing registers
67 int nr_ioapic_registers
[MAX_IO_APICS
];
69 static int disable_timer_pin_1 __initdata
;
72 * Rough estimation of how many shared IRQs there are, can
75 #define MAX_PLUS_SHARED_IRQS NR_IRQS
76 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
79 * This is performance-critical, we want to do it O(1)
81 * the indexing order of this array favors 1:1 mappings
82 * between pins and IRQs.
85 static struct irq_pin_list
{
87 } irq_2_pin
[PIN_MAP_SIZE
];
89 int vector_irq
[NR_VECTORS
] __read_mostly
= { [0 ... NR_VECTORS
- 1] = -1};
91 #define vector_to_irq(vector) \
92 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
94 #define vector_to_irq(vector) (vector)
99 struct { u32 w1
, w2
; };
100 struct IO_APIC_route_entry entry
;
103 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
105 union entry_union eu
;
107 spin_lock_irqsave(&ioapic_lock
, flags
);
108 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
109 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
110 spin_unlock_irqrestore(&ioapic_lock
, flags
);
114 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
117 union entry_union eu
;
119 spin_lock_irqsave(&ioapic_lock
, flags
);
120 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
121 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
122 spin_unlock_irqrestore(&ioapic_lock
, flags
);
126 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
127 * shared ISA-space IRQs, so we have to support them. We are super
128 * fast in the common case, and fast for shared ISA-space IRQs.
130 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
132 static int first_free_entry
= NR_IRQS
;
133 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
136 entry
= irq_2_pin
+ entry
->next
;
138 if (entry
->pin
!= -1) {
139 entry
->next
= first_free_entry
;
140 entry
= irq_2_pin
+ entry
->next
;
141 if (++first_free_entry
>= PIN_MAP_SIZE
)
142 panic("io_apic.c: whoops");
149 * Reroute an IRQ to a different pin.
151 static void __init
replace_pin_at_irq(unsigned int irq
,
152 int oldapic
, int oldpin
,
153 int newapic
, int newpin
)
155 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
158 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
159 entry
->apic
= newapic
;
164 entry
= irq_2_pin
+ entry
->next
;
168 static void __modify_IO_APIC_irq (unsigned int irq
, unsigned long enable
, unsigned long disable
)
170 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
171 unsigned int pin
, reg
;
177 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
180 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
183 entry
= irq_2_pin
+ entry
->next
;
188 static void __mask_IO_APIC_irq (unsigned int irq
)
190 __modify_IO_APIC_irq(irq
, 0x00010000, 0);
194 static void __unmask_IO_APIC_irq (unsigned int irq
)
196 __modify_IO_APIC_irq(irq
, 0, 0x00010000);
199 /* mask = 1, trigger = 0 */
200 static void __mask_and_edge_IO_APIC_irq (unsigned int irq
)
202 __modify_IO_APIC_irq(irq
, 0x00010000, 0x00008000);
205 /* mask = 0, trigger = 1 */
206 static void __unmask_and_level_IO_APIC_irq (unsigned int irq
)
208 __modify_IO_APIC_irq(irq
, 0x00008000, 0x00010000);
211 static void mask_IO_APIC_irq (unsigned int irq
)
215 spin_lock_irqsave(&ioapic_lock
, flags
);
216 __mask_IO_APIC_irq(irq
);
217 spin_unlock_irqrestore(&ioapic_lock
, flags
);
220 static void unmask_IO_APIC_irq (unsigned int irq
)
224 spin_lock_irqsave(&ioapic_lock
, flags
);
225 __unmask_IO_APIC_irq(irq
);
226 spin_unlock_irqrestore(&ioapic_lock
, flags
);
229 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
231 struct IO_APIC_route_entry entry
;
233 /* Check delivery_mode to be sure we're not clearing an SMI pin */
234 entry
= ioapic_read_entry(apic
, pin
);
235 if (entry
.delivery_mode
== dest_SMI
)
239 * Disable it in the IO-APIC irq-routing table:
241 memset(&entry
, 0, sizeof(entry
));
243 ioapic_write_entry(apic
, pin
, entry
);
246 static void clear_IO_APIC (void)
250 for (apic
= 0; apic
< nr_ioapics
; apic
++)
251 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
252 clear_IO_APIC_pin(apic
, pin
);
256 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
260 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
261 unsigned int apicid_value
;
264 cpus_and(tmp
, cpumask
, cpu_online_map
);
268 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
270 apicid_value
= cpu_mask_to_apicid(cpumask
);
271 /* Prepare to do the io_apic_write */
272 apicid_value
= apicid_value
<< 24;
273 spin_lock_irqsave(&ioapic_lock
, flags
);
278 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
281 entry
= irq_2_pin
+ entry
->next
;
283 set_irq_info(irq
, cpumask
);
284 spin_unlock_irqrestore(&ioapic_lock
, flags
);
287 #if defined(CONFIG_IRQBALANCE)
288 # include <asm/processor.h> /* kernel_thread() */
289 # include <linux/kernel_stat.h> /* kstat */
290 # include <linux/slab.h> /* kmalloc() */
291 # include <linux/timer.h> /* time_after() */
293 #ifdef CONFIG_BALANCED_IRQ_DEBUG
294 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
295 # define Dprintk(x...) do { TDprintk(x); } while (0)
297 # define TDprintk(x...)
298 # define Dprintk(x...)
301 #define IRQBALANCE_CHECK_ARCH -999
302 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
303 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
304 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
305 #define BALANCED_IRQ_LESS_DELTA (HZ)
307 static int irqbalance_disabled __read_mostly
= IRQBALANCE_CHECK_ARCH
;
308 static int physical_balance __read_mostly
;
309 static long balanced_irq_interval __read_mostly
= MAX_BALANCED_IRQ_INTERVAL
;
311 static struct irq_cpu_info
{
312 unsigned long * last_irq
;
313 unsigned long * irq_delta
;
315 } irq_cpu_data
[NR_CPUS
];
317 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
318 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
319 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
321 #define IDLE_ENOUGH(cpu,now) \
322 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
324 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
326 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
328 static cpumask_t balance_irq_affinity
[NR_IRQS
] = {
329 [0 ... NR_IRQS
-1] = CPU_MASK_ALL
332 void set_balance_irq_affinity(unsigned int irq
, cpumask_t mask
)
334 balance_irq_affinity
[irq
] = mask
;
337 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
338 unsigned long now
, int direction
)
346 if (unlikely(cpu
== curr_cpu
))
349 if (direction
== 1) {
358 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
,allowed_mask
) ||
359 (search_idle
&& !IDLE_ENOUGH(cpu
,now
)));
364 static inline void balance_irq(int cpu
, int irq
)
366 unsigned long now
= jiffies
;
367 cpumask_t allowed_mask
;
368 unsigned int new_cpu
;
370 if (irqbalance_disabled
)
373 cpus_and(allowed_mask
, cpu_online_map
, balance_irq_affinity
[irq
]);
374 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
375 if (cpu
!= new_cpu
) {
376 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
380 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
383 Dprintk("Rotating IRQs among CPUs.\n");
384 for_each_online_cpu(i
) {
385 for (j
= 0; j
< NR_IRQS
; j
++) {
386 if (!irq_desc
[j
].action
)
388 /* Is it a significant load ? */
389 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
),j
) <
390 useful_load_threshold
)
395 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
396 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
400 static void do_irq_balance(void)
403 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
404 unsigned long move_this_load
= 0;
405 int max_loaded
= 0, min_loaded
= 0;
407 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
409 int tmp_loaded
, first_attempt
= 1;
410 unsigned long tmp_cpu_irq
;
411 unsigned long imbalance
= 0;
412 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
414 for_each_possible_cpu(i
) {
419 package_index
= CPU_TO_PACKAGEINDEX(i
);
420 for (j
= 0; j
< NR_IRQS
; j
++) {
421 unsigned long value_now
, delta
;
422 /* Is this an active IRQ? */
423 if (!irq_desc
[j
].action
)
425 if ( package_index
== i
)
426 IRQ_DELTA(package_index
,j
) = 0;
427 /* Determine the total count per processor per IRQ */
428 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
430 /* Determine the activity per processor per IRQ */
431 delta
= value_now
- LAST_CPU_IRQ(i
,j
);
433 /* Update last_cpu_irq[][] for the next time */
434 LAST_CPU_IRQ(i
,j
) = value_now
;
436 /* Ignore IRQs whose rate is less than the clock */
437 if (delta
< useful_load_threshold
)
439 /* update the load for the processor or package total */
440 IRQ_DELTA(package_index
,j
) += delta
;
442 /* Keep track of the higher numbered sibling as well */
443 if (i
!= package_index
)
446 * We have sibling A and sibling B in the package
448 * cpu_irq[A] = load for cpu A + load for cpu B
449 * cpu_irq[B] = load for cpu B
451 CPU_IRQ(package_index
) += delta
;
454 /* Find the least loaded processor package */
455 for_each_online_cpu(i
) {
456 if (i
!= CPU_TO_PACKAGEINDEX(i
))
458 if (min_cpu_irq
> CPU_IRQ(i
)) {
459 min_cpu_irq
= CPU_IRQ(i
);
463 max_cpu_irq
= ULONG_MAX
;
466 /* Look for heaviest loaded processor.
467 * We may come back to get the next heaviest loaded processor.
468 * Skip processors with trivial loads.
472 for_each_online_cpu(i
) {
473 if (i
!= CPU_TO_PACKAGEINDEX(i
))
475 if (max_cpu_irq
<= CPU_IRQ(i
))
477 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
478 tmp_cpu_irq
= CPU_IRQ(i
);
483 if (tmp_loaded
== -1) {
484 /* In the case of small number of heavy interrupt sources,
485 * loading some of the cpus too much. We use Ingo's original
486 * approach to rotate them around.
488 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
489 rotate_irqs_among_cpus(useful_load_threshold
);
492 goto not_worth_the_effort
;
495 first_attempt
= 0; /* heaviest search */
496 max_cpu_irq
= tmp_cpu_irq
; /* load */
497 max_loaded
= tmp_loaded
; /* processor */
498 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
500 Dprintk("max_loaded cpu = %d\n", max_loaded
);
501 Dprintk("min_loaded cpu = %d\n", min_loaded
);
502 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq
);
503 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq
);
504 Dprintk("load imbalance = %lu\n", imbalance
);
506 /* if imbalance is less than approx 10% of max load, then
507 * observe diminishing returns action. - quit
509 if (imbalance
< (max_cpu_irq
>> 3)) {
510 Dprintk("Imbalance too trivial\n");
511 goto not_worth_the_effort
;
515 /* if we select an IRQ to move that can't go where we want, then
516 * see if there is another one to try.
520 for (j
= 0; j
< NR_IRQS
; j
++) {
521 /* Is this an active IRQ? */
522 if (!irq_desc
[j
].action
)
524 if (imbalance
<= IRQ_DELTA(max_loaded
,j
))
526 /* Try to find the IRQ that is closest to the imbalance
527 * without going over.
529 if (move_this_load
< IRQ_DELTA(max_loaded
,j
)) {
530 move_this_load
= IRQ_DELTA(max_loaded
,j
);
534 if (selected_irq
== -1) {
538 imbalance
= move_this_load
;
540 /* For physical_balance case, we accumlated both load
541 * values in the one of the siblings cpu_irq[],
542 * to use the same code for physical and logical processors
543 * as much as possible.
545 * NOTE: the cpu_irq[] array holds the sum of the load for
546 * sibling A and sibling B in the slot for the lowest numbered
547 * sibling (A), _AND_ the load for sibling B in the slot for
548 * the higher numbered sibling.
550 * We seek the least loaded sibling by making the comparison
553 load
= CPU_IRQ(min_loaded
) >> 1;
554 for_each_cpu_mask(j
, cpu_sibling_map
[min_loaded
]) {
555 if (load
> CPU_IRQ(j
)) {
556 /* This won't change cpu_sibling_map[min_loaded] */
562 cpus_and(allowed_mask
,
564 balance_irq_affinity
[selected_irq
]);
565 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
566 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
568 if (!cpus_empty(tmp
)) {
570 Dprintk("irq = %d moved to cpu = %d\n",
571 selected_irq
, min_loaded
);
572 /* mark for change destination */
573 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
575 /* Since we made a change, come back sooner to
576 * check for more variation.
578 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
579 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
584 not_worth_the_effort
:
586 * if we did not find an IRQ to move, then adjust the time interval
589 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
590 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
591 Dprintk("IRQ worth rotating not found\n");
595 static int balanced_irq(void *unused
)
598 unsigned long prev_balance_time
= jiffies
;
599 long time_remaining
= balanced_irq_interval
;
603 /* push everything to CPU 0 to give us a starting point. */
604 for (i
= 0 ; i
< NR_IRQS
; i
++) {
605 irq_desc
[i
].pending_mask
= cpumask_of_cpu(0);
606 set_pending_irq(i
, cpumask_of_cpu(0));
610 time_remaining
= schedule_timeout_interruptible(time_remaining
);
612 if (time_after(jiffies
,
613 prev_balance_time
+balanced_irq_interval
)) {
616 prev_balance_time
= jiffies
;
617 time_remaining
= balanced_irq_interval
;
624 static int __init
balanced_irq_init(void)
627 struct cpuinfo_x86
*c
;
630 cpus_shift_right(tmp
, cpu_online_map
, 2);
632 /* When not overwritten by the command line ask subarchitecture. */
633 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
634 irqbalance_disabled
= NO_BALANCE_IRQ
;
635 if (irqbalance_disabled
)
638 /* disable irqbalance completely if there is only one processor online */
639 if (num_online_cpus() < 2) {
640 irqbalance_disabled
= 1;
644 * Enable physical balance only if more than 1 physical processor
647 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
648 physical_balance
= 1;
650 for_each_online_cpu(i
) {
651 irq_cpu_data
[i
].irq_delta
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
652 irq_cpu_data
[i
].last_irq
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
653 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
654 printk(KERN_ERR
"balanced_irq_init: out of memory");
657 memset(irq_cpu_data
[i
].irq_delta
,0,sizeof(unsigned long) * NR_IRQS
);
658 memset(irq_cpu_data
[i
].last_irq
,0,sizeof(unsigned long) * NR_IRQS
);
661 printk(KERN_INFO
"Starting balanced_irq\n");
662 if (kernel_thread(balanced_irq
, NULL
, CLONE_KERNEL
) >= 0)
665 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
667 for_each_possible_cpu(i
) {
668 kfree(irq_cpu_data
[i
].irq_delta
);
669 irq_cpu_data
[i
].irq_delta
= NULL
;
670 kfree(irq_cpu_data
[i
].last_irq
);
671 irq_cpu_data
[i
].last_irq
= NULL
;
676 int __init
irqbalance_disable(char *str
)
678 irqbalance_disabled
= 1;
682 __setup("noirqbalance", irqbalance_disable
);
684 late_initcall(balanced_irq_init
);
685 #endif /* CONFIG_IRQBALANCE */
686 #endif /* CONFIG_SMP */
689 void fastcall
send_IPI_self(int vector
)
696 apic_wait_icr_idle();
697 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
699 * Send the IPI. The write to APIC_ICR fires this off.
701 apic_write_around(APIC_ICR
, cfg
);
703 #endif /* !CONFIG_SMP */
707 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
708 * specific CPU-side IRQs.
712 static int pirq_entries
[MAX_PIRQS
];
713 static int pirqs_enabled
;
714 int skip_ioapic_setup
;
716 static int __init
ioapic_setup(char *str
)
718 skip_ioapic_setup
= 1;
722 __setup("noapic", ioapic_setup
);
724 static int __init
ioapic_pirq_setup(char *str
)
727 int ints
[MAX_PIRQS
+1];
729 get_options(str
, ARRAY_SIZE(ints
), ints
);
731 for (i
= 0; i
< MAX_PIRQS
; i
++)
732 pirq_entries
[i
] = -1;
735 apic_printk(APIC_VERBOSE
, KERN_INFO
736 "PIRQ redirection, working around broken MP-BIOS.\n");
738 if (ints
[0] < MAX_PIRQS
)
741 for (i
= 0; i
< max
; i
++) {
742 apic_printk(APIC_VERBOSE
, KERN_DEBUG
743 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
745 * PIRQs are mapped upside down, usually.
747 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
752 __setup("pirq=", ioapic_pirq_setup
);
755 * Find the IRQ entry number of a certain pin.
757 static int find_irq_entry(int apic
, int pin
, int type
)
761 for (i
= 0; i
< mp_irq_entries
; i
++)
762 if (mp_irqs
[i
].mpc_irqtype
== type
&&
763 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
764 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
765 mp_irqs
[i
].mpc_dstirq
== pin
)
772 * Find the pin to which IRQ[irq] (ISA) is connected
774 static int __init
find_isa_irq_pin(int irq
, int type
)
778 for (i
= 0; i
< mp_irq_entries
; i
++) {
779 int lbus
= mp_irqs
[i
].mpc_srcbus
;
781 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
782 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
783 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
||
784 mp_bus_id_to_type
[lbus
] == MP_BUS_NEC98
786 (mp_irqs
[i
].mpc_irqtype
== type
) &&
787 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
789 return mp_irqs
[i
].mpc_dstirq
;
794 static int __init
find_isa_irq_apic(int irq
, int type
)
798 for (i
= 0; i
< mp_irq_entries
; i
++) {
799 int lbus
= mp_irqs
[i
].mpc_srcbus
;
801 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
802 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
803 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
||
804 mp_bus_id_to_type
[lbus
] == MP_BUS_NEC98
806 (mp_irqs
[i
].mpc_irqtype
== type
) &&
807 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
810 if (i
< mp_irq_entries
) {
812 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
813 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
822 * Find a specific PCI IRQ entry.
823 * Not an __init, possibly needed by modules
825 static int pin_2_irq(int idx
, int apic
, int pin
);
827 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
829 int apic
, i
, best_guess
= -1;
831 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
832 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
833 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
834 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
837 for (i
= 0; i
< mp_irq_entries
; i
++) {
838 int lbus
= mp_irqs
[i
].mpc_srcbus
;
840 for (apic
= 0; apic
< nr_ioapics
; apic
++)
841 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
842 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
845 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
846 !mp_irqs
[i
].mpc_irqtype
&&
848 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
849 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
851 if (!(apic
|| IO_APIC_IRQ(irq
)))
854 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
857 * Use the first all-but-pin matching entry as a
858 * best-guess fuzzy result for broken mptables.
866 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
869 * This function currently is only a helper for the i386 smp boot process where
870 * we need to reprogram the ioredtbls to cater for the cpus which have come online
871 * so mask in all cases should simply be TARGET_CPUS
874 void __init
setup_ioapic_dest(void)
876 int pin
, ioapic
, irq
, irq_entry
;
878 if (skip_ioapic_setup
== 1)
881 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
882 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
883 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
886 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
887 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
895 * EISA Edge/Level control register, ELCR
897 static int EISA_ELCR(unsigned int irq
)
900 unsigned int port
= 0x4d0 + (irq
>> 3);
901 return (inb(port
) >> (irq
& 7)) & 1;
903 apic_printk(APIC_VERBOSE
, KERN_INFO
904 "Broken MPtable reports ISA irq %d\n", irq
);
908 /* EISA interrupts are always polarity zero and can be edge or level
909 * trigger depending on the ELCR value. If an interrupt is listed as
910 * EISA conforming in the MP table, that means its trigger type must
911 * be read in from the ELCR */
913 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
914 #define default_EISA_polarity(idx) (0)
916 /* ISA interrupts are always polarity zero edge triggered,
917 * when listed as conforming in the MP table. */
919 #define default_ISA_trigger(idx) (0)
920 #define default_ISA_polarity(idx) (0)
922 /* PCI interrupts are always polarity one level triggered,
923 * when listed as conforming in the MP table. */
925 #define default_PCI_trigger(idx) (1)
926 #define default_PCI_polarity(idx) (1)
928 /* MCA interrupts are always polarity zero level triggered,
929 * when listed as conforming in the MP table. */
931 #define default_MCA_trigger(idx) (1)
932 #define default_MCA_polarity(idx) (0)
934 /* NEC98 interrupts are always polarity zero edge triggered,
935 * when listed as conforming in the MP table. */
937 #define default_NEC98_trigger(idx) (0)
938 #define default_NEC98_polarity(idx) (0)
940 static int __init
MPBIOS_polarity(int idx
)
942 int bus
= mp_irqs
[idx
].mpc_srcbus
;
946 * Determine IRQ line polarity (high active or low active):
948 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
950 case 0: /* conforms, ie. bus-type dependent polarity */
952 switch (mp_bus_id_to_type
[bus
])
954 case MP_BUS_ISA
: /* ISA pin */
956 polarity
= default_ISA_polarity(idx
);
959 case MP_BUS_EISA
: /* EISA pin */
961 polarity
= default_EISA_polarity(idx
);
964 case MP_BUS_PCI
: /* PCI pin */
966 polarity
= default_PCI_polarity(idx
);
969 case MP_BUS_MCA
: /* MCA pin */
971 polarity
= default_MCA_polarity(idx
);
974 case MP_BUS_NEC98
: /* NEC 98 pin */
976 polarity
= default_NEC98_polarity(idx
);
981 printk(KERN_WARNING
"broken BIOS!!\n");
988 case 1: /* high active */
993 case 2: /* reserved */
995 printk(KERN_WARNING
"broken BIOS!!\n");
999 case 3: /* low active */
1004 default: /* invalid */
1006 printk(KERN_WARNING
"broken BIOS!!\n");
1014 static int MPBIOS_trigger(int idx
)
1016 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1020 * Determine IRQ trigger mode (edge or level sensitive):
1022 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
1024 case 0: /* conforms, ie. bus-type dependent */
1026 switch (mp_bus_id_to_type
[bus
])
1028 case MP_BUS_ISA
: /* ISA pin */
1030 trigger
= default_ISA_trigger(idx
);
1033 case MP_BUS_EISA
: /* EISA pin */
1035 trigger
= default_EISA_trigger(idx
);
1038 case MP_BUS_PCI
: /* PCI pin */
1040 trigger
= default_PCI_trigger(idx
);
1043 case MP_BUS_MCA
: /* MCA pin */
1045 trigger
= default_MCA_trigger(idx
);
1048 case MP_BUS_NEC98
: /* NEC 98 pin */
1050 trigger
= default_NEC98_trigger(idx
);
1055 printk(KERN_WARNING
"broken BIOS!!\n");
1067 case 2: /* reserved */
1069 printk(KERN_WARNING
"broken BIOS!!\n");
1078 default: /* invalid */
1080 printk(KERN_WARNING
"broken BIOS!!\n");
1088 static inline int irq_polarity(int idx
)
1090 return MPBIOS_polarity(idx
);
1093 static inline int irq_trigger(int idx
)
1095 return MPBIOS_trigger(idx
);
1098 static int pin_2_irq(int idx
, int apic
, int pin
)
1101 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1104 * Debugging check, we are in big trouble if this message pops up!
1106 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
1107 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1109 switch (mp_bus_id_to_type
[bus
])
1111 case MP_BUS_ISA
: /* ISA pin */
1116 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
1119 case MP_BUS_PCI
: /* PCI pin */
1122 * PCI IRQs are mapped in order
1126 irq
+= nr_ioapic_registers
[i
++];
1130 * For MPS mode, so far only needed by ES7000 platform
1132 if (ioapic_renumber_irq
)
1133 irq
= ioapic_renumber_irq(apic
, irq
);
1139 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
1146 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1148 if ((pin
>= 16) && (pin
<= 23)) {
1149 if (pirq_entries
[pin
-16] != -1) {
1150 if (!pirq_entries
[pin
-16]) {
1151 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1152 "disabling PIRQ%d\n", pin
-16);
1154 irq
= pirq_entries
[pin
-16];
1155 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1156 "using PIRQ%d -> IRQ %d\n",
1164 static inline int IO_APIC_irq_trigger(int irq
)
1168 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1169 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1170 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1171 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
1172 return irq_trigger(idx
);
1176 * nonexistent IRQs are edge default
1181 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1182 u8 irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_DEVICE_VECTOR
, 0 };
1184 int assign_irq_vector(int irq
)
1186 static int current_vector
= FIRST_DEVICE_VECTOR
, offset
= 0;
1187 unsigned long flags
;
1190 BUG_ON(irq
!= AUTO_ASSIGN
&& (unsigned)irq
>= NR_IRQ_VECTORS
);
1192 spin_lock_irqsave(&vector_lock
, flags
);
1194 if (irq
!= AUTO_ASSIGN
&& IO_APIC_VECTOR(irq
) > 0) {
1195 spin_unlock_irqrestore(&vector_lock
, flags
);
1196 return IO_APIC_VECTOR(irq
);
1199 current_vector
+= 8;
1200 if (current_vector
== SYSCALL_VECTOR
)
1203 if (current_vector
>= FIRST_SYSTEM_VECTOR
) {
1206 spin_unlock_irqrestore(&vector_lock
, flags
);
1209 current_vector
= FIRST_DEVICE_VECTOR
+ offset
;
1212 vector
= current_vector
;
1213 vector_irq
[vector
] = irq
;
1214 if (irq
!= AUTO_ASSIGN
)
1215 IO_APIC_VECTOR(irq
) = vector
;
1217 spin_unlock_irqrestore(&vector_lock
, flags
);
1222 static struct irq_chip ioapic_chip
;
1224 #define IOAPIC_AUTO -1
1225 #define IOAPIC_EDGE 0
1226 #define IOAPIC_LEVEL 1
1228 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1232 idx
= use_pci_vector() && !platform_legacy_irq(irq
) ? vector
: irq
;
1234 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1235 trigger
== IOAPIC_LEVEL
)
1236 set_irq_chip_and_handler(idx
, &ioapic_chip
,
1237 handle_fasteoi_irq
);
1239 set_irq_chip_and_handler(idx
, &ioapic_chip
,
1241 set_intr_gate(vector
, interrupt
[idx
]);
1244 static void __init
setup_IO_APIC_irqs(void)
1246 struct IO_APIC_route_entry entry
;
1247 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1248 unsigned long flags
;
1250 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1252 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1253 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1256 * add it to the IO-APIC irq-routing table:
1258 memset(&entry
,0,sizeof(entry
));
1260 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1261 entry
.dest_mode
= INT_DEST_MODE
;
1262 entry
.mask
= 0; /* enable IRQ */
1263 entry
.dest
.logical
.logical_dest
=
1264 cpu_mask_to_apicid(TARGET_CPUS
);
1266 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1269 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1270 " IO-APIC (apicid-pin) %d-%d",
1271 mp_ioapics
[apic
].mpc_apicid
,
1275 apic_printk(APIC_VERBOSE
, ", %d-%d",
1276 mp_ioapics
[apic
].mpc_apicid
, pin
);
1280 entry
.trigger
= irq_trigger(idx
);
1281 entry
.polarity
= irq_polarity(idx
);
1283 if (irq_trigger(idx
)) {
1288 irq
= pin_2_irq(idx
, apic
, pin
);
1290 * skip adding the timer int on secondary nodes, which causes
1291 * a small but painful rift in the time-space continuum
1293 if (multi_timer_check(apic
, irq
))
1296 add_pin_to_irq(irq
, apic
, pin
);
1298 if (!apic
&& !IO_APIC_IRQ(irq
))
1301 if (IO_APIC_IRQ(irq
)) {
1302 vector
= assign_irq_vector(irq
);
1303 entry
.vector
= vector
;
1304 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1306 if (!apic
&& (irq
< 16))
1307 disable_8259A_irq(irq
);
1309 ioapic_write_entry(apic
, pin
, entry
);
1310 spin_lock_irqsave(&ioapic_lock
, flags
);
1311 set_native_irq_info(irq
, TARGET_CPUS
);
1312 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1317 apic_printk(APIC_VERBOSE
, " not connected.\n");
1321 * Set up the 8259A-master output pin:
1323 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
1325 struct IO_APIC_route_entry entry
;
1327 memset(&entry
,0,sizeof(entry
));
1329 disable_8259A_irq(0);
1332 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1335 * We use logical delivery to get the timer IRQ
1338 entry
.dest_mode
= INT_DEST_MODE
;
1339 entry
.mask
= 0; /* unmask IRQ now */
1340 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1341 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1344 entry
.vector
= vector
;
1347 * The timer IRQ doesn't have to know that behind the
1348 * scene we have a 8259A-master in AEOI mode ...
1350 irq_desc
[0].chip
= &ioapic_chip
;
1351 set_irq_handler(0, handle_edge_irq
);
1354 * Add it to the IO-APIC irq-routing table:
1356 ioapic_write_entry(apic
, pin
, entry
);
1358 enable_8259A_irq(0);
1361 static inline void UNEXPECTED_IO_APIC(void)
1365 void __init
print_IO_APIC(void)
1368 union IO_APIC_reg_00 reg_00
;
1369 union IO_APIC_reg_01 reg_01
;
1370 union IO_APIC_reg_02 reg_02
;
1371 union IO_APIC_reg_03 reg_03
;
1372 unsigned long flags
;
1374 if (apic_verbosity
== APIC_QUIET
)
1377 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1378 for (i
= 0; i
< nr_ioapics
; i
++)
1379 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1380 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
1383 * We are a bit conservative about what we expect. We have to
1384 * know about every hardware change ASAP.
1386 printk(KERN_INFO
"testing the IO APIC.......................\n");
1388 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1390 spin_lock_irqsave(&ioapic_lock
, flags
);
1391 reg_00
.raw
= io_apic_read(apic
, 0);
1392 reg_01
.raw
= io_apic_read(apic
, 1);
1393 if (reg_01
.bits
.version
>= 0x10)
1394 reg_02
.raw
= io_apic_read(apic
, 2);
1395 if (reg_01
.bits
.version
>= 0x20)
1396 reg_03
.raw
= io_apic_read(apic
, 3);
1397 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1399 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
1400 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1401 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1402 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1403 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1404 if (reg_00
.bits
.ID
>= get_physical_broadcast())
1405 UNEXPECTED_IO_APIC();
1406 if (reg_00
.bits
.__reserved_1
|| reg_00
.bits
.__reserved_2
)
1407 UNEXPECTED_IO_APIC();
1409 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1410 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1411 if ( (reg_01
.bits
.entries
!= 0x0f) && /* older (Neptune) boards */
1412 (reg_01
.bits
.entries
!= 0x17) && /* typical ISA+PCI boards */
1413 (reg_01
.bits
.entries
!= 0x1b) && /* Compaq Proliant boards */
1414 (reg_01
.bits
.entries
!= 0x1f) && /* dual Xeon boards */
1415 (reg_01
.bits
.entries
!= 0x22) && /* bigger Xeon boards */
1416 (reg_01
.bits
.entries
!= 0x2E) &&
1417 (reg_01
.bits
.entries
!= 0x3F)
1419 UNEXPECTED_IO_APIC();
1421 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1422 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1423 if ( (reg_01
.bits
.version
!= 0x01) && /* 82489DX IO-APICs */
1424 (reg_01
.bits
.version
!= 0x10) && /* oldest IO-APICs */
1425 (reg_01
.bits
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
1426 (reg_01
.bits
.version
!= 0x13) && /* Xeon IO-APICs */
1427 (reg_01
.bits
.version
!= 0x20) /* Intel P64H (82806 AA) */
1429 UNEXPECTED_IO_APIC();
1430 if (reg_01
.bits
.__reserved_1
|| reg_01
.bits
.__reserved_2
)
1431 UNEXPECTED_IO_APIC();
1434 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1435 * but the value of reg_02 is read as the previous read register
1436 * value, so ignore it if reg_02 == reg_01.
1438 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1439 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1440 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1441 if (reg_02
.bits
.__reserved_1
|| reg_02
.bits
.__reserved_2
)
1442 UNEXPECTED_IO_APIC();
1446 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1447 * or reg_03, but the value of reg_0[23] is read as the previous read
1448 * register value, so ignore it if reg_03 == reg_0[12].
1450 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1451 reg_03
.raw
!= reg_01
.raw
) {
1452 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1453 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1454 if (reg_03
.bits
.__reserved_1
)
1455 UNEXPECTED_IO_APIC();
1458 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1460 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1461 " Stat Dest Deli Vect: \n");
1463 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1464 struct IO_APIC_route_entry entry
;
1466 entry
= ioapic_read_entry(apic
, i
);
1468 printk(KERN_DEBUG
" %02x %03X %02X ",
1470 entry
.dest
.logical
.logical_dest
,
1471 entry
.dest
.physical
.physical_dest
1474 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1479 entry
.delivery_status
,
1481 entry
.delivery_mode
,
1486 if (use_pci_vector())
1487 printk(KERN_INFO
"Using vector-based indexing\n");
1488 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1489 for (i
= 0; i
< NR_IRQS
; i
++) {
1490 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1493 if (use_pci_vector() && !platform_legacy_irq(i
))
1494 printk(KERN_DEBUG
"IRQ%d ", IO_APIC_VECTOR(i
));
1496 printk(KERN_DEBUG
"IRQ%d ", i
);
1498 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1501 entry
= irq_2_pin
+ entry
->next
;
1506 printk(KERN_INFO
".................................... done.\n");
1513 static void print_APIC_bitfield (int base
)
1518 if (apic_verbosity
== APIC_QUIET
)
1521 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1522 for (i
= 0; i
< 8; i
++) {
1523 v
= apic_read(base
+ i
*0x10);
1524 for (j
= 0; j
< 32; j
++) {
1534 void /*__init*/ print_local_APIC(void * dummy
)
1536 unsigned int v
, ver
, maxlvt
;
1538 if (apic_verbosity
== APIC_QUIET
)
1541 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1542 smp_processor_id(), hard_smp_processor_id());
1543 v
= apic_read(APIC_ID
);
1544 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
1545 v
= apic_read(APIC_LVR
);
1546 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1547 ver
= GET_APIC_VERSION(v
);
1548 maxlvt
= get_maxlvt();
1550 v
= apic_read(APIC_TASKPRI
);
1551 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1553 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1554 v
= apic_read(APIC_ARBPRI
);
1555 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1556 v
& APIC_ARBPRI_MASK
);
1557 v
= apic_read(APIC_PROCPRI
);
1558 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1561 v
= apic_read(APIC_EOI
);
1562 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1563 v
= apic_read(APIC_RRR
);
1564 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1565 v
= apic_read(APIC_LDR
);
1566 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1567 v
= apic_read(APIC_DFR
);
1568 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1569 v
= apic_read(APIC_SPIV
);
1570 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1572 printk(KERN_DEBUG
"... APIC ISR field:\n");
1573 print_APIC_bitfield(APIC_ISR
);
1574 printk(KERN_DEBUG
"... APIC TMR field:\n");
1575 print_APIC_bitfield(APIC_TMR
);
1576 printk(KERN_DEBUG
"... APIC IRR field:\n");
1577 print_APIC_bitfield(APIC_IRR
);
1579 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1580 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1581 apic_write(APIC_ESR
, 0);
1582 v
= apic_read(APIC_ESR
);
1583 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1586 v
= apic_read(APIC_ICR
);
1587 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1588 v
= apic_read(APIC_ICR2
);
1589 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1591 v
= apic_read(APIC_LVTT
);
1592 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1594 if (maxlvt
> 3) { /* PC is LVT#4. */
1595 v
= apic_read(APIC_LVTPC
);
1596 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1598 v
= apic_read(APIC_LVT0
);
1599 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1600 v
= apic_read(APIC_LVT1
);
1601 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1603 if (maxlvt
> 2) { /* ERR is LVT#3. */
1604 v
= apic_read(APIC_LVTERR
);
1605 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1608 v
= apic_read(APIC_TMICT
);
1609 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1610 v
= apic_read(APIC_TMCCT
);
1611 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1612 v
= apic_read(APIC_TDCR
);
1613 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1617 void print_all_local_APICs (void)
1619 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1622 void /*__init*/ print_PIC(void)
1625 unsigned long flags
;
1627 if (apic_verbosity
== APIC_QUIET
)
1630 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1632 spin_lock_irqsave(&i8259A_lock
, flags
);
1634 v
= inb(0xa1) << 8 | inb(0x21);
1635 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1637 v
= inb(0xa0) << 8 | inb(0x20);
1638 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1642 v
= inb(0xa0) << 8 | inb(0x20);
1646 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1648 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1650 v
= inb(0x4d1) << 8 | inb(0x4d0);
1651 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1656 static void __init
enable_IO_APIC(void)
1658 union IO_APIC_reg_01 reg_01
;
1659 int i8259_apic
, i8259_pin
;
1661 unsigned long flags
;
1663 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1664 irq_2_pin
[i
].pin
= -1;
1665 irq_2_pin
[i
].next
= 0;
1668 for (i
= 0; i
< MAX_PIRQS
; i
++)
1669 pirq_entries
[i
] = -1;
1672 * The number of IO-APIC IRQ registers (== #pins):
1674 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1675 spin_lock_irqsave(&ioapic_lock
, flags
);
1676 reg_01
.raw
= io_apic_read(apic
, 1);
1677 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1678 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1680 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1682 /* See if any of the pins is in ExtINT mode */
1683 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1684 struct IO_APIC_route_entry entry
;
1685 entry
= ioapic_read_entry(apic
, pin
);
1688 /* If the interrupt line is enabled and in ExtInt mode
1689 * I have found the pin where the i8259 is connected.
1691 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1692 ioapic_i8259
.apic
= apic
;
1693 ioapic_i8259
.pin
= pin
;
1699 /* Look to see what if the MP table has reported the ExtINT */
1700 /* If we could not find the appropriate pin by looking at the ioapic
1701 * the i8259 probably is not connected the ioapic but give the
1702 * mptable a chance anyway.
1704 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1705 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1706 /* Trust the MP table if nothing is setup in the hardware */
1707 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1708 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1709 ioapic_i8259
.pin
= i8259_pin
;
1710 ioapic_i8259
.apic
= i8259_apic
;
1712 /* Complain if the MP table and the hardware disagree */
1713 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1714 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1716 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1720 * Do not trust the IO-APIC being empty at bootup
1726 * Not an __init, needed by the reboot code
1728 void disable_IO_APIC(void)
1731 * Clear the IO-APIC before rebooting:
1736 * If the i8259 is routed through an IOAPIC
1737 * Put that IOAPIC in virtual wire mode
1738 * so legacy interrupts can be delivered.
1740 if (ioapic_i8259
.pin
!= -1) {
1741 struct IO_APIC_route_entry entry
;
1743 memset(&entry
, 0, sizeof(entry
));
1744 entry
.mask
= 0; /* Enabled */
1745 entry
.trigger
= 0; /* Edge */
1747 entry
.polarity
= 0; /* High */
1748 entry
.delivery_status
= 0;
1749 entry
.dest_mode
= 0; /* Physical */
1750 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1752 entry
.dest
.physical
.physical_dest
=
1753 GET_APIC_ID(apic_read(APIC_ID
));
1756 * Add it to the IO-APIC irq-routing table:
1758 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1760 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1764 * function to set the IO-APIC physical IDs based on the
1765 * values stored in the MPC table.
1767 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1770 #ifndef CONFIG_X86_NUMAQ
1771 static void __init
setup_ioapic_ids_from_mpc(void)
1773 union IO_APIC_reg_00 reg_00
;
1774 physid_mask_t phys_id_present_map
;
1777 unsigned char old_id
;
1778 unsigned long flags
;
1781 * Don't check I/O APIC IDs for xAPIC systems. They have
1782 * no meaning without the serial APIC bus.
1784 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1785 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1788 * This is broken; anything with a real cpu count has to
1789 * circumvent this idiocy regardless.
1791 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1794 * Set the IOAPIC ID to the value stored in the MPC table.
1796 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1798 /* Read the register 0 value */
1799 spin_lock_irqsave(&ioapic_lock
, flags
);
1800 reg_00
.raw
= io_apic_read(apic
, 0);
1801 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1803 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1805 if (mp_ioapics
[apic
].mpc_apicid
>= get_physical_broadcast()) {
1806 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1807 apic
, mp_ioapics
[apic
].mpc_apicid
);
1808 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1810 mp_ioapics
[apic
].mpc_apicid
= reg_00
.bits
.ID
;
1814 * Sanity check, is the ID really free? Every APIC in a
1815 * system must have a unique ID or we get lots of nice
1816 * 'stuck on smp_invalidate_needed IPI wait' messages.
1818 if (check_apicid_used(phys_id_present_map
,
1819 mp_ioapics
[apic
].mpc_apicid
)) {
1820 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1821 apic
, mp_ioapics
[apic
].mpc_apicid
);
1822 for (i
= 0; i
< get_physical_broadcast(); i
++)
1823 if (!physid_isset(i
, phys_id_present_map
))
1825 if (i
>= get_physical_broadcast())
1826 panic("Max APIC ID exceeded!\n");
1827 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1829 physid_set(i
, phys_id_present_map
);
1830 mp_ioapics
[apic
].mpc_apicid
= i
;
1833 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mpc_apicid
);
1834 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1835 "phys_id_present_map\n",
1836 mp_ioapics
[apic
].mpc_apicid
);
1837 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1842 * We need to adjust the IRQ routing table
1843 * if the ID changed.
1845 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1846 for (i
= 0; i
< mp_irq_entries
; i
++)
1847 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1848 mp_irqs
[i
].mpc_dstapic
1849 = mp_ioapics
[apic
].mpc_apicid
;
1852 * Read the right value from the MPC table and
1853 * write it into the ID register.
1855 apic_printk(APIC_VERBOSE
, KERN_INFO
1856 "...changing IO-APIC physical APIC ID to %d ...",
1857 mp_ioapics
[apic
].mpc_apicid
);
1859 reg_00
.bits
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1860 spin_lock_irqsave(&ioapic_lock
, flags
);
1861 io_apic_write(apic
, 0, reg_00
.raw
);
1862 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1867 spin_lock_irqsave(&ioapic_lock
, flags
);
1868 reg_00
.raw
= io_apic_read(apic
, 0);
1869 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1870 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1871 printk("could not set ID!\n");
1873 apic_printk(APIC_VERBOSE
, " ok.\n");
1877 static void __init
setup_ioapic_ids_from_mpc(void) { }
1881 * There is a nasty bug in some older SMP boards, their mptable lies
1882 * about the timer IRQ. We do the following to work around the situation:
1884 * - timer IRQ defaults to IO-APIC IRQ
1885 * - if this function detects that timer IRQs are defunct, then we fall
1886 * back to ISA timer IRQs
1888 static int __init
timer_irq_works(void)
1890 unsigned long t1
= jiffies
;
1893 /* Let ten ticks pass... */
1894 mdelay((10 * 1000) / HZ
);
1897 * Expect a few ticks at least, to be sure some possible
1898 * glue logic does not lock up after one or two first
1899 * ticks in a non-ExtINT mode. Also the local APIC
1900 * might have cached one ExtINT interrupt. Finally, at
1901 * least one tick may be lost due to delays.
1903 if (jiffies
- t1
> 4)
1910 * In the SMP+IOAPIC case it might happen that there are an unspecified
1911 * number of pending IRQ events unhandled. These cases are very rare,
1912 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1913 * better to do it this way as thus we do not have to be aware of
1914 * 'pending' interrupts in the IRQ path, except at this point.
1917 * Edge triggered needs to resend any interrupt
1918 * that was delayed but this is now handled in the device
1925 * Starting up a edge-triggered IO-APIC interrupt is
1926 * nasty - we need to make sure that we get the edge.
1927 * If it is already asserted for some reason, we need
1928 * return 1 to indicate that is was pending.
1930 * This is not complete - we should be able to fake
1931 * an edge even if it isn't on the 8259A...
1933 * (We do this for level-triggered IRQs too - it cannot hurt.)
1935 static unsigned int startup_ioapic_irq(unsigned int irq
)
1937 int was_pending
= 0;
1938 unsigned long flags
;
1940 spin_lock_irqsave(&ioapic_lock
, flags
);
1942 disable_8259A_irq(irq
);
1943 if (i8259A_irq_pending(irq
))
1946 __unmask_IO_APIC_irq(irq
);
1947 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1952 static void ack_ioapic_irq(unsigned int irq
)
1958 static void ack_ioapic_quirk_irq(unsigned int irq
)
1965 * It appears there is an erratum which affects at least version 0x11
1966 * of I/O APIC (that's the 82093AA and cores integrated into various
1967 * chipsets). Under certain conditions a level-triggered interrupt is
1968 * erroneously delivered as edge-triggered one but the respective IRR
1969 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1970 * message but it will never arrive and further interrupts are blocked
1971 * from the source. The exact reason is so far unknown, but the
1972 * phenomenon was observed when two consecutive interrupt requests
1973 * from a given source get delivered to the same CPU and the source is
1974 * temporarily disabled in between.
1976 * A workaround is to simulate an EOI message manually. We achieve it
1977 * by setting the trigger mode to edge and then to level when the edge
1978 * trigger mode gets detected in the TMR of a local APIC for a
1979 * level-triggered interrupt. We mask the source for the time of the
1980 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1981 * The idea is from Manfred Spraul. --macro
1983 i
= IO_APIC_VECTOR(irq
);
1985 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1989 if (!(v
& (1 << (i
& 0x1f)))) {
1990 atomic_inc(&irq_mis_count
);
1991 spin_lock(&ioapic_lock
);
1992 __mask_and_edge_IO_APIC_irq(irq
);
1993 __unmask_and_level_IO_APIC_irq(irq
);
1994 spin_unlock(&ioapic_lock
);
1998 static unsigned int startup_ioapic_vector(unsigned int vector
)
2000 int irq
= vector_to_irq(vector
);
2002 return startup_ioapic_irq(irq
);
2005 static void ack_ioapic_vector(unsigned int vector
)
2007 int irq
= vector_to_irq(vector
);
2009 move_native_irq(vector
);
2010 ack_ioapic_irq(irq
);
2013 static void ack_ioapic_quirk_vector(unsigned int vector
)
2015 int irq
= vector_to_irq(vector
);
2017 move_native_irq(vector
);
2018 ack_ioapic_quirk_irq(irq
);
2021 static void mask_IO_APIC_vector (unsigned int vector
)
2023 int irq
= vector_to_irq(vector
);
2025 mask_IO_APIC_irq(irq
);
2028 static void unmask_IO_APIC_vector (unsigned int vector
)
2030 int irq
= vector_to_irq(vector
);
2032 unmask_IO_APIC_irq(irq
);
2036 * Oh just glorious. If CONFIG_PCI_MSI we've done
2037 * #define set_ioapic_affinity set_ioapic_affinity_vector
2039 #if defined (CONFIG_SMP) && defined(CONFIG_X86_IO_APIC) && \
2040 defined(CONFIG_PCI_MSI)
2041 static void set_ioapic_affinity_vector (unsigned int vector
,
2044 int irq
= vector_to_irq(vector
);
2046 set_native_irq_info(vector
, cpu_mask
);
2047 set_ioapic_affinity_irq(irq
, cpu_mask
);
2051 static int ioapic_retrigger_vector(unsigned int vector
)
2053 int irq
= vector_to_irq(vector
);
2055 send_IPI_self(IO_APIC_VECTOR(irq
));
2060 static struct irq_chip ioapic_chip __read_mostly
= {
2062 .startup
= startup_ioapic_vector
,
2063 .mask
= mask_IO_APIC_vector
,
2064 .unmask
= unmask_IO_APIC_vector
,
2065 .ack
= ack_ioapic_vector
,
2066 .eoi
= ack_ioapic_quirk_vector
,
2068 .set_affinity
= set_ioapic_affinity
,
2070 .retrigger
= ioapic_retrigger_vector
,
2074 static inline void init_IO_APIC_traps(void)
2079 * NOTE! The local APIC isn't very good at handling
2080 * multiple interrupts at the same interrupt level.
2081 * As the interrupt level is determined by taking the
2082 * vector number and shifting that right by 4, we
2083 * want to spread these out a bit so that they don't
2084 * all fall in the same interrupt level.
2086 * Also, we've got to be careful not to trash gate
2087 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2089 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
2091 if (use_pci_vector()) {
2092 if (!platform_legacy_irq(tmp
))
2093 if ((tmp
= vector_to_irq(tmp
)) == -1)
2096 if (IO_APIC_IRQ(tmp
) && !IO_APIC_VECTOR(tmp
)) {
2098 * Hmm.. We don't have an entry for this,
2099 * so default to an old-fashioned 8259
2100 * interrupt if we can..
2103 make_8259A_irq(irq
);
2105 /* Strange. Oh, well.. */
2106 irq_desc
[irq
].chip
= &no_irq_chip
;
2112 * The local APIC irq-chip implementation:
2115 static void ack_apic(unsigned int irq
)
2120 static void mask_lapic_irq (unsigned int irq
)
2124 v
= apic_read(APIC_LVT0
);
2125 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2128 static void unmask_lapic_irq (unsigned int irq
)
2132 v
= apic_read(APIC_LVT0
);
2133 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2136 static struct irq_chip lapic_chip __read_mostly
= {
2137 .name
= "local-APIC-edge",
2138 .mask
= mask_lapic_irq
,
2139 .unmask
= unmask_lapic_irq
,
2143 static void setup_nmi (void)
2146 * Dirty trick to enable the NMI watchdog ...
2147 * We put the 8259A master into AEOI mode and
2148 * unmask on all local APICs LVT0 as NMI.
2150 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2151 * is from Maciej W. Rozycki - so we do not have to EOI from
2152 * the NMI handler or the timer interrupt.
2154 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2156 on_each_cpu(enable_NMI_through_LVT0
, NULL
, 1, 1);
2158 apic_printk(APIC_VERBOSE
, " done.\n");
2162 * This looks a bit hackish but it's about the only one way of sending
2163 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2164 * not support the ExtINT mode, unfortunately. We need to send these
2165 * cycles as some i82489DX-based boards have glue logic that keeps the
2166 * 8259A interrupt line asserted until INTA. --macro
2168 static inline void unlock_ExtINT_logic(void)
2171 struct IO_APIC_route_entry entry0
, entry1
;
2172 unsigned char save_control
, save_freq_select
;
2174 pin
= find_isa_irq_pin(8, mp_INT
);
2175 apic
= find_isa_irq_apic(8, mp_INT
);
2179 entry0
= ioapic_read_entry(apic
, pin
);
2180 clear_IO_APIC_pin(apic
, pin
);
2182 memset(&entry1
, 0, sizeof(entry1
));
2184 entry1
.dest_mode
= 0; /* physical delivery */
2185 entry1
.mask
= 0; /* unmask IRQ now */
2186 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2187 entry1
.delivery_mode
= dest_ExtINT
;
2188 entry1
.polarity
= entry0
.polarity
;
2192 ioapic_write_entry(apic
, pin
, entry1
);
2194 save_control
= CMOS_READ(RTC_CONTROL
);
2195 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2196 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2198 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2203 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2207 CMOS_WRITE(save_control
, RTC_CONTROL
);
2208 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2209 clear_IO_APIC_pin(apic
, pin
);
2211 ioapic_write_entry(apic
, pin
, entry0
);
2214 int timer_uses_ioapic_pin_0
;
2217 * This code may look a bit paranoid, but it's supposed to cooperate with
2218 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2219 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2220 * fanatically on his truly buggy board.
2222 static inline void check_timer(void)
2224 int apic1
, pin1
, apic2
, pin2
;
2228 * get/set the timer IRQ vector:
2230 disable_8259A_irq(0);
2231 vector
= assign_irq_vector(0);
2232 set_intr_gate(vector
, interrupt
[0]);
2235 * Subtle, code in do_timer_interrupt() expects an AEOI
2236 * mode for the 8259A whenever interrupts are routed
2237 * through I/O APICs. Also IRQ0 has to be enabled in
2238 * the 8259A which implies the virtual wire has to be
2239 * disabled in the local APIC.
2241 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2244 if (timer_over_8254
> 0)
2245 enable_8259A_irq(0);
2247 pin1
= find_isa_irq_pin(0, mp_INT
);
2248 apic1
= find_isa_irq_apic(0, mp_INT
);
2249 pin2
= ioapic_i8259
.pin
;
2250 apic2
= ioapic_i8259
.apic
;
2253 timer_uses_ioapic_pin_0
= 1;
2255 printk(KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2256 vector
, apic1
, pin1
, apic2
, pin2
);
2260 * Ok, does IRQ0 through the IOAPIC work?
2262 unmask_IO_APIC_irq(0);
2263 if (timer_irq_works()) {
2264 if (nmi_watchdog
== NMI_IO_APIC
) {
2265 disable_8259A_irq(0);
2267 enable_8259A_irq(0);
2269 if (disable_timer_pin_1
> 0)
2270 clear_IO_APIC_pin(0, pin1
);
2273 clear_IO_APIC_pin(apic1
, pin1
);
2274 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to "
2278 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
2280 printk("\n..... (found pin %d) ...", pin2
);
2282 * legacy devices should be connected to IO APIC #0
2284 setup_ExtINT_IRQ0_pin(apic2
, pin2
, vector
);
2285 if (timer_irq_works()) {
2288 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2290 add_pin_to_irq(0, apic2
, pin2
);
2291 if (nmi_watchdog
== NMI_IO_APIC
) {
2297 * Cleanup, just in case ...
2299 clear_IO_APIC_pin(apic2
, pin2
);
2301 printk(" failed.\n");
2303 if (nmi_watchdog
== NMI_IO_APIC
) {
2304 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2308 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
2310 disable_8259A_irq(0);
2311 set_irq_chip_and_handler(0, &lapic_chip
, handle_fasteoi_irq
);
2312 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2313 enable_8259A_irq(0);
2315 if (timer_irq_works()) {
2316 printk(" works.\n");
2319 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2320 printk(" failed.\n");
2322 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
2327 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
2329 unlock_ExtINT_logic();
2331 if (timer_irq_works()) {
2332 printk(" works.\n");
2335 printk(" failed :(.\n");
2336 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2337 "report. Then try booting with the 'noapic' option");
2342 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2343 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2344 * Linux doesn't really care, as it's not actually used
2345 * for any interrupt handling anyway.
2347 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2349 void __init
setup_IO_APIC(void)
2354 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
2356 io_apic_irqs
= ~PIC_IRQS
;
2358 printk("ENABLING IO-APIC IRQs\n");
2361 * Set up IO-APIC IRQ routing.
2364 setup_ioapic_ids_from_mpc();
2366 setup_IO_APIC_irqs();
2367 init_IO_APIC_traps();
2373 static int __init
setup_disable_8254_timer(char *s
)
2375 timer_over_8254
= -1;
2378 static int __init
setup_enable_8254_timer(char *s
)
2380 timer_over_8254
= 2;
2384 __setup("disable_8254_timer", setup_disable_8254_timer
);
2385 __setup("enable_8254_timer", setup_enable_8254_timer
);
2388 * Called after all the initialization is done. If we didnt find any
2389 * APIC bugs then we can allow the modify fast path
2392 static int __init
io_apic_bug_finalize(void)
2394 if(sis_apic_bug
== -1)
2399 late_initcall(io_apic_bug_finalize
);
2401 struct sysfs_ioapic_data
{
2402 struct sys_device dev
;
2403 struct IO_APIC_route_entry entry
[0];
2405 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2407 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2409 struct IO_APIC_route_entry
*entry
;
2410 struct sysfs_ioapic_data
*data
;
2413 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2414 entry
= data
->entry
;
2415 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2416 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2421 static int ioapic_resume(struct sys_device
*dev
)
2423 struct IO_APIC_route_entry
*entry
;
2424 struct sysfs_ioapic_data
*data
;
2425 unsigned long flags
;
2426 union IO_APIC_reg_00 reg_00
;
2429 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2430 entry
= data
->entry
;
2432 spin_lock_irqsave(&ioapic_lock
, flags
);
2433 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2434 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
2435 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
2436 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2438 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2439 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2440 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2445 static struct sysdev_class ioapic_sysdev_class
= {
2446 set_kset_name("ioapic"),
2447 .suspend
= ioapic_suspend
,
2448 .resume
= ioapic_resume
,
2451 static int __init
ioapic_init_sysfs(void)
2453 struct sys_device
* dev
;
2454 int i
, size
, error
= 0;
2456 error
= sysdev_class_register(&ioapic_sysdev_class
);
2460 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2461 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2462 * sizeof(struct IO_APIC_route_entry
);
2463 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
2464 if (!mp_ioapic_data
[i
]) {
2465 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2468 memset(mp_ioapic_data
[i
], 0, size
);
2469 dev
= &mp_ioapic_data
[i
]->dev
;
2471 dev
->cls
= &ioapic_sysdev_class
;
2472 error
= sysdev_register(dev
);
2474 kfree(mp_ioapic_data
[i
]);
2475 mp_ioapic_data
[i
] = NULL
;
2476 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2484 device_initcall(ioapic_init_sysfs
);
2486 /* --------------------------------------------------------------------------
2487 ACPI-based IOAPIC Configuration
2488 -------------------------------------------------------------------------- */
2492 int __init
io_apic_get_unique_id (int ioapic
, int apic_id
)
2494 union IO_APIC_reg_00 reg_00
;
2495 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2497 unsigned long flags
;
2501 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2502 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2503 * supports up to 16 on one shared APIC bus.
2505 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2506 * advantage of new APIC bus architecture.
2509 if (physids_empty(apic_id_map
))
2510 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2512 spin_lock_irqsave(&ioapic_lock
, flags
);
2513 reg_00
.raw
= io_apic_read(ioapic
, 0);
2514 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2516 if (apic_id
>= get_physical_broadcast()) {
2517 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2518 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2519 apic_id
= reg_00
.bits
.ID
;
2523 * Every APIC in a system must have a unique ID or we get lots of nice
2524 * 'stuck on smp_invalidate_needed IPI wait' messages.
2526 if (check_apicid_used(apic_id_map
, apic_id
)) {
2528 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2529 if (!check_apicid_used(apic_id_map
, i
))
2533 if (i
== get_physical_broadcast())
2534 panic("Max apic_id exceeded!\n");
2536 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2537 "trying %d\n", ioapic
, apic_id
, i
);
2542 tmp
= apicid_to_cpu_present(apic_id
);
2543 physids_or(apic_id_map
, apic_id_map
, tmp
);
2545 if (reg_00
.bits
.ID
!= apic_id
) {
2546 reg_00
.bits
.ID
= apic_id
;
2548 spin_lock_irqsave(&ioapic_lock
, flags
);
2549 io_apic_write(ioapic
, 0, reg_00
.raw
);
2550 reg_00
.raw
= io_apic_read(ioapic
, 0);
2551 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2554 if (reg_00
.bits
.ID
!= apic_id
) {
2555 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2560 apic_printk(APIC_VERBOSE
, KERN_INFO
2561 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2567 int __init
io_apic_get_version (int ioapic
)
2569 union IO_APIC_reg_01 reg_01
;
2570 unsigned long flags
;
2572 spin_lock_irqsave(&ioapic_lock
, flags
);
2573 reg_01
.raw
= io_apic_read(ioapic
, 1);
2574 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2576 return reg_01
.bits
.version
;
2580 int __init
io_apic_get_redir_entries (int ioapic
)
2582 union IO_APIC_reg_01 reg_01
;
2583 unsigned long flags
;
2585 spin_lock_irqsave(&ioapic_lock
, flags
);
2586 reg_01
.raw
= io_apic_read(ioapic
, 1);
2587 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2589 return reg_01
.bits
.entries
;
2593 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2595 struct IO_APIC_route_entry entry
;
2596 unsigned long flags
;
2598 if (!IO_APIC_IRQ(irq
)) {
2599 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2605 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2606 * Note that we mask (disable) IRQs now -- these get enabled when the
2607 * corresponding device driver registers for this IRQ.
2610 memset(&entry
,0,sizeof(entry
));
2612 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2613 entry
.dest_mode
= INT_DEST_MODE
;
2614 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2615 entry
.trigger
= edge_level
;
2616 entry
.polarity
= active_high_low
;
2620 * IRQs < 16 are already in the irq_2_pin[] map
2623 add_pin_to_irq(irq
, ioapic
, pin
);
2625 entry
.vector
= assign_irq_vector(irq
);
2627 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2628 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2629 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
,
2630 edge_level
, active_high_low
);
2632 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2634 if (!ioapic
&& (irq
< 16))
2635 disable_8259A_irq(irq
);
2637 ioapic_write_entry(ioapic
, pin
, entry
);
2638 spin_lock_irqsave(&ioapic_lock
, flags
);
2639 set_native_irq_info(use_pci_vector() ? entry
.vector
: irq
, TARGET_CPUS
);
2640 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2645 #endif /* CONFIG_ACPI */
2647 static int __init
parse_disable_timer_pin_1(char *arg
)
2649 disable_timer_pin_1
= 1;
2652 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2654 static int __init
parse_enable_timer_pin_1(char *arg
)
2656 disable_timer_pin_1
= -1;
2659 early_param("enable_timer_pin_1", parse_enable_timer_pin_1
);
2661 static int __init
parse_noapic(char *arg
)
2663 /* disable IO-APIC */
2664 disable_ioapic_setup();
2667 early_param("noapic", parse_noapic
);