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1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 *
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
9 *
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
13 *
14 * This code is released under the GNU General Public License version 2 or
15 * later.
16 *
17 * Fixes
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
28 * from Jose Renau
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
35
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/kernel.h>
39
40 #include <linux/mm.h>
41 #include <linux/sched.h>
42 #include <linux/kernel_stat.h>
43 #include <linux/smp_lock.h>
44 #include <linux/bootmem.h>
45 #include <linux/notifier.h>
46 #include <linux/cpu.h>
47 #include <linux/percpu.h>
48 #include <linux/nmi.h>
49
50 #include <linux/delay.h>
51 #include <linux/mc146818rtc.h>
52 #include <asm/tlbflush.h>
53 #include <asm/desc.h>
54 #include <asm/arch_hooks.h>
55 #include <asm/nmi.h>
56 #include <asm/pda.h>
57
58 #include <mach_apic.h>
59 #include <mach_wakecpu.h>
60 #include <smpboot_hooks.h>
61 #include <asm/vmi.h>
62
63 /* Set if we find a B stepping CPU */
64 static int __devinitdata smp_b_stepping;
65
66 /* Number of siblings per CPU package */
67 int smp_num_siblings = 1;
68 EXPORT_SYMBOL(smp_num_siblings);
69
70 /* Last level cache ID of each logical CPU */
71 int cpu_llc_id[NR_CPUS] __cpuinitdata = {[0 ... NR_CPUS-1] = BAD_APICID};
72
73 /* representing HT siblings of each logical CPU */
74 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
75 EXPORT_SYMBOL(cpu_sibling_map);
76
77 /* representing HT and core siblings of each logical CPU */
78 cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
79 EXPORT_SYMBOL(cpu_core_map);
80
81 /* bitmap of online cpus */
82 cpumask_t cpu_online_map __read_mostly;
83 EXPORT_SYMBOL(cpu_online_map);
84
85 cpumask_t cpu_callin_map;
86 cpumask_t cpu_callout_map;
87 EXPORT_SYMBOL(cpu_callout_map);
88 cpumask_t cpu_possible_map;
89 EXPORT_SYMBOL(cpu_possible_map);
90 static cpumask_t smp_commenced_mask;
91
92 /* Per CPU bogomips and other parameters */
93 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
94 EXPORT_SYMBOL(cpu_data);
95
96 u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
97 { [0 ... NR_CPUS-1] = 0xff };
98 EXPORT_SYMBOL(x86_cpu_to_apicid);
99
100 u8 apicid_2_node[MAX_APICID];
101
102 /*
103 * Trampoline 80x86 program as an array.
104 */
105
106 extern unsigned char trampoline_data [];
107 extern unsigned char trampoline_end [];
108 static unsigned char *trampoline_base;
109 static int trampoline_exec;
110
111 static void map_cpu_to_logical_apicid(void);
112
113 /* State of each CPU. */
114 DEFINE_PER_CPU(int, cpu_state) = { 0 };
115
116 /*
117 * Currently trivial. Write the real->protected mode
118 * bootstrap into the page concerned. The caller
119 * has made sure it's suitably aligned.
120 */
121
122 static unsigned long __devinit setup_trampoline(void)
123 {
124 memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data);
125 return virt_to_phys(trampoline_base);
126 }
127
128 /*
129 * We are called very early to get the low memory for the
130 * SMP bootup trampoline page.
131 */
132 void __init smp_alloc_memory(void)
133 {
134 trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE);
135 /*
136 * Has to be in very low memory so we can execute
137 * real-mode AP code.
138 */
139 if (__pa(trampoline_base) >= 0x9F000)
140 BUG();
141 /*
142 * Make the SMP trampoline executable:
143 */
144 trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1);
145 }
146
147 /*
148 * The bootstrap kernel entry code has set these up. Save them for
149 * a given CPU
150 */
151
152 static void __cpuinit smp_store_cpu_info(int id)
153 {
154 struct cpuinfo_x86 *c = cpu_data + id;
155
156 *c = boot_cpu_data;
157 if (id!=0)
158 identify_secondary_cpu(c);
159 /*
160 * Mask B, Pentium, but not Pentium MMX
161 */
162 if (c->x86_vendor == X86_VENDOR_INTEL &&
163 c->x86 == 5 &&
164 c->x86_mask >= 1 && c->x86_mask <= 4 &&
165 c->x86_model <= 3)
166 /*
167 * Remember we have B step Pentia with bugs
168 */
169 smp_b_stepping = 1;
170
171 /*
172 * Certain Athlons might work (for various values of 'work') in SMP
173 * but they are not certified as MP capable.
174 */
175 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
176
177 if (num_possible_cpus() == 1)
178 goto valid_k7;
179
180 /* Athlon 660/661 is valid. */
181 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
182 goto valid_k7;
183
184 /* Duron 670 is valid */
185 if ((c->x86_model==7) && (c->x86_mask==0))
186 goto valid_k7;
187
188 /*
189 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
190 * It's worth noting that the A5 stepping (662) of some Athlon XP's
191 * have the MP bit set.
192 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
193 */
194 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
195 ((c->x86_model==7) && (c->x86_mask>=1)) ||
196 (c->x86_model> 7))
197 if (cpu_has_mp)
198 goto valid_k7;
199
200 /* If we get here, it's not a certified SMP capable AMD system. */
201 add_taint(TAINT_UNSAFE_SMP);
202 }
203
204 valid_k7:
205 ;
206 }
207
208 extern void calibrate_delay(void);
209
210 static atomic_t init_deasserted;
211
212 static void __cpuinit smp_callin(void)
213 {
214 int cpuid, phys_id;
215 unsigned long timeout;
216
217 /*
218 * If waken up by an INIT in an 82489DX configuration
219 * we may get here before an INIT-deassert IPI reaches
220 * our local APIC. We have to wait for the IPI or we'll
221 * lock up on an APIC access.
222 */
223 wait_for_init_deassert(&init_deasserted);
224
225 /*
226 * (This works even if the APIC is not enabled.)
227 */
228 phys_id = GET_APIC_ID(apic_read(APIC_ID));
229 cpuid = smp_processor_id();
230 if (cpu_isset(cpuid, cpu_callin_map)) {
231 printk("huh, phys CPU#%d, CPU#%d already present??\n",
232 phys_id, cpuid);
233 BUG();
234 }
235 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
236
237 /*
238 * STARTUP IPIs are fragile beasts as they might sometimes
239 * trigger some glue motherboard logic. Complete APIC bus
240 * silence for 1 second, this overestimates the time the
241 * boot CPU is spending to send the up to 2 STARTUP IPIs
242 * by a factor of two. This should be enough.
243 */
244
245 /*
246 * Waiting 2s total for startup (udelay is not yet working)
247 */
248 timeout = jiffies + 2*HZ;
249 while (time_before(jiffies, timeout)) {
250 /*
251 * Has the boot CPU finished it's STARTUP sequence?
252 */
253 if (cpu_isset(cpuid, cpu_callout_map))
254 break;
255 rep_nop();
256 }
257
258 if (!time_before(jiffies, timeout)) {
259 printk("BUG: CPU%d started up but did not get a callout!\n",
260 cpuid);
261 BUG();
262 }
263
264 /*
265 * the boot CPU has finished the init stage and is spinning
266 * on callin_map until we finish. We are free to set up this
267 * CPU, first the APIC. (this is probably redundant on most
268 * boards)
269 */
270
271 Dprintk("CALLIN, before setup_local_APIC().\n");
272 smp_callin_clear_local_apic();
273 setup_local_APIC();
274 map_cpu_to_logical_apicid();
275
276 /*
277 * Get our bogomips.
278 */
279 calibrate_delay();
280 Dprintk("Stack at about %p\n",&cpuid);
281
282 /*
283 * Save our processor parameters
284 */
285 smp_store_cpu_info(cpuid);
286
287 /*
288 * Allow the master to continue.
289 */
290 cpu_set(cpuid, cpu_callin_map);
291 }
292
293 static int cpucount;
294
295 /* maps the cpu to the sched domain representing multi-core */
296 cpumask_t cpu_coregroup_map(int cpu)
297 {
298 struct cpuinfo_x86 *c = cpu_data + cpu;
299 /*
300 * For perf, we return last level cache shared map.
301 * And for power savings, we return cpu_core_map
302 */
303 if (sched_mc_power_savings || sched_smt_power_savings)
304 return cpu_core_map[cpu];
305 else
306 return c->llc_shared_map;
307 }
308
309 /* representing cpus for which sibling maps can be computed */
310 static cpumask_t cpu_sibling_setup_map;
311
312 static inline void
313 set_cpu_sibling_map(int cpu)
314 {
315 int i;
316 struct cpuinfo_x86 *c = cpu_data;
317
318 cpu_set(cpu, cpu_sibling_setup_map);
319
320 if (smp_num_siblings > 1) {
321 for_each_cpu_mask(i, cpu_sibling_setup_map) {
322 if (c[cpu].phys_proc_id == c[i].phys_proc_id &&
323 c[cpu].cpu_core_id == c[i].cpu_core_id) {
324 cpu_set(i, cpu_sibling_map[cpu]);
325 cpu_set(cpu, cpu_sibling_map[i]);
326 cpu_set(i, cpu_core_map[cpu]);
327 cpu_set(cpu, cpu_core_map[i]);
328 cpu_set(i, c[cpu].llc_shared_map);
329 cpu_set(cpu, c[i].llc_shared_map);
330 }
331 }
332 } else {
333 cpu_set(cpu, cpu_sibling_map[cpu]);
334 }
335
336 cpu_set(cpu, c[cpu].llc_shared_map);
337
338 if (current_cpu_data.x86_max_cores == 1) {
339 cpu_core_map[cpu] = cpu_sibling_map[cpu];
340 c[cpu].booted_cores = 1;
341 return;
342 }
343
344 for_each_cpu_mask(i, cpu_sibling_setup_map) {
345 if (cpu_llc_id[cpu] != BAD_APICID &&
346 cpu_llc_id[cpu] == cpu_llc_id[i]) {
347 cpu_set(i, c[cpu].llc_shared_map);
348 cpu_set(cpu, c[i].llc_shared_map);
349 }
350 if (c[cpu].phys_proc_id == c[i].phys_proc_id) {
351 cpu_set(i, cpu_core_map[cpu]);
352 cpu_set(cpu, cpu_core_map[i]);
353 /*
354 * Does this new cpu bringup a new core?
355 */
356 if (cpus_weight(cpu_sibling_map[cpu]) == 1) {
357 /*
358 * for each core in package, increment
359 * the booted_cores for this new cpu
360 */
361 if (first_cpu(cpu_sibling_map[i]) == i)
362 c[cpu].booted_cores++;
363 /*
364 * increment the core count for all
365 * the other cpus in this package
366 */
367 if (i != cpu)
368 c[i].booted_cores++;
369 } else if (i != cpu && !c[cpu].booted_cores)
370 c[cpu].booted_cores = c[i].booted_cores;
371 }
372 }
373 }
374
375 /*
376 * Activate a secondary processor.
377 */
378 static void __cpuinit start_secondary(void *unused)
379 {
380 /*
381 * Don't put *anything* before cpu_init(), SMP booting is too
382 * fragile that we want to limit the things done here to the
383 * most necessary things.
384 */
385 #ifdef CONFIG_VMI
386 vmi_bringup();
387 #endif
388 cpu_init();
389 preempt_disable();
390 smp_callin();
391 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
392 rep_nop();
393 /*
394 * Check TSC synchronization with the BP:
395 */
396 check_tsc_sync_target();
397
398 setup_secondary_clock();
399 if (nmi_watchdog == NMI_IO_APIC) {
400 disable_8259A_irq(0);
401 enable_NMI_through_LVT0(NULL);
402 enable_8259A_irq(0);
403 }
404 /*
405 * low-memory mappings have been cleared, flush them from
406 * the local TLBs too.
407 */
408 local_flush_tlb();
409
410 /* This must be done before setting cpu_online_map */
411 set_cpu_sibling_map(raw_smp_processor_id());
412 wmb();
413
414 /*
415 * We need to hold call_lock, so there is no inconsistency
416 * between the time smp_call_function() determines number of
417 * IPI receipients, and the time when the determination is made
418 * for which cpus receive the IPI. Holding this
419 * lock helps us to not include this cpu in a currently in progress
420 * smp_call_function().
421 */
422 lock_ipi_call_lock();
423 cpu_set(smp_processor_id(), cpu_online_map);
424 unlock_ipi_call_lock();
425 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
426
427 /* We can take interrupts now: we're officially "up". */
428 local_irq_enable();
429
430 wmb();
431 cpu_idle();
432 }
433
434 /*
435 * Everything has been set up for the secondary
436 * CPUs - they just need to reload everything
437 * from the task structure
438 * This function must not return.
439 */
440 void __devinit initialize_secondary(void)
441 {
442 /*
443 * We don't actually need to load the full TSS,
444 * basically just the stack pointer and the eip.
445 */
446
447 asm volatile(
448 "movl %0,%%esp\n\t"
449 "jmp *%1"
450 :
451 :"m" (current->thread.esp),"m" (current->thread.eip));
452 }
453
454 /* Static state in head.S used to set up a CPU */
455 extern struct {
456 void * esp;
457 unsigned short ss;
458 } stack_start;
459 extern struct i386_pda *start_pda;
460
461 #ifdef CONFIG_NUMA
462
463 /* which logical CPUs are on which nodes */
464 cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly =
465 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
466 EXPORT_SYMBOL(node_2_cpu_mask);
467 /* which node each logical CPU is on */
468 int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
469 EXPORT_SYMBOL(cpu_2_node);
470
471 /* set up a mapping between cpu and node. */
472 static inline void map_cpu_to_node(int cpu, int node)
473 {
474 printk("Mapping cpu %d to node %d\n", cpu, node);
475 cpu_set(cpu, node_2_cpu_mask[node]);
476 cpu_2_node[cpu] = node;
477 }
478
479 /* undo a mapping between cpu and node. */
480 static inline void unmap_cpu_to_node(int cpu)
481 {
482 int node;
483
484 printk("Unmapping cpu %d from all nodes\n", cpu);
485 for (node = 0; node < MAX_NUMNODES; node ++)
486 cpu_clear(cpu, node_2_cpu_mask[node]);
487 cpu_2_node[cpu] = 0;
488 }
489 #else /* !CONFIG_NUMA */
490
491 #define map_cpu_to_node(cpu, node) ({})
492 #define unmap_cpu_to_node(cpu) ({})
493
494 #endif /* CONFIG_NUMA */
495
496 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
497
498 static void map_cpu_to_logical_apicid(void)
499 {
500 int cpu = smp_processor_id();
501 int apicid = logical_smp_processor_id();
502 int node = apicid_to_node(apicid);
503
504 if (!node_online(node))
505 node = first_online_node;
506
507 cpu_2_logical_apicid[cpu] = apicid;
508 map_cpu_to_node(cpu, node);
509 }
510
511 static void unmap_cpu_to_logical_apicid(int cpu)
512 {
513 cpu_2_logical_apicid[cpu] = BAD_APICID;
514 unmap_cpu_to_node(cpu);
515 }
516
517 #if APIC_DEBUG
518 static inline void __inquire_remote_apic(int apicid)
519 {
520 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
521 char *names[] = { "ID", "VERSION", "SPIV" };
522 int timeout, status;
523
524 printk("Inquiring remote APIC #%d...\n", apicid);
525
526 for (i = 0; i < ARRAY_SIZE(regs); i++) {
527 printk("... APIC #%d %s: ", apicid, names[i]);
528
529 /*
530 * Wait for idle.
531 */
532 apic_wait_icr_idle();
533
534 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
535 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
536
537 timeout = 0;
538 do {
539 udelay(100);
540 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
541 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
542
543 switch (status) {
544 case APIC_ICR_RR_VALID:
545 status = apic_read(APIC_RRR);
546 printk("%08x\n", status);
547 break;
548 default:
549 printk("failed\n");
550 }
551 }
552 }
553 #endif
554
555 #ifdef WAKE_SECONDARY_VIA_NMI
556 /*
557 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
558 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
559 * won't ... remember to clear down the APIC, etc later.
560 */
561 static int __devinit
562 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
563 {
564 unsigned long send_status = 0, accept_status = 0;
565 int timeout, maxlvt;
566
567 /* Target chip */
568 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
569
570 /* Boot on the stack */
571 /* Kick the second */
572 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
573
574 Dprintk("Waiting for send to finish...\n");
575 timeout = 0;
576 do {
577 Dprintk("+");
578 udelay(100);
579 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
580 } while (send_status && (timeout++ < 1000));
581
582 /*
583 * Give the other CPU some time to accept the IPI.
584 */
585 udelay(200);
586 /*
587 * Due to the Pentium erratum 3AP.
588 */
589 maxlvt = lapic_get_maxlvt();
590 if (maxlvt > 3) {
591 apic_read_around(APIC_SPIV);
592 apic_write(APIC_ESR, 0);
593 }
594 accept_status = (apic_read(APIC_ESR) & 0xEF);
595 Dprintk("NMI sent.\n");
596
597 if (send_status)
598 printk("APIC never delivered???\n");
599 if (accept_status)
600 printk("APIC delivery error (%lx).\n", accept_status);
601
602 return (send_status | accept_status);
603 }
604 #endif /* WAKE_SECONDARY_VIA_NMI */
605
606 #ifdef WAKE_SECONDARY_VIA_INIT
607 static int __devinit
608 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
609 {
610 unsigned long send_status = 0, accept_status = 0;
611 int maxlvt, timeout, num_starts, j;
612
613 /*
614 * Be paranoid about clearing APIC errors.
615 */
616 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
617 apic_read_around(APIC_SPIV);
618 apic_write(APIC_ESR, 0);
619 apic_read(APIC_ESR);
620 }
621
622 Dprintk("Asserting INIT.\n");
623
624 /*
625 * Turn INIT on target chip
626 */
627 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
628
629 /*
630 * Send IPI
631 */
632 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
633 | APIC_DM_INIT);
634
635 Dprintk("Waiting for send to finish...\n");
636 timeout = 0;
637 do {
638 Dprintk("+");
639 udelay(100);
640 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
641 } while (send_status && (timeout++ < 1000));
642
643 mdelay(10);
644
645 Dprintk("Deasserting INIT.\n");
646
647 /* Target chip */
648 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
649
650 /* Send IPI */
651 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
652
653 Dprintk("Waiting for send to finish...\n");
654 timeout = 0;
655 do {
656 Dprintk("+");
657 udelay(100);
658 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
659 } while (send_status && (timeout++ < 1000));
660
661 atomic_set(&init_deasserted, 1);
662
663 /*
664 * Should we send STARTUP IPIs ?
665 *
666 * Determine this based on the APIC version.
667 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
668 */
669 if (APIC_INTEGRATED(apic_version[phys_apicid]))
670 num_starts = 2;
671 else
672 num_starts = 0;
673
674 /*
675 * Paravirt / VMI wants a startup IPI hook here to set up the
676 * target processor state.
677 */
678 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
679 (unsigned long) stack_start.esp);
680
681 /*
682 * Run STARTUP IPI loop.
683 */
684 Dprintk("#startup loops: %d.\n", num_starts);
685
686 maxlvt = lapic_get_maxlvt();
687
688 for (j = 1; j <= num_starts; j++) {
689 Dprintk("Sending STARTUP #%d.\n",j);
690 apic_read_around(APIC_SPIV);
691 apic_write(APIC_ESR, 0);
692 apic_read(APIC_ESR);
693 Dprintk("After apic_write.\n");
694
695 /*
696 * STARTUP IPI
697 */
698
699 /* Target chip */
700 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
701
702 /* Boot on the stack */
703 /* Kick the second */
704 apic_write_around(APIC_ICR, APIC_DM_STARTUP
705 | (start_eip >> 12));
706
707 /*
708 * Give the other CPU some time to accept the IPI.
709 */
710 udelay(300);
711
712 Dprintk("Startup point 1.\n");
713
714 Dprintk("Waiting for send to finish...\n");
715 timeout = 0;
716 do {
717 Dprintk("+");
718 udelay(100);
719 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
720 } while (send_status && (timeout++ < 1000));
721
722 /*
723 * Give the other CPU some time to accept the IPI.
724 */
725 udelay(200);
726 /*
727 * Due to the Pentium erratum 3AP.
728 */
729 if (maxlvt > 3) {
730 apic_read_around(APIC_SPIV);
731 apic_write(APIC_ESR, 0);
732 }
733 accept_status = (apic_read(APIC_ESR) & 0xEF);
734 if (send_status || accept_status)
735 break;
736 }
737 Dprintk("After Startup.\n");
738
739 if (send_status)
740 printk("APIC never delivered???\n");
741 if (accept_status)
742 printk("APIC delivery error (%lx).\n", accept_status);
743
744 return (send_status | accept_status);
745 }
746 #endif /* WAKE_SECONDARY_VIA_INIT */
747
748 extern cpumask_t cpu_initialized;
749 static inline int alloc_cpu_id(void)
750 {
751 cpumask_t tmp_map;
752 int cpu;
753 cpus_complement(tmp_map, cpu_present_map);
754 cpu = first_cpu(tmp_map);
755 if (cpu >= NR_CPUS)
756 return -ENODEV;
757 return cpu;
758 }
759
760 #ifdef CONFIG_HOTPLUG_CPU
761 static struct task_struct * __devinitdata cpu_idle_tasks[NR_CPUS];
762 static inline struct task_struct * alloc_idle_task(int cpu)
763 {
764 struct task_struct *idle;
765
766 if ((idle = cpu_idle_tasks[cpu]) != NULL) {
767 /* initialize thread_struct. we really want to avoid destroy
768 * idle tread
769 */
770 idle->thread.esp = (unsigned long)task_pt_regs(idle);
771 init_idle(idle, cpu);
772 return idle;
773 }
774 idle = fork_idle(cpu);
775
776 if (!IS_ERR(idle))
777 cpu_idle_tasks[cpu] = idle;
778 return idle;
779 }
780 #else
781 #define alloc_idle_task(cpu) fork_idle(cpu)
782 #endif
783
784 /* Initialize the CPU's GDT. This is either the boot CPU doing itself
785 (still using the master per-cpu area), or a CPU doing it for a
786 secondary which will soon come up. */
787 static __cpuinit void init_gdt(int cpu, struct task_struct *idle)
788 {
789 struct desc_struct *gdt = get_cpu_gdt_table(cpu);
790 struct i386_pda *pda = &per_cpu(_cpu_pda, cpu);
791
792 pack_descriptor((u32 *)&gdt[GDT_ENTRY_PDA].a,
793 (u32 *)&gdt[GDT_ENTRY_PDA].b,
794 (unsigned long)pda, sizeof(*pda) - 1,
795 0x80 | DESCTYPE_S | 0x2, 0); /* present read-write data segment */
796
797 memset(pda, 0, sizeof(*pda));
798 pda->_pda = pda;
799 pda->cpu_number = cpu;
800 pda->pcurrent = idle;
801 }
802
803 /* Defined in head.S */
804 extern struct Xgt_desc_struct early_gdt_descr;
805
806 static int __cpuinit do_boot_cpu(int apicid, int cpu)
807 /*
808 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
809 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
810 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
811 */
812 {
813 struct task_struct *idle;
814 unsigned long boot_error;
815 int timeout;
816 unsigned long start_eip;
817 unsigned short nmi_high = 0, nmi_low = 0;
818
819 /*
820 * We can't use kernel_thread since we must avoid to
821 * reschedule the child.
822 */
823 idle = alloc_idle_task(cpu);
824 if (IS_ERR(idle))
825 panic("failed fork for CPU %d", cpu);
826
827 init_gdt(cpu, idle);
828 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
829 start_pda = cpu_pda(cpu);
830
831 idle->thread.eip = (unsigned long) start_secondary;
832 /* start_eip had better be page-aligned! */
833 start_eip = setup_trampoline();
834
835 ++cpucount;
836 alternatives_smp_switch(1);
837
838 /* So we see what's up */
839 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
840 /* Stack for startup_32 can be just as for start_secondary onwards */
841 stack_start.esp = (void *) idle->thread.esp;
842
843 irq_ctx_init(cpu);
844
845 x86_cpu_to_apicid[cpu] = apicid;
846 /*
847 * This grunge runs the startup process for
848 * the targeted processor.
849 */
850
851 atomic_set(&init_deasserted, 0);
852
853 Dprintk("Setting warm reset code and vector.\n");
854
855 store_NMI_vector(&nmi_high, &nmi_low);
856
857 smpboot_setup_warm_reset_vector(start_eip);
858
859 /*
860 * Starting actual IPI sequence...
861 */
862 boot_error = wakeup_secondary_cpu(apicid, start_eip);
863
864 if (!boot_error) {
865 /*
866 * allow APs to start initializing.
867 */
868 Dprintk("Before Callout %d.\n", cpu);
869 cpu_set(cpu, cpu_callout_map);
870 Dprintk("After Callout %d.\n", cpu);
871
872 /*
873 * Wait 5s total for a response
874 */
875 for (timeout = 0; timeout < 50000; timeout++) {
876 if (cpu_isset(cpu, cpu_callin_map))
877 break; /* It has booted */
878 udelay(100);
879 }
880
881 if (cpu_isset(cpu, cpu_callin_map)) {
882 /* number CPUs logically, starting from 1 (BSP is 0) */
883 Dprintk("OK.\n");
884 printk("CPU%d: ", cpu);
885 print_cpu_info(&cpu_data[cpu]);
886 Dprintk("CPU has booted.\n");
887 } else {
888 boot_error= 1;
889 if (*((volatile unsigned char *)trampoline_base)
890 == 0xA5)
891 /* trampoline started but...? */
892 printk("Stuck ??\n");
893 else
894 /* trampoline code not run */
895 printk("Not responding.\n");
896 inquire_remote_apic(apicid);
897 }
898 }
899
900 if (boot_error) {
901 /* Try to put things back the way they were before ... */
902 unmap_cpu_to_logical_apicid(cpu);
903 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
904 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
905 cpucount--;
906 } else {
907 x86_cpu_to_apicid[cpu] = apicid;
908 cpu_set(cpu, cpu_present_map);
909 }
910
911 /* mark "stuck" area as not stuck */
912 *((volatile unsigned long *)trampoline_base) = 0;
913
914 return boot_error;
915 }
916
917 #ifdef CONFIG_HOTPLUG_CPU
918 void cpu_exit_clear(void)
919 {
920 int cpu = raw_smp_processor_id();
921
922 idle_task_exit();
923
924 cpucount --;
925 cpu_uninit();
926 irq_ctx_exit(cpu);
927
928 cpu_clear(cpu, cpu_callout_map);
929 cpu_clear(cpu, cpu_callin_map);
930
931 cpu_clear(cpu, smp_commenced_mask);
932 unmap_cpu_to_logical_apicid(cpu);
933 }
934
935 struct warm_boot_cpu_info {
936 struct completion *complete;
937 struct work_struct task;
938 int apicid;
939 int cpu;
940 };
941
942 static void __cpuinit do_warm_boot_cpu(struct work_struct *work)
943 {
944 struct warm_boot_cpu_info *info =
945 container_of(work, struct warm_boot_cpu_info, task);
946 do_boot_cpu(info->apicid, info->cpu);
947 complete(info->complete);
948 }
949
950 static int __cpuinit __smp_prepare_cpu(int cpu)
951 {
952 DECLARE_COMPLETION_ONSTACK(done);
953 struct warm_boot_cpu_info info;
954 int apicid, ret;
955
956 apicid = x86_cpu_to_apicid[cpu];
957 if (apicid == BAD_APICID) {
958 ret = -ENODEV;
959 goto exit;
960 }
961
962 info.complete = &done;
963 info.apicid = apicid;
964 info.cpu = cpu;
965 INIT_WORK(&info.task, do_warm_boot_cpu);
966
967 /* init low mem mapping */
968 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
969 min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS));
970 flush_tlb_all();
971 schedule_work(&info.task);
972 wait_for_completion(&done);
973
974 zap_low_mappings();
975 ret = 0;
976 exit:
977 return ret;
978 }
979 #endif
980
981 static void smp_tune_scheduling(void)
982 {
983 unsigned long cachesize; /* kB */
984
985 if (cpu_khz) {
986 cachesize = boot_cpu_data.x86_cache_size;
987
988 if (cachesize > 0)
989 max_cache_size = cachesize * 1024;
990 }
991 }
992
993 /*
994 * Cycle through the processors sending APIC IPIs to boot each.
995 */
996
997 static int boot_cpu_logical_apicid;
998 /* Where the IO area was mapped on multiquad, always 0 otherwise */
999 void *xquad_portio;
1000 #ifdef CONFIG_X86_NUMAQ
1001 EXPORT_SYMBOL(xquad_portio);
1002 #endif
1003
1004 static void __init smp_boot_cpus(unsigned int max_cpus)
1005 {
1006 int apicid, cpu, bit, kicked;
1007 unsigned long bogosum = 0;
1008
1009 /*
1010 * Setup boot CPU information
1011 */
1012 smp_store_cpu_info(0); /* Final full version of the data */
1013 printk("CPU%d: ", 0);
1014 print_cpu_info(&cpu_data[0]);
1015
1016 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
1017 boot_cpu_logical_apicid = logical_smp_processor_id();
1018 x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
1019
1020 current_thread_info()->cpu = 0;
1021 smp_tune_scheduling();
1022
1023 set_cpu_sibling_map(0);
1024
1025 /*
1026 * If we couldn't find an SMP configuration at boot time,
1027 * get out of here now!
1028 */
1029 if (!smp_found_config && !acpi_lapic) {
1030 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1031 smpboot_clear_io_apic_irqs();
1032 phys_cpu_present_map = physid_mask_of_physid(0);
1033 if (APIC_init_uniprocessor())
1034 printk(KERN_NOTICE "Local APIC not detected."
1035 " Using dummy APIC emulation.\n");
1036 map_cpu_to_logical_apicid();
1037 cpu_set(0, cpu_sibling_map[0]);
1038 cpu_set(0, cpu_core_map[0]);
1039 return;
1040 }
1041
1042 /*
1043 * Should not be necessary because the MP table should list the boot
1044 * CPU too, but we do it for the sake of robustness anyway.
1045 * Makes no sense to do this check in clustered apic mode, so skip it
1046 */
1047 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1048 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1049 boot_cpu_physical_apicid);
1050 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1051 }
1052
1053 /*
1054 * If we couldn't find a local APIC, then get out of here now!
1055 */
1056 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
1057 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1058 boot_cpu_physical_apicid);
1059 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1060 smpboot_clear_io_apic_irqs();
1061 phys_cpu_present_map = physid_mask_of_physid(0);
1062 cpu_set(0, cpu_sibling_map[0]);
1063 cpu_set(0, cpu_core_map[0]);
1064 return;
1065 }
1066
1067 verify_local_APIC();
1068
1069 /*
1070 * If SMP should be disabled, then really disable it!
1071 */
1072 if (!max_cpus) {
1073 smp_found_config = 0;
1074 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1075 smpboot_clear_io_apic_irqs();
1076 phys_cpu_present_map = physid_mask_of_physid(0);
1077 cpu_set(0, cpu_sibling_map[0]);
1078 cpu_set(0, cpu_core_map[0]);
1079 return;
1080 }
1081
1082 connect_bsp_APIC();
1083 setup_local_APIC();
1084 map_cpu_to_logical_apicid();
1085
1086
1087 setup_portio_remap();
1088
1089 /*
1090 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1091 *
1092 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1093 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1094 * clustered apic ID.
1095 */
1096 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
1097
1098 kicked = 1;
1099 for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
1100 apicid = cpu_present_to_apicid(bit);
1101 /*
1102 * Don't even attempt to start the boot CPU!
1103 */
1104 if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
1105 continue;
1106
1107 if (!check_apicid_present(bit))
1108 continue;
1109 if (max_cpus <= cpucount+1)
1110 continue;
1111
1112 if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu))
1113 printk("CPU #%d not responding - cannot use it.\n",
1114 apicid);
1115 else
1116 ++kicked;
1117 }
1118
1119 /*
1120 * Cleanup possible dangling ends...
1121 */
1122 smpboot_restore_warm_reset_vector();
1123
1124 /*
1125 * Allow the user to impress friends.
1126 */
1127 Dprintk("Before bogomips.\n");
1128 for (cpu = 0; cpu < NR_CPUS; cpu++)
1129 if (cpu_isset(cpu, cpu_callout_map))
1130 bogosum += cpu_data[cpu].loops_per_jiffy;
1131 printk(KERN_INFO
1132 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1133 cpucount+1,
1134 bogosum/(500000/HZ),
1135 (bogosum/(5000/HZ))%100);
1136
1137 Dprintk("Before bogocount - setting activated=1.\n");
1138
1139 if (smp_b_stepping)
1140 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1141
1142 /*
1143 * Don't taint if we are running SMP kernel on a single non-MP
1144 * approved Athlon
1145 */
1146 if (tainted & TAINT_UNSAFE_SMP) {
1147 if (cpucount)
1148 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
1149 else
1150 tainted &= ~TAINT_UNSAFE_SMP;
1151 }
1152
1153 Dprintk("Boot done.\n");
1154
1155 /*
1156 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1157 * efficiently.
1158 */
1159 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1160 cpus_clear(cpu_sibling_map[cpu]);
1161 cpus_clear(cpu_core_map[cpu]);
1162 }
1163
1164 cpu_set(0, cpu_sibling_map[0]);
1165 cpu_set(0, cpu_core_map[0]);
1166
1167 smpboot_setup_io_apic();
1168
1169 setup_boot_clock();
1170 }
1171
1172 /* These are wrappers to interface to the new boot process. Someone
1173 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1174 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1175 {
1176 smp_commenced_mask = cpumask_of_cpu(0);
1177 cpu_callin_map = cpumask_of_cpu(0);
1178 mb();
1179 smp_boot_cpus(max_cpus);
1180 }
1181
1182 /* Current gdt points %fs at the "master" per-cpu area: after this,
1183 * it's on the real one. */
1184 static inline void switch_to_new_gdt(void)
1185 {
1186 struct Xgt_desc_struct gdt_descr;
1187
1188 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
1189 gdt_descr.size = GDT_SIZE - 1;
1190 load_gdt(&gdt_descr);
1191 asm volatile ("mov %0, %%fs" : : "r" (__KERNEL_PDA) : "memory");
1192 }
1193
1194 void __init native_smp_prepare_boot_cpu(void)
1195 {
1196 unsigned int cpu = smp_processor_id();
1197
1198 init_gdt(cpu, current);
1199 switch_to_new_gdt();
1200
1201 cpu_set(cpu, cpu_online_map);
1202 cpu_set(cpu, cpu_callout_map);
1203 cpu_set(cpu, cpu_present_map);
1204 cpu_set(cpu, cpu_possible_map);
1205 __get_cpu_var(cpu_state) = CPU_ONLINE;
1206 }
1207
1208 #ifdef CONFIG_HOTPLUG_CPU
1209 static void
1210 remove_siblinginfo(int cpu)
1211 {
1212 int sibling;
1213 struct cpuinfo_x86 *c = cpu_data;
1214
1215 for_each_cpu_mask(sibling, cpu_core_map[cpu]) {
1216 cpu_clear(cpu, cpu_core_map[sibling]);
1217 /*
1218 * last thread sibling in this cpu core going down
1219 */
1220 if (cpus_weight(cpu_sibling_map[cpu]) == 1)
1221 c[sibling].booted_cores--;
1222 }
1223
1224 for_each_cpu_mask(sibling, cpu_sibling_map[cpu])
1225 cpu_clear(cpu, cpu_sibling_map[sibling]);
1226 cpus_clear(cpu_sibling_map[cpu]);
1227 cpus_clear(cpu_core_map[cpu]);
1228 c[cpu].phys_proc_id = 0;
1229 c[cpu].cpu_core_id = 0;
1230 cpu_clear(cpu, cpu_sibling_setup_map);
1231 }
1232
1233 int __cpu_disable(void)
1234 {
1235 cpumask_t map = cpu_online_map;
1236 int cpu = smp_processor_id();
1237
1238 /*
1239 * Perhaps use cpufreq to drop frequency, but that could go
1240 * into generic code.
1241 *
1242 * We won't take down the boot processor on i386 due to some
1243 * interrupts only being able to be serviced by the BSP.
1244 * Especially so if we're not using an IOAPIC -zwane
1245 */
1246 if (cpu == 0)
1247 return -EBUSY;
1248 if (nmi_watchdog == NMI_LOCAL_APIC)
1249 stop_apic_nmi_watchdog(NULL);
1250 clear_local_APIC();
1251 /* Allow any queued timer interrupts to get serviced */
1252 local_irq_enable();
1253 mdelay(1);
1254 local_irq_disable();
1255
1256 remove_siblinginfo(cpu);
1257
1258 cpu_clear(cpu, map);
1259 fixup_irqs(map);
1260 /* It's now safe to remove this processor from the online map */
1261 cpu_clear(cpu, cpu_online_map);
1262 return 0;
1263 }
1264
1265 void __cpu_die(unsigned int cpu)
1266 {
1267 /* We don't do anything here: idle task is faking death itself. */
1268 unsigned int i;
1269
1270 for (i = 0; i < 10; i++) {
1271 /* They ack this in play_dead by setting CPU_DEAD */
1272 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1273 printk ("CPU %d is now offline\n", cpu);
1274 if (1 == num_online_cpus())
1275 alternatives_smp_switch(0);
1276 return;
1277 }
1278 msleep(100);
1279 }
1280 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1281 }
1282 #else /* ... !CONFIG_HOTPLUG_CPU */
1283 int __cpu_disable(void)
1284 {
1285 return -ENOSYS;
1286 }
1287
1288 void __cpu_die(unsigned int cpu)
1289 {
1290 /* We said "no" in __cpu_disable */
1291 BUG();
1292 }
1293 #endif /* CONFIG_HOTPLUG_CPU */
1294
1295 int __cpuinit native_cpu_up(unsigned int cpu)
1296 {
1297 unsigned long flags;
1298 #ifdef CONFIG_HOTPLUG_CPU
1299 int ret = 0;
1300
1301 /*
1302 * We do warm boot only on cpus that had booted earlier
1303 * Otherwise cold boot is all handled from smp_boot_cpus().
1304 * cpu_callin_map is set during AP kickstart process. Its reset
1305 * when a cpu is taken offline from cpu_exit_clear().
1306 */
1307 if (!cpu_isset(cpu, cpu_callin_map))
1308 ret = __smp_prepare_cpu(cpu);
1309
1310 if (ret)
1311 return -EIO;
1312 #endif
1313
1314 /* In case one didn't come up */
1315 if (!cpu_isset(cpu, cpu_callin_map)) {
1316 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1317 return -EIO;
1318 }
1319
1320 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1321 /* Unleash the CPU! */
1322 cpu_set(cpu, smp_commenced_mask);
1323
1324 /*
1325 * Check TSC synchronization with the AP (keep irqs disabled
1326 * while doing so):
1327 */
1328 local_irq_save(flags);
1329 check_tsc_sync_source(cpu);
1330 local_irq_restore(flags);
1331
1332 while (!cpu_isset(cpu, cpu_online_map)) {
1333 cpu_relax();
1334 touch_nmi_watchdog();
1335 }
1336
1337 return 0;
1338 }
1339
1340 void __init native_smp_cpus_done(unsigned int max_cpus)
1341 {
1342 #ifdef CONFIG_X86_IO_APIC
1343 setup_ioapic_dest();
1344 #endif
1345 zap_low_mappings();
1346 #ifndef CONFIG_HOTPLUG_CPU
1347 /*
1348 * Disable executability of the SMP trampoline:
1349 */
1350 set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
1351 #endif
1352 }
1353
1354 void __init smp_intr_init(void)
1355 {
1356 /*
1357 * IRQ0 must be given a fixed assignment and initialized,
1358 * because it's used before the IO-APIC is set up.
1359 */
1360 set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
1361
1362 /*
1363 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1364 * IPI, driven by wakeup.
1365 */
1366 set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
1367
1368 /* IPI for invalidation */
1369 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1370
1371 /* IPI for generic function call */
1372 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
1373 }
1374
1375 /*
1376 * If the BIOS enumerates physical processors before logical,
1377 * maxcpus=N at enumeration-time can be used to disable HT.
1378 */
1379 static int __init parse_maxcpus(char *arg)
1380 {
1381 extern unsigned int maxcpus;
1382
1383 maxcpus = simple_strtoul(arg, NULL, 0);
1384 return 0;
1385 }
1386 early_param("maxcpus", parse_maxcpus);