2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/kernel.h>
41 #include <linux/sched.h>
42 #include <linux/kernel_stat.h>
43 #include <linux/bootmem.h>
44 #include <linux/notifier.h>
45 #include <linux/cpu.h>
46 #include <linux/percpu.h>
47 #include <linux/nmi.h>
49 #include <linux/delay.h>
50 #include <linux/mc146818rtc.h>
51 #include <asm/tlbflush.h>
53 #include <asm/arch_hooks.h>
56 #include <mach_apic.h>
57 #include <mach_wakecpu.h>
58 #include <smpboot_hooks.h>
62 /* Set if we find a B stepping CPU */
63 static int __devinitdata smp_b_stepping
;
65 /* Number of siblings per CPU package */
66 int smp_num_siblings
= 1;
67 EXPORT_SYMBOL(smp_num_siblings
);
69 /* Last level cache ID of each logical CPU */
70 int cpu_llc_id
[NR_CPUS
] __cpuinitdata
= {[0 ... NR_CPUS
-1] = BAD_APICID
};
72 /* representing HT siblings of each logical CPU */
73 cpumask_t cpu_sibling_map
[NR_CPUS
] __read_mostly
;
74 EXPORT_SYMBOL(cpu_sibling_map
);
76 /* representing HT and core siblings of each logical CPU */
77 cpumask_t cpu_core_map
[NR_CPUS
] __read_mostly
;
78 EXPORT_SYMBOL(cpu_core_map
);
80 /* bitmap of online cpus */
81 cpumask_t cpu_online_map __read_mostly
;
82 EXPORT_SYMBOL(cpu_online_map
);
84 cpumask_t cpu_callin_map
;
85 cpumask_t cpu_callout_map
;
86 EXPORT_SYMBOL(cpu_callout_map
);
87 cpumask_t cpu_possible_map
;
88 EXPORT_SYMBOL(cpu_possible_map
);
89 static cpumask_t smp_commenced_mask
;
91 /* Per CPU bogomips and other parameters */
92 struct cpuinfo_x86 cpu_data
[NR_CPUS
] __cacheline_aligned
;
93 EXPORT_SYMBOL(cpu_data
);
95 u8 x86_cpu_to_apicid
[NR_CPUS
] __read_mostly
=
96 { [0 ... NR_CPUS
-1] = 0xff };
97 EXPORT_SYMBOL(x86_cpu_to_apicid
);
99 u8 apicid_2_node
[MAX_APICID
];
101 DEFINE_PER_CPU(unsigned long, this_cpu_off
);
102 EXPORT_PER_CPU_SYMBOL(this_cpu_off
);
105 * Trampoline 80x86 program as an array.
108 extern unsigned char trampoline_data
[];
109 extern unsigned char trampoline_end
[];
110 static unsigned char *trampoline_base
;
111 static int trampoline_exec
;
113 static void map_cpu_to_logical_apicid(void);
115 /* State of each CPU. */
116 DEFINE_PER_CPU(int, cpu_state
) = { 0 };
119 * Currently trivial. Write the real->protected mode
120 * bootstrap into the page concerned. The caller
121 * has made sure it's suitably aligned.
124 static unsigned long __devinit
setup_trampoline(void)
126 memcpy(trampoline_base
, trampoline_data
, trampoline_end
- trampoline_data
);
127 return virt_to_phys(trampoline_base
);
131 * We are called very early to get the low memory for the
132 * SMP bootup trampoline page.
134 void __init
smp_alloc_memory(void)
136 trampoline_base
= (void *) alloc_bootmem_low_pages(PAGE_SIZE
);
138 * Has to be in very low memory so we can execute
141 if (__pa(trampoline_base
) >= 0x9F000)
144 * Make the SMP trampoline executable:
146 trampoline_exec
= set_kernel_exec((unsigned long)trampoline_base
, 1);
150 * The bootstrap kernel entry code has set these up. Save them for
154 static void __cpuinit
smp_store_cpu_info(int id
)
156 struct cpuinfo_x86
*c
= cpu_data
+ id
;
160 identify_secondary_cpu(c
);
162 * Mask B, Pentium, but not Pentium MMX
164 if (c
->x86_vendor
== X86_VENDOR_INTEL
&&
166 c
->x86_mask
>= 1 && c
->x86_mask
<= 4 &&
169 * Remember we have B step Pentia with bugs
174 * Certain Athlons might work (for various values of 'work') in SMP
175 * but they are not certified as MP capable.
177 if ((c
->x86_vendor
== X86_VENDOR_AMD
) && (c
->x86
== 6)) {
179 if (num_possible_cpus() == 1)
182 /* Athlon 660/661 is valid. */
183 if ((c
->x86_model
==6) && ((c
->x86_mask
==0) || (c
->x86_mask
==1)))
186 /* Duron 670 is valid */
187 if ((c
->x86_model
==7) && (c
->x86_mask
==0))
191 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
192 * It's worth noting that the A5 stepping (662) of some Athlon XP's
193 * have the MP bit set.
194 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
196 if (((c
->x86_model
==6) && (c
->x86_mask
>=2)) ||
197 ((c
->x86_model
==7) && (c
->x86_mask
>=1)) ||
202 /* If we get here, it's not a certified SMP capable AMD system. */
203 add_taint(TAINT_UNSAFE_SMP
);
210 extern void calibrate_delay(void);
212 static atomic_t init_deasserted
;
214 static void __cpuinit
smp_callin(void)
217 unsigned long timeout
;
220 * If waken up by an INIT in an 82489DX configuration
221 * we may get here before an INIT-deassert IPI reaches
222 * our local APIC. We have to wait for the IPI or we'll
223 * lock up on an APIC access.
225 wait_for_init_deassert(&init_deasserted
);
228 * (This works even if the APIC is not enabled.)
230 phys_id
= GET_APIC_ID(apic_read(APIC_ID
));
231 cpuid
= smp_processor_id();
232 if (cpu_isset(cpuid
, cpu_callin_map
)) {
233 printk("huh, phys CPU#%d, CPU#%d already present??\n",
237 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid
, phys_id
);
240 * STARTUP IPIs are fragile beasts as they might sometimes
241 * trigger some glue motherboard logic. Complete APIC bus
242 * silence for 1 second, this overestimates the time the
243 * boot CPU is spending to send the up to 2 STARTUP IPIs
244 * by a factor of two. This should be enough.
248 * Waiting 2s total for startup (udelay is not yet working)
250 timeout
= jiffies
+ 2*HZ
;
251 while (time_before(jiffies
, timeout
)) {
253 * Has the boot CPU finished it's STARTUP sequence?
255 if (cpu_isset(cpuid
, cpu_callout_map
))
260 if (!time_before(jiffies
, timeout
)) {
261 printk("BUG: CPU%d started up but did not get a callout!\n",
267 * the boot CPU has finished the init stage and is spinning
268 * on callin_map until we finish. We are free to set up this
269 * CPU, first the APIC. (this is probably redundant on most
273 Dprintk("CALLIN, before setup_local_APIC().\n");
274 smp_callin_clear_local_apic();
276 map_cpu_to_logical_apicid();
282 Dprintk("Stack at about %p\n",&cpuid
);
285 * Save our processor parameters
287 smp_store_cpu_info(cpuid
);
290 * Allow the master to continue.
292 cpu_set(cpuid
, cpu_callin_map
);
297 /* maps the cpu to the sched domain representing multi-core */
298 cpumask_t
cpu_coregroup_map(int cpu
)
300 struct cpuinfo_x86
*c
= cpu_data
+ cpu
;
302 * For perf, we return last level cache shared map.
303 * And for power savings, we return cpu_core_map
305 if (sched_mc_power_savings
|| sched_smt_power_savings
)
306 return cpu_core_map
[cpu
];
308 return c
->llc_shared_map
;
311 /* representing cpus for which sibling maps can be computed */
312 static cpumask_t cpu_sibling_setup_map
;
315 set_cpu_sibling_map(int cpu
)
318 struct cpuinfo_x86
*c
= cpu_data
;
320 cpu_set(cpu
, cpu_sibling_setup_map
);
322 if (smp_num_siblings
> 1) {
323 for_each_cpu_mask(i
, cpu_sibling_setup_map
) {
324 if (c
[cpu
].phys_proc_id
== c
[i
].phys_proc_id
&&
325 c
[cpu
].cpu_core_id
== c
[i
].cpu_core_id
) {
326 cpu_set(i
, cpu_sibling_map
[cpu
]);
327 cpu_set(cpu
, cpu_sibling_map
[i
]);
328 cpu_set(i
, cpu_core_map
[cpu
]);
329 cpu_set(cpu
, cpu_core_map
[i
]);
330 cpu_set(i
, c
[cpu
].llc_shared_map
);
331 cpu_set(cpu
, c
[i
].llc_shared_map
);
335 cpu_set(cpu
, cpu_sibling_map
[cpu
]);
338 cpu_set(cpu
, c
[cpu
].llc_shared_map
);
340 if (current_cpu_data
.x86_max_cores
== 1) {
341 cpu_core_map
[cpu
] = cpu_sibling_map
[cpu
];
342 c
[cpu
].booted_cores
= 1;
346 for_each_cpu_mask(i
, cpu_sibling_setup_map
) {
347 if (cpu_llc_id
[cpu
] != BAD_APICID
&&
348 cpu_llc_id
[cpu
] == cpu_llc_id
[i
]) {
349 cpu_set(i
, c
[cpu
].llc_shared_map
);
350 cpu_set(cpu
, c
[i
].llc_shared_map
);
352 if (c
[cpu
].phys_proc_id
== c
[i
].phys_proc_id
) {
353 cpu_set(i
, cpu_core_map
[cpu
]);
354 cpu_set(cpu
, cpu_core_map
[i
]);
356 * Does this new cpu bringup a new core?
358 if (cpus_weight(cpu_sibling_map
[cpu
]) == 1) {
360 * for each core in package, increment
361 * the booted_cores for this new cpu
363 if (first_cpu(cpu_sibling_map
[i
]) == i
)
364 c
[cpu
].booted_cores
++;
366 * increment the core count for all
367 * the other cpus in this package
371 } else if (i
!= cpu
&& !c
[cpu
].booted_cores
)
372 c
[cpu
].booted_cores
= c
[i
].booted_cores
;
378 * Activate a secondary processor.
380 static void __cpuinit
start_secondary(void *unused
)
383 * Don't put *anything* before cpu_init(), SMP booting is too
384 * fragile that we want to limit the things done here to the
385 * most necessary things.
393 while (!cpu_isset(smp_processor_id(), smp_commenced_mask
))
396 * Check TSC synchronization with the BP:
398 check_tsc_sync_target();
400 setup_secondary_clock();
401 if (nmi_watchdog
== NMI_IO_APIC
) {
402 disable_8259A_irq(0);
403 enable_NMI_through_LVT0(NULL
);
407 * low-memory mappings have been cleared, flush them from
408 * the local TLBs too.
412 /* This must be done before setting cpu_online_map */
413 set_cpu_sibling_map(raw_smp_processor_id());
417 * We need to hold call_lock, so there is no inconsistency
418 * between the time smp_call_function() determines number of
419 * IPI receipients, and the time when the determination is made
420 * for which cpus receive the IPI. Holding this
421 * lock helps us to not include this cpu in a currently in progress
422 * smp_call_function().
424 lock_ipi_call_lock();
425 cpu_set(smp_processor_id(), cpu_online_map
);
426 unlock_ipi_call_lock();
427 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
429 /* We can take interrupts now: we're officially "up". */
437 * Everything has been set up for the secondary
438 * CPUs - they just need to reload everything
439 * from the task structure
440 * This function must not return.
442 void __devinit
initialize_secondary(void)
445 * We don't actually need to load the full TSS,
446 * basically just the stack pointer and the eip.
453 :"m" (current
->thread
.esp
),"m" (current
->thread
.eip
));
456 /* Static state in head.S used to set up a CPU */
464 /* which logical CPUs are on which nodes */
465 cpumask_t node_2_cpu_mask
[MAX_NUMNODES
] __read_mostly
=
466 { [0 ... MAX_NUMNODES
-1] = CPU_MASK_NONE
};
467 EXPORT_SYMBOL(node_2_cpu_mask
);
468 /* which node each logical CPU is on */
469 int cpu_2_node
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = 0 };
470 EXPORT_SYMBOL(cpu_2_node
);
472 /* set up a mapping between cpu and node. */
473 static inline void map_cpu_to_node(int cpu
, int node
)
475 printk("Mapping cpu %d to node %d\n", cpu
, node
);
476 cpu_set(cpu
, node_2_cpu_mask
[node
]);
477 cpu_2_node
[cpu
] = node
;
480 /* undo a mapping between cpu and node. */
481 static inline void unmap_cpu_to_node(int cpu
)
485 printk("Unmapping cpu %d from all nodes\n", cpu
);
486 for (node
= 0; node
< MAX_NUMNODES
; node
++)
487 cpu_clear(cpu
, node_2_cpu_mask
[node
]);
490 #else /* !CONFIG_NUMA */
492 #define map_cpu_to_node(cpu, node) ({})
493 #define unmap_cpu_to_node(cpu) ({})
495 #endif /* CONFIG_NUMA */
497 u8 cpu_2_logical_apicid
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = BAD_APICID
};
499 static void map_cpu_to_logical_apicid(void)
501 int cpu
= smp_processor_id();
502 int apicid
= logical_smp_processor_id();
503 int node
= apicid_to_node(apicid
);
505 if (!node_online(node
))
506 node
= first_online_node
;
508 cpu_2_logical_apicid
[cpu
] = apicid
;
509 map_cpu_to_node(cpu
, node
);
512 static void unmap_cpu_to_logical_apicid(int cpu
)
514 cpu_2_logical_apicid
[cpu
] = BAD_APICID
;
515 unmap_cpu_to_node(cpu
);
518 static inline void __inquire_remote_apic(int apicid
)
520 int i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
521 char *names
[] = { "ID", "VERSION", "SPIV" };
523 unsigned long status
;
525 printk("Inquiring remote APIC #%d...\n", apicid
);
527 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
528 printk("... APIC #%d %s: ", apicid
, names
[i
]);
533 status
= safe_apic_wait_icr_idle();
535 printk("a previous APIC delivery may have failed\n");
537 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(apicid
));
538 apic_write_around(APIC_ICR
, APIC_DM_REMRD
| regs
[i
]);
543 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
544 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
547 case APIC_ICR_RR_VALID
:
548 status
= apic_read(APIC_RRR
);
549 printk("%lx\n", status
);
557 #ifdef WAKE_SECONDARY_VIA_NMI
559 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
560 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
561 * won't ... remember to clear down the APIC, etc later.
564 wakeup_secondary_cpu(int logical_apicid
, unsigned long start_eip
)
566 unsigned long send_status
, accept_status
= 0;
570 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(logical_apicid
));
572 /* Boot on the stack */
573 /* Kick the second */
574 apic_write_around(APIC_ICR
, APIC_DM_NMI
| APIC_DEST_LOGICAL
);
576 Dprintk("Waiting for send to finish...\n");
577 send_status
= safe_apic_wait_icr_idle();
580 * Give the other CPU some time to accept the IPI.
584 * Due to the Pentium erratum 3AP.
586 maxlvt
= lapic_get_maxlvt();
588 apic_read_around(APIC_SPIV
);
589 apic_write(APIC_ESR
, 0);
591 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
592 Dprintk("NMI sent.\n");
595 printk("APIC never delivered???\n");
597 printk("APIC delivery error (%lx).\n", accept_status
);
599 return (send_status
| accept_status
);
601 #endif /* WAKE_SECONDARY_VIA_NMI */
603 #ifdef WAKE_SECONDARY_VIA_INIT
605 wakeup_secondary_cpu(int phys_apicid
, unsigned long start_eip
)
607 unsigned long send_status
, accept_status
= 0;
608 int maxlvt
, num_starts
, j
;
611 * Be paranoid about clearing APIC errors.
613 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
614 apic_read_around(APIC_SPIV
);
615 apic_write(APIC_ESR
, 0);
619 Dprintk("Asserting INIT.\n");
622 * Turn INIT on target chip
624 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
629 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
632 Dprintk("Waiting for send to finish...\n");
633 send_status
= safe_apic_wait_icr_idle();
637 Dprintk("Deasserting INIT.\n");
640 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
643 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
645 Dprintk("Waiting for send to finish...\n");
646 send_status
= safe_apic_wait_icr_idle();
648 atomic_set(&init_deasserted
, 1);
651 * Should we send STARTUP IPIs ?
653 * Determine this based on the APIC version.
654 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
656 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
662 * Paravirt / VMI wants a startup IPI hook here to set up the
663 * target processor state.
665 startup_ipi_hook(phys_apicid
, (unsigned long) start_secondary
,
666 (unsigned long) stack_start
.esp
);
669 * Run STARTUP IPI loop.
671 Dprintk("#startup loops: %d.\n", num_starts
);
673 maxlvt
= lapic_get_maxlvt();
675 for (j
= 1; j
<= num_starts
; j
++) {
676 Dprintk("Sending STARTUP #%d.\n",j
);
677 apic_read_around(APIC_SPIV
);
678 apic_write(APIC_ESR
, 0);
680 Dprintk("After apic_write.\n");
687 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
689 /* Boot on the stack */
690 /* Kick the second */
691 apic_write_around(APIC_ICR
, APIC_DM_STARTUP
692 | (start_eip
>> 12));
695 * Give the other CPU some time to accept the IPI.
699 Dprintk("Startup point 1.\n");
701 Dprintk("Waiting for send to finish...\n");
702 send_status
= safe_apic_wait_icr_idle();
705 * Give the other CPU some time to accept the IPI.
709 * Due to the Pentium erratum 3AP.
712 apic_read_around(APIC_SPIV
);
713 apic_write(APIC_ESR
, 0);
715 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
716 if (send_status
|| accept_status
)
719 Dprintk("After Startup.\n");
722 printk("APIC never delivered???\n");
724 printk("APIC delivery error (%lx).\n", accept_status
);
726 return (send_status
| accept_status
);
728 #endif /* WAKE_SECONDARY_VIA_INIT */
730 extern cpumask_t cpu_initialized
;
731 static inline int alloc_cpu_id(void)
735 cpus_complement(tmp_map
, cpu_present_map
);
736 cpu
= first_cpu(tmp_map
);
742 #ifdef CONFIG_HOTPLUG_CPU
743 static struct task_struct
* __devinitdata cpu_idle_tasks
[NR_CPUS
];
744 static inline struct task_struct
* alloc_idle_task(int cpu
)
746 struct task_struct
*idle
;
748 if ((idle
= cpu_idle_tasks
[cpu
]) != NULL
) {
749 /* initialize thread_struct. we really want to avoid destroy
752 idle
->thread
.esp
= (unsigned long)task_pt_regs(idle
);
753 init_idle(idle
, cpu
);
756 idle
= fork_idle(cpu
);
759 cpu_idle_tasks
[cpu
] = idle
;
763 #define alloc_idle_task(cpu) fork_idle(cpu)
766 /* Initialize the CPU's GDT. This is either the boot CPU doing itself
767 (still using the master per-cpu area), or a CPU doing it for a
768 secondary which will soon come up. */
769 static __cpuinit
void init_gdt(int cpu
)
771 struct desc_struct
*gdt
= get_cpu_gdt_table(cpu
);
773 pack_descriptor((u32
*)&gdt
[GDT_ENTRY_PERCPU
].a
,
774 (u32
*)&gdt
[GDT_ENTRY_PERCPU
].b
,
775 __per_cpu_offset
[cpu
], 0xFFFFF,
776 0x80 | DESCTYPE_S
| 0x2, 0x8);
778 per_cpu(this_cpu_off
, cpu
) = __per_cpu_offset
[cpu
];
779 per_cpu(cpu_number
, cpu
) = cpu
;
782 /* Defined in head.S */
783 extern struct Xgt_desc_struct early_gdt_descr
;
785 static int __cpuinit
do_boot_cpu(int apicid
, int cpu
)
787 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
788 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
789 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
792 struct task_struct
*idle
;
793 unsigned long boot_error
;
795 unsigned long start_eip
;
796 unsigned short nmi_high
= 0, nmi_low
= 0;
799 * Save current MTRR state in case it was changed since early boot
800 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
805 * We can't use kernel_thread since we must avoid to
806 * reschedule the child.
808 idle
= alloc_idle_task(cpu
);
810 panic("failed fork for CPU %d", cpu
);
813 per_cpu(current_task
, cpu
) = idle
;
814 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
816 idle
->thread
.eip
= (unsigned long) start_secondary
;
817 /* start_eip had better be page-aligned! */
818 start_eip
= setup_trampoline();
821 alternatives_smp_switch(1);
823 /* So we see what's up */
824 printk("Booting processor %d/%d eip %lx\n", cpu
, apicid
, start_eip
);
825 /* Stack for startup_32 can be just as for start_secondary onwards */
826 stack_start
.esp
= (void *) idle
->thread
.esp
;
830 x86_cpu_to_apicid
[cpu
] = apicid
;
832 * This grunge runs the startup process for
833 * the targeted processor.
836 atomic_set(&init_deasserted
, 0);
838 Dprintk("Setting warm reset code and vector.\n");
840 store_NMI_vector(&nmi_high
, &nmi_low
);
842 smpboot_setup_warm_reset_vector(start_eip
);
845 * Starting actual IPI sequence...
847 boot_error
= wakeup_secondary_cpu(apicid
, start_eip
);
851 * allow APs to start initializing.
853 Dprintk("Before Callout %d.\n", cpu
);
854 cpu_set(cpu
, cpu_callout_map
);
855 Dprintk("After Callout %d.\n", cpu
);
858 * Wait 5s total for a response
860 for (timeout
= 0; timeout
< 50000; timeout
++) {
861 if (cpu_isset(cpu
, cpu_callin_map
))
862 break; /* It has booted */
866 if (cpu_isset(cpu
, cpu_callin_map
)) {
867 /* number CPUs logically, starting from 1 (BSP is 0) */
869 printk("CPU%d: ", cpu
);
870 print_cpu_info(&cpu_data
[cpu
]);
871 Dprintk("CPU has booted.\n");
874 if (*((volatile unsigned char *)trampoline_base
)
876 /* trampoline started but...? */
877 printk("Stuck ??\n");
879 /* trampoline code not run */
880 printk("Not responding.\n");
881 inquire_remote_apic(apicid
);
886 /* Try to put things back the way they were before ... */
887 unmap_cpu_to_logical_apicid(cpu
);
888 cpu_clear(cpu
, cpu_callout_map
); /* was set here (do_boot_cpu()) */
889 cpu_clear(cpu
, cpu_initialized
); /* was set by cpu_init() */
892 x86_cpu_to_apicid
[cpu
] = apicid
;
893 cpu_set(cpu
, cpu_present_map
);
896 /* mark "stuck" area as not stuck */
897 *((volatile unsigned long *)trampoline_base
) = 0;
902 #ifdef CONFIG_HOTPLUG_CPU
903 void cpu_exit_clear(void)
905 int cpu
= raw_smp_processor_id();
913 cpu_clear(cpu
, cpu_callout_map
);
914 cpu_clear(cpu
, cpu_callin_map
);
916 cpu_clear(cpu
, smp_commenced_mask
);
917 unmap_cpu_to_logical_apicid(cpu
);
920 struct warm_boot_cpu_info
{
921 struct completion
*complete
;
922 struct work_struct task
;
927 static void __cpuinit
do_warm_boot_cpu(struct work_struct
*work
)
929 struct warm_boot_cpu_info
*info
=
930 container_of(work
, struct warm_boot_cpu_info
, task
);
931 do_boot_cpu(info
->apicid
, info
->cpu
);
932 complete(info
->complete
);
935 static int __cpuinit
__smp_prepare_cpu(int cpu
)
937 DECLARE_COMPLETION_ONSTACK(done
);
938 struct warm_boot_cpu_info info
;
941 apicid
= x86_cpu_to_apicid
[cpu
];
942 if (apicid
== BAD_APICID
) {
947 info
.complete
= &done
;
948 info
.apicid
= apicid
;
950 INIT_WORK(&info
.task
, do_warm_boot_cpu
);
952 /* init low mem mapping */
953 clone_pgd_range(swapper_pg_dir
, swapper_pg_dir
+ USER_PGD_PTRS
,
954 min_t(unsigned long, KERNEL_PGD_PTRS
, USER_PGD_PTRS
));
956 schedule_work(&info
.task
);
957 wait_for_completion(&done
);
966 static void smp_tune_scheduling(void)
968 unsigned long cachesize
; /* kB */
971 cachesize
= boot_cpu_data
.x86_cache_size
;
974 max_cache_size
= cachesize
* 1024;
979 * Cycle through the processors sending APIC IPIs to boot each.
982 static int boot_cpu_logical_apicid
;
983 /* Where the IO area was mapped on multiquad, always 0 otherwise */
985 #ifdef CONFIG_X86_NUMAQ
986 EXPORT_SYMBOL(xquad_portio
);
989 static void __init
smp_boot_cpus(unsigned int max_cpus
)
991 int apicid
, cpu
, bit
, kicked
;
992 unsigned long bogosum
= 0;
995 * Setup boot CPU information
997 smp_store_cpu_info(0); /* Final full version of the data */
998 printk("CPU%d: ", 0);
999 print_cpu_info(&cpu_data
[0]);
1001 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1002 boot_cpu_logical_apicid
= logical_smp_processor_id();
1003 x86_cpu_to_apicid
[0] = boot_cpu_physical_apicid
;
1005 current_thread_info()->cpu
= 0;
1006 smp_tune_scheduling();
1008 set_cpu_sibling_map(0);
1011 * If we couldn't find an SMP configuration at boot time,
1012 * get out of here now!
1014 if (!smp_found_config
&& !acpi_lapic
) {
1015 printk(KERN_NOTICE
"SMP motherboard not detected.\n");
1016 smpboot_clear_io_apic_irqs();
1017 phys_cpu_present_map
= physid_mask_of_physid(0);
1018 if (APIC_init_uniprocessor())
1019 printk(KERN_NOTICE
"Local APIC not detected."
1020 " Using dummy APIC emulation.\n");
1021 map_cpu_to_logical_apicid();
1022 cpu_set(0, cpu_sibling_map
[0]);
1023 cpu_set(0, cpu_core_map
[0]);
1028 * Should not be necessary because the MP table should list the boot
1029 * CPU too, but we do it for the sake of robustness anyway.
1030 * Makes no sense to do this check in clustered apic mode, so skip it
1032 if (!check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1033 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1034 boot_cpu_physical_apicid
);
1035 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1039 * If we couldn't find a local APIC, then get out of here now!
1041 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) && !cpu_has_apic
) {
1042 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1043 boot_cpu_physical_apicid
);
1044 printk(KERN_ERR
"... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1045 smpboot_clear_io_apic_irqs();
1046 phys_cpu_present_map
= physid_mask_of_physid(0);
1047 cpu_set(0, cpu_sibling_map
[0]);
1048 cpu_set(0, cpu_core_map
[0]);
1052 verify_local_APIC();
1055 * If SMP should be disabled, then really disable it!
1058 smp_found_config
= 0;
1059 printk(KERN_INFO
"SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1060 smpboot_clear_io_apic_irqs();
1061 phys_cpu_present_map
= physid_mask_of_physid(0);
1062 cpu_set(0, cpu_sibling_map
[0]);
1063 cpu_set(0, cpu_core_map
[0]);
1069 map_cpu_to_logical_apicid();
1072 setup_portio_remap();
1075 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1077 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1078 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1079 * clustered apic ID.
1081 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map
));
1084 for (bit
= 0; kicked
< NR_CPUS
&& bit
< MAX_APICS
; bit
++) {
1085 apicid
= cpu_present_to_apicid(bit
);
1087 * Don't even attempt to start the boot CPU!
1089 if ((apicid
== boot_cpu_apicid
) || (apicid
== BAD_APICID
))
1092 if (!check_apicid_present(bit
))
1094 if (max_cpus
<= cpucount
+1)
1097 if (((cpu
= alloc_cpu_id()) <= 0) || do_boot_cpu(apicid
, cpu
))
1098 printk("CPU #%d not responding - cannot use it.\n",
1105 * Cleanup possible dangling ends...
1107 smpboot_restore_warm_reset_vector();
1110 * Allow the user to impress friends.
1112 Dprintk("Before bogomips.\n");
1113 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++)
1114 if (cpu_isset(cpu
, cpu_callout_map
))
1115 bogosum
+= cpu_data
[cpu
].loops_per_jiffy
;
1117 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1119 bogosum
/(500000/HZ
),
1120 (bogosum
/(5000/HZ
))%100);
1122 Dprintk("Before bogocount - setting activated=1.\n");
1125 printk(KERN_WARNING
"WARNING: SMP operation may be unreliable with B stepping processors.\n");
1128 * Don't taint if we are running SMP kernel on a single non-MP
1131 if (tainted
& TAINT_UNSAFE_SMP
) {
1133 printk (KERN_INFO
"WARNING: This combination of AMD processors is not suitable for SMP.\n");
1135 tainted
&= ~TAINT_UNSAFE_SMP
;
1138 Dprintk("Boot done.\n");
1141 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1144 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++) {
1145 cpus_clear(cpu_sibling_map
[cpu
]);
1146 cpus_clear(cpu_core_map
[cpu
]);
1149 cpu_set(0, cpu_sibling_map
[0]);
1150 cpu_set(0, cpu_core_map
[0]);
1152 smpboot_setup_io_apic();
1157 /* These are wrappers to interface to the new boot process. Someone
1158 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1159 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1161 smp_commenced_mask
= cpumask_of_cpu(0);
1162 cpu_callin_map
= cpumask_of_cpu(0);
1164 smp_boot_cpus(max_cpus
);
1167 void __init
native_smp_prepare_boot_cpu(void)
1169 unsigned int cpu
= smp_processor_id();
1172 switch_to_new_gdt();
1174 cpu_set(cpu
, cpu_online_map
);
1175 cpu_set(cpu
, cpu_callout_map
);
1176 cpu_set(cpu
, cpu_present_map
);
1177 cpu_set(cpu
, cpu_possible_map
);
1178 __get_cpu_var(cpu_state
) = CPU_ONLINE
;
1181 #ifdef CONFIG_HOTPLUG_CPU
1183 remove_siblinginfo(int cpu
)
1186 struct cpuinfo_x86
*c
= cpu_data
;
1188 for_each_cpu_mask(sibling
, cpu_core_map
[cpu
]) {
1189 cpu_clear(cpu
, cpu_core_map
[sibling
]);
1191 * last thread sibling in this cpu core going down
1193 if (cpus_weight(cpu_sibling_map
[cpu
]) == 1)
1194 c
[sibling
].booted_cores
--;
1197 for_each_cpu_mask(sibling
, cpu_sibling_map
[cpu
])
1198 cpu_clear(cpu
, cpu_sibling_map
[sibling
]);
1199 cpus_clear(cpu_sibling_map
[cpu
]);
1200 cpus_clear(cpu_core_map
[cpu
]);
1201 c
[cpu
].phys_proc_id
= 0;
1202 c
[cpu
].cpu_core_id
= 0;
1203 cpu_clear(cpu
, cpu_sibling_setup_map
);
1206 int __cpu_disable(void)
1208 cpumask_t map
= cpu_online_map
;
1209 int cpu
= smp_processor_id();
1212 * Perhaps use cpufreq to drop frequency, but that could go
1213 * into generic code.
1215 * We won't take down the boot processor on i386 due to some
1216 * interrupts only being able to be serviced by the BSP.
1217 * Especially so if we're not using an IOAPIC -zwane
1221 if (nmi_watchdog
== NMI_LOCAL_APIC
)
1222 stop_apic_nmi_watchdog(NULL
);
1224 /* Allow any queued timer interrupts to get serviced */
1227 local_irq_disable();
1229 remove_siblinginfo(cpu
);
1231 cpu_clear(cpu
, map
);
1233 /* It's now safe to remove this processor from the online map */
1234 cpu_clear(cpu
, cpu_online_map
);
1238 void __cpu_die(unsigned int cpu
)
1240 /* We don't do anything here: idle task is faking death itself. */
1243 for (i
= 0; i
< 10; i
++) {
1244 /* They ack this in play_dead by setting CPU_DEAD */
1245 if (per_cpu(cpu_state
, cpu
) == CPU_DEAD
) {
1246 printk ("CPU %d is now offline\n", cpu
);
1247 if (1 == num_online_cpus())
1248 alternatives_smp_switch(0);
1253 printk(KERN_ERR
"CPU %u didn't die...\n", cpu
);
1255 #else /* ... !CONFIG_HOTPLUG_CPU */
1256 int __cpu_disable(void)
1261 void __cpu_die(unsigned int cpu
)
1263 /* We said "no" in __cpu_disable */
1266 #endif /* CONFIG_HOTPLUG_CPU */
1268 int __cpuinit
native_cpu_up(unsigned int cpu
)
1270 unsigned long flags
;
1271 #ifdef CONFIG_HOTPLUG_CPU
1275 * We do warm boot only on cpus that had booted earlier
1276 * Otherwise cold boot is all handled from smp_boot_cpus().
1277 * cpu_callin_map is set during AP kickstart process. Its reset
1278 * when a cpu is taken offline from cpu_exit_clear().
1280 if (!cpu_isset(cpu
, cpu_callin_map
))
1281 ret
= __smp_prepare_cpu(cpu
);
1287 /* In case one didn't come up */
1288 if (!cpu_isset(cpu
, cpu_callin_map
)) {
1289 printk(KERN_DEBUG
"skipping cpu%d, didn't come online\n", cpu
);
1293 per_cpu(cpu_state
, cpu
) = CPU_UP_PREPARE
;
1294 /* Unleash the CPU! */
1295 cpu_set(cpu
, smp_commenced_mask
);
1298 * Check TSC synchronization with the AP (keep irqs disabled
1301 local_irq_save(flags
);
1302 check_tsc_sync_source(cpu
);
1303 local_irq_restore(flags
);
1305 while (!cpu_isset(cpu
, cpu_online_map
)) {
1307 touch_nmi_watchdog();
1313 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1315 #ifdef CONFIG_X86_IO_APIC
1316 setup_ioapic_dest();
1319 #ifndef CONFIG_HOTPLUG_CPU
1321 * Disable executability of the SMP trampoline:
1323 set_kernel_exec((unsigned long)trampoline_base
, trampoline_exec
);
1327 void __init
smp_intr_init(void)
1330 * IRQ0 must be given a fixed assignment and initialized,
1331 * because it's used before the IO-APIC is set up.
1333 set_intr_gate(FIRST_DEVICE_VECTOR
, interrupt
[0]);
1336 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1337 * IPI, driven by wakeup.
1339 set_intr_gate(RESCHEDULE_VECTOR
, reschedule_interrupt
);
1341 /* IPI for invalidation */
1342 set_intr_gate(INVALIDATE_TLB_VECTOR
, invalidate_interrupt
);
1344 /* IPI for generic function call */
1345 set_intr_gate(CALL_FUNCTION_VECTOR
, call_function_interrupt
);
1349 * If the BIOS enumerates physical processors before logical,
1350 * maxcpus=N at enumeration-time can be used to disable HT.
1352 static int __init
parse_maxcpus(char *arg
)
1354 extern unsigned int maxcpus
;
1356 maxcpus
= simple_strtoul(arg
, NULL
, 0);
1359 early_param("maxcpus", parse_maxcpus
);