4 * Copyright (C) 1999 Intel Corp.
5 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
6 * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
7 * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 1999 VA Linux Systems
10 * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
12 * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O
13 * APIC code. In particular, we now have separate
14 * handlers for edge and level triggered
16 * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
17 * allocation PCI to vector mapping, shared PCI
19 * 00/10/27 D. Mosberger Document things a bit more to make them more
20 * understandable. Clean up much of the old
22 * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts
23 * and fixes for ACPI S5(SoftOff) support.
24 * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT
25 * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt
26 * vectors in iosapic_set_affinity(),
27 * initializations for /proc/irq/#/smp_affinity
28 * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing.
29 * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq
30 * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to
31 * IOSAPIC mapping error
32 * 02/07/29 T. Kochi Allocate interrupt vectors dynamically
33 * 02/08/04 T. Kochi Cleaned up terminology (irq, global system
34 * interrupt, vector, etc.)
35 * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's
37 * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC.
38 * Remove iosapic_address & gsi_base from
39 * external interfaces. Rationalize
40 * __init/__devinit attributes.
41 * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004
42 * Updated to work with irq migration necessary
46 * Here is what the interrupt logic between a PCI device and the kernel looks
49 * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
50 * INTD). The device is uniquely identified by its bus-, and slot-number
51 * (the function number does not matter here because all functions share
52 * the same interrupt lines).
54 * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
55 * controller. Multiple interrupt lines may have to share the same
56 * IOSAPIC pin (if they're level triggered and use the same polarity).
57 * Each interrupt line has a unique Global System Interrupt (GSI) number
58 * which can be calculated as the sum of the controller's base GSI number
59 * and the IOSAPIC pin number to which the line connects.
61 * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
62 * IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then
65 * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is
66 * used as architecture-independent interrupt handling mechanism in Linux.
67 * As an IRQ is a number, we have to have
68 * IA-64 interrupt vector number <-> IRQ number mapping. On smaller
69 * systems, we use one-to-one mapping between IA-64 vector and IRQ. A
70 * platform can implement platform_irq_to_vector(irq) and
71 * platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
72 * Please see also arch/ia64/include/asm/hw_irq.h for those APIs.
74 * To sum up, there are three levels of mappings involved:
76 * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
78 * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
79 * describeinterrupts. Now we use "IRQ" only for Linux IRQ's. ISA IRQ
80 * (isa_irq) is the only exception in this source code.
83 #include <linux/acpi.h>
84 #include <linux/init.h>
85 #include <linux/irq.h>
86 #include <linux/kernel.h>
87 #include <linux/list.h>
88 #include <linux/pci.h>
89 #include <linux/slab.h>
90 #include <linux/smp.h>
91 #include <linux/string.h>
92 #include <linux/bootmem.h>
94 #include <asm/delay.h>
95 #include <asm/hw_irq.h>
97 #include <asm/iosapic.h>
98 #include <asm/machvec.h>
99 #include <asm/processor.h>
100 #include <asm/ptrace.h>
101 #include <asm/system.h>
103 #undef DEBUG_INTERRUPT_ROUTING
105 #ifdef DEBUG_INTERRUPT_ROUTING
106 #define DBG(fmt...) printk(fmt)
111 static DEFINE_SPINLOCK(iosapic_lock
);
114 * These tables map IA-64 vectors to the IOSAPIC pin that generates this
120 static struct iosapic
{
121 char __iomem
*addr
; /* base address of IOSAPIC */
122 unsigned int gsi_base
; /* GSI base */
123 unsigned short num_rte
; /* # of RTEs on this IOSAPIC */
124 int rtes_inuse
; /* # of RTEs in use on this IOSAPIC */
126 unsigned short node
; /* numa node association via pxm */
128 spinlock_t lock
; /* lock for indirect reg access */
129 } iosapic_lists
[NR_IOSAPICS
];
131 struct iosapic_rte_info
{
132 struct list_head rte_list
; /* RTEs sharing the same vector */
133 char rte_index
; /* IOSAPIC RTE index */
134 int refcnt
; /* reference counter */
135 struct iosapic
*iosapic
;
136 } ____cacheline_aligned
;
138 static struct iosapic_intr_info
{
139 struct list_head rtes
; /* RTEs using this vector (empty =>
140 * not an IOSAPIC interrupt) */
141 int count
; /* # of registered RTEs */
142 u32 low32
; /* current value of low word of
143 * Redirection table entry */
144 unsigned int dest
; /* destination CPU physical ID */
145 unsigned char dmode
: 3; /* delivery mode (see iosapic.h) */
146 unsigned char polarity
: 1; /* interrupt polarity
148 unsigned char trigger
: 1; /* trigger mode (see iosapic.h) */
149 } iosapic_intr_info
[NR_IRQS
];
151 static unsigned char pcat_compat __devinitdata
; /* 8259 compatibility flag */
154 iosapic_write(struct iosapic
*iosapic
, unsigned int reg
, u32 val
)
158 spin_lock_irqsave(&iosapic
->lock
, flags
);
159 __iosapic_write(iosapic
->addr
, reg
, val
);
160 spin_unlock_irqrestore(&iosapic
->lock
, flags
);
164 * Find an IOSAPIC associated with a GSI
167 find_iosapic (unsigned int gsi
)
171 for (i
= 0; i
< NR_IOSAPICS
; i
++) {
172 if ((unsigned) (gsi
- iosapic_lists
[i
].gsi_base
) <
173 iosapic_lists
[i
].num_rte
)
180 static inline int __gsi_to_irq(unsigned int gsi
)
183 struct iosapic_intr_info
*info
;
184 struct iosapic_rte_info
*rte
;
186 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
187 info
= &iosapic_intr_info
[irq
];
188 list_for_each_entry(rte
, &info
->rtes
, rte_list
)
189 if (rte
->iosapic
->gsi_base
+ rte
->rte_index
== gsi
)
196 gsi_to_irq (unsigned int gsi
)
201 spin_lock_irqsave(&iosapic_lock
, flags
);
202 irq
= __gsi_to_irq(gsi
);
203 spin_unlock_irqrestore(&iosapic_lock
, flags
);
207 static struct iosapic_rte_info
*find_rte(unsigned int irq
, unsigned int gsi
)
209 struct iosapic_rte_info
*rte
;
211 list_for_each_entry(rte
, &iosapic_intr_info
[irq
].rtes
, rte_list
)
212 if (rte
->iosapic
->gsi_base
+ rte
->rte_index
== gsi
)
218 set_rte (unsigned int gsi
, unsigned int irq
, unsigned int dest
, int mask
)
220 unsigned long pol
, trigger
, dmode
;
224 struct iosapic_rte_info
*rte
;
225 ia64_vector vector
= irq_to_vector(irq
);
227 DBG(KERN_DEBUG
"IOSAPIC: routing vector %d to 0x%x\n", vector
, dest
);
229 rte
= find_rte(irq
, gsi
);
231 return; /* not an IOSAPIC interrupt */
233 rte_index
= rte
->rte_index
;
234 pol
= iosapic_intr_info
[irq
].polarity
;
235 trigger
= iosapic_intr_info
[irq
].trigger
;
236 dmode
= iosapic_intr_info
[irq
].dmode
;
238 redir
= (dmode
== IOSAPIC_LOWEST_PRIORITY
) ? 1 : 0;
241 set_irq_affinity_info(irq
, (int)(dest
& 0xffff), redir
);
244 low32
= ((pol
<< IOSAPIC_POLARITY_SHIFT
) |
245 (trigger
<< IOSAPIC_TRIGGER_SHIFT
) |
246 (dmode
<< IOSAPIC_DELIVERY_SHIFT
) |
247 ((mask
? 1 : 0) << IOSAPIC_MASK_SHIFT
) |
250 /* dest contains both id and eid */
251 high32
= (dest
<< IOSAPIC_DEST_SHIFT
);
253 iosapic_write(rte
->iosapic
, IOSAPIC_RTE_HIGH(rte_index
), high32
);
254 iosapic_write(rte
->iosapic
, IOSAPIC_RTE_LOW(rte_index
), low32
);
255 iosapic_intr_info
[irq
].low32
= low32
;
256 iosapic_intr_info
[irq
].dest
= dest
;
260 nop (unsigned int irq
)
268 kexec_disable_iosapic(void)
270 struct iosapic_intr_info
*info
;
271 struct iosapic_rte_info
*rte
;
275 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
276 info
= &iosapic_intr_info
[irq
];
277 vec
= irq_to_vector(irq
);
278 list_for_each_entry(rte
, &info
->rtes
,
280 iosapic_write(rte
->iosapic
,
281 IOSAPIC_RTE_LOW(rte
->rte_index
),
283 iosapic_eoi(rte
->iosapic
->addr
, vec
);
290 mask_irq (unsigned int irq
)
294 struct iosapic_rte_info
*rte
;
296 if (!iosapic_intr_info
[irq
].count
)
297 return; /* not an IOSAPIC interrupt! */
299 /* set only the mask bit */
300 low32
= iosapic_intr_info
[irq
].low32
|= IOSAPIC_MASK
;
301 list_for_each_entry(rte
, &iosapic_intr_info
[irq
].rtes
, rte_list
) {
302 rte_index
= rte
->rte_index
;
303 iosapic_write(rte
->iosapic
, IOSAPIC_RTE_LOW(rte_index
), low32
);
308 unmask_irq (unsigned int irq
)
312 struct iosapic_rte_info
*rte
;
314 if (!iosapic_intr_info
[irq
].count
)
315 return; /* not an IOSAPIC interrupt! */
317 low32
= iosapic_intr_info
[irq
].low32
&= ~IOSAPIC_MASK
;
318 list_for_each_entry(rte
, &iosapic_intr_info
[irq
].rtes
, rte_list
) {
319 rte_index
= rte
->rte_index
;
320 iosapic_write(rte
->iosapic
, IOSAPIC_RTE_LOW(rte_index
), low32
);
326 iosapic_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
330 int cpu
, dest
, rte_index
;
331 int redir
= (irq
& IA64_IRQ_REDIRECTED
) ? 1 : 0;
332 struct iosapic_rte_info
*rte
;
333 struct iosapic
*iosapic
;
335 irq
&= (~IA64_IRQ_REDIRECTED
);
337 cpu
= cpumask_first_and(cpu_online_mask
, mask
);
338 if (cpu
>= nr_cpu_ids
)
341 if (irq_prepare_move(irq
, cpu
))
344 dest
= cpu_physical_id(cpu
);
346 if (!iosapic_intr_info
[irq
].count
)
347 return -1; /* not an IOSAPIC interrupt */
349 set_irq_affinity_info(irq
, dest
, redir
);
351 /* dest contains both id and eid */
352 high32
= dest
<< IOSAPIC_DEST_SHIFT
;
354 low32
= iosapic_intr_info
[irq
].low32
& ~(7 << IOSAPIC_DELIVERY_SHIFT
);
356 /* change delivery mode to lowest priority */
357 low32
|= (IOSAPIC_LOWEST_PRIORITY
<< IOSAPIC_DELIVERY_SHIFT
);
359 /* change delivery mode to fixed */
360 low32
|= (IOSAPIC_FIXED
<< IOSAPIC_DELIVERY_SHIFT
);
361 low32
&= IOSAPIC_VECTOR_MASK
;
362 low32
|= irq_to_vector(irq
);
364 iosapic_intr_info
[irq
].low32
= low32
;
365 iosapic_intr_info
[irq
].dest
= dest
;
366 list_for_each_entry(rte
, &iosapic_intr_info
[irq
].rtes
, rte_list
) {
367 iosapic
= rte
->iosapic
;
368 rte_index
= rte
->rte_index
;
369 iosapic_write(iosapic
, IOSAPIC_RTE_HIGH(rte_index
), high32
);
370 iosapic_write(iosapic
, IOSAPIC_RTE_LOW(rte_index
), low32
);
378 * Handlers for level-triggered interrupts.
382 iosapic_startup_level_irq (unsigned int irq
)
389 iosapic_unmask_level_irq (unsigned int irq
)
391 ia64_vector vec
= irq_to_vector(irq
);
392 struct iosapic_rte_info
*rte
;
393 int do_unmask_irq
= 0;
395 irq_complete_move(irq
);
396 if (unlikely(irq_desc
[irq
].status
& IRQ_MOVE_PENDING
)) {
402 list_for_each_entry(rte
, &iosapic_intr_info
[irq
].rtes
, rte_list
)
403 iosapic_eoi(rte
->iosapic
->addr
, vec
);
405 if (unlikely(do_unmask_irq
)) {
406 move_masked_irq(irq
);
411 #define iosapic_shutdown_level_irq mask_irq
412 #define iosapic_enable_level_irq unmask_irq
413 #define iosapic_disable_level_irq mask_irq
414 #define iosapic_ack_level_irq nop
416 static struct irq_chip irq_type_iosapic_level
= {
417 .name
= "IO-SAPIC-level",
418 .startup
= iosapic_startup_level_irq
,
419 .shutdown
= iosapic_shutdown_level_irq
,
420 .enable
= iosapic_enable_level_irq
,
421 .disable
= iosapic_disable_level_irq
,
422 .ack
= iosapic_ack_level_irq
,
424 .unmask
= iosapic_unmask_level_irq
,
425 .set_affinity
= iosapic_set_affinity
429 * Handlers for edge-triggered interrupts.
433 iosapic_startup_edge_irq (unsigned int irq
)
437 * IOSAPIC simply drops interrupts pended while the
438 * corresponding pin was masked, so we can't know if an
439 * interrupt is pending already. Let's hope not...
445 iosapic_ack_edge_irq (unsigned int irq
)
447 struct irq_desc
*idesc
= irq_desc
+ irq
;
449 irq_complete_move(irq
);
450 move_native_irq(irq
);
452 * Once we have recorded IRQ_PENDING already, we can mask the
453 * interrupt for real. This prevents IRQ storms from unhandled
456 if ((idesc
->status
& (IRQ_PENDING
|IRQ_DISABLED
)) ==
457 (IRQ_PENDING
|IRQ_DISABLED
))
461 #define iosapic_enable_edge_irq unmask_irq
462 #define iosapic_disable_edge_irq nop
463 #define iosapic_end_edge_irq nop
465 static struct irq_chip irq_type_iosapic_edge
= {
466 .name
= "IO-SAPIC-edge",
467 .startup
= iosapic_startup_edge_irq
,
468 .shutdown
= iosapic_disable_edge_irq
,
469 .enable
= iosapic_enable_edge_irq
,
470 .disable
= iosapic_disable_edge_irq
,
471 .ack
= iosapic_ack_edge_irq
,
472 .end
= iosapic_end_edge_irq
,
474 .unmask
= unmask_irq
,
475 .set_affinity
= iosapic_set_affinity
479 iosapic_version (char __iomem
*addr
)
482 * IOSAPIC Version Register return 32 bit structure like:
484 * unsigned int version : 8;
485 * unsigned int reserved1 : 8;
486 * unsigned int max_redir : 8;
487 * unsigned int reserved2 : 8;
490 return __iosapic_read(addr
, IOSAPIC_VERSION
);
493 static int iosapic_find_sharable_irq(unsigned long trigger
, unsigned long pol
)
495 int i
, irq
= -ENOSPC
, min_count
= -1;
496 struct iosapic_intr_info
*info
;
499 * shared vectors for edge-triggered interrupts are not
502 if (trigger
== IOSAPIC_EDGE
)
505 for (i
= 0; i
< NR_IRQS
; i
++) {
506 info
= &iosapic_intr_info
[i
];
507 if (info
->trigger
== trigger
&& info
->polarity
== pol
&&
508 (info
->dmode
== IOSAPIC_FIXED
||
509 info
->dmode
== IOSAPIC_LOWEST_PRIORITY
) &&
510 can_request_irq(i
, IRQF_SHARED
)) {
511 if (min_count
== -1 || info
->count
< min_count
) {
513 min_count
= info
->count
;
521 * if the given vector is already owned by other,
522 * assign a new vector for the other and make the vector available
525 iosapic_reassign_vector (int irq
)
529 if (iosapic_intr_info
[irq
].count
) {
530 new_irq
= create_irq();
532 panic("%s: out of interrupt vectors!\n", __func__
);
533 printk(KERN_INFO
"Reassigning vector %d to %d\n",
534 irq_to_vector(irq
), irq_to_vector(new_irq
));
535 memcpy(&iosapic_intr_info
[new_irq
], &iosapic_intr_info
[irq
],
536 sizeof(struct iosapic_intr_info
));
537 INIT_LIST_HEAD(&iosapic_intr_info
[new_irq
].rtes
);
538 list_move(iosapic_intr_info
[irq
].rtes
.next
,
539 &iosapic_intr_info
[new_irq
].rtes
);
540 memset(&iosapic_intr_info
[irq
], 0,
541 sizeof(struct iosapic_intr_info
));
542 iosapic_intr_info
[irq
].low32
= IOSAPIC_MASK
;
543 INIT_LIST_HEAD(&iosapic_intr_info
[irq
].rtes
);
547 static inline int irq_is_shared (int irq
)
549 return (iosapic_intr_info
[irq
].count
> 1);
553 ia64_native_iosapic_get_irq_chip(unsigned long trigger
)
555 if (trigger
== IOSAPIC_EDGE
)
556 return &irq_type_iosapic_edge
;
558 return &irq_type_iosapic_level
;
562 register_intr (unsigned int gsi
, int irq
, unsigned char delivery
,
563 unsigned long polarity
, unsigned long trigger
)
565 struct irq_desc
*idesc
;
566 struct irq_chip
*irq_type
;
568 struct iosapic_rte_info
*rte
;
570 index
= find_iosapic(gsi
);
572 printk(KERN_WARNING
"%s: No IOSAPIC for GSI %u\n",
577 rte
= find_rte(irq
, gsi
);
579 rte
= kzalloc(sizeof (*rte
), GFP_ATOMIC
);
581 printk(KERN_WARNING
"%s: cannot allocate memory\n",
586 rte
->iosapic
= &iosapic_lists
[index
];
587 rte
->rte_index
= gsi
- rte
->iosapic
->gsi_base
;
589 list_add_tail(&rte
->rte_list
, &iosapic_intr_info
[irq
].rtes
);
590 iosapic_intr_info
[irq
].count
++;
591 iosapic_lists
[index
].rtes_inuse
++;
593 else if (rte
->refcnt
== NO_REF_RTE
) {
594 struct iosapic_intr_info
*info
= &iosapic_intr_info
[irq
];
595 if (info
->count
> 0 &&
596 (info
->trigger
!= trigger
|| info
->polarity
!= polarity
)){
598 "%s: cannot override the interrupt\n",
603 iosapic_intr_info
[irq
].count
++;
604 iosapic_lists
[index
].rtes_inuse
++;
607 iosapic_intr_info
[irq
].polarity
= polarity
;
608 iosapic_intr_info
[irq
].dmode
= delivery
;
609 iosapic_intr_info
[irq
].trigger
= trigger
;
611 irq_type
= iosapic_get_irq_chip(trigger
);
613 idesc
= irq_desc
+ irq
;
614 if (irq_type
!= NULL
&& idesc
->chip
!= irq_type
) {
615 if (idesc
->chip
!= &no_irq_chip
)
617 "%s: changing vector %d from %s to %s\n",
618 __func__
, irq_to_vector(irq
),
619 idesc
->chip
->name
, irq_type
->name
);
620 idesc
->chip
= irq_type
;
622 if (trigger
== IOSAPIC_EDGE
)
623 __set_irq_handler_unlocked(irq
, handle_edge_irq
);
625 __set_irq_handler_unlocked(irq
, handle_level_irq
);
630 get_target_cpu (unsigned int gsi
, int irq
)
634 extern int cpe_vector
;
635 cpumask_t domain
= irq_to_domain(irq
);
638 * In case of vector shared by multiple RTEs, all RTEs that
639 * share the vector need to use the same destination CPU.
641 if (iosapic_intr_info
[irq
].count
)
642 return iosapic_intr_info
[irq
].dest
;
645 * If the platform supports redirection via XTP, let it
646 * distribute interrupts.
648 if (smp_int_redirect
& SMP_IRQ_REDIRECTION
)
649 return cpu_physical_id(smp_processor_id());
652 * Some interrupts (ACPI SCI, for instance) are registered
653 * before the BSP is marked as online.
655 if (!cpu_online(smp_processor_id()))
656 return cpu_physical_id(smp_processor_id());
659 if (cpe_vector
> 0 && irq_to_vector(irq
) == IA64_CPEP_VECTOR
)
660 return get_cpei_target_cpu();
665 int num_cpus
, cpu_index
, iosapic_index
, numa_cpu
, i
= 0;
666 const struct cpumask
*cpu_mask
;
668 iosapic_index
= find_iosapic(gsi
);
669 if (iosapic_index
< 0 ||
670 iosapic_lists
[iosapic_index
].node
== MAX_NUMNODES
)
671 goto skip_numa_setup
;
673 cpu_mask
= cpumask_of_node(iosapic_lists
[iosapic_index
].node
);
675 for_each_cpu_and(numa_cpu
, cpu_mask
, &domain
) {
676 if (cpu_online(numa_cpu
))
681 goto skip_numa_setup
;
683 /* Use irq assignment to distribute across cpus in node */
684 cpu_index
= irq
% num_cpus
;
686 for_each_cpu_and(numa_cpu
, cpu_mask
, &domain
)
687 if (cpu_online(numa_cpu
) && i
++ >= cpu_index
)
690 if (numa_cpu
< nr_cpu_ids
)
691 return cpu_physical_id(numa_cpu
);
696 * Otherwise, round-robin interrupt vectors across all the
697 * processors. (It'd be nice if we could be smarter in the
701 if (++cpu
>= nr_cpu_ids
)
703 } while (!cpu_online(cpu
) || !cpu_isset(cpu
, domain
));
705 return cpu_physical_id(cpu
);
706 #else /* CONFIG_SMP */
707 return cpu_physical_id(smp_processor_id());
711 static inline unsigned char choose_dmode(void)
714 if (smp_int_redirect
& SMP_IRQ_REDIRECTION
)
715 return IOSAPIC_LOWEST_PRIORITY
;
717 return IOSAPIC_FIXED
;
721 * ACPI can describe IOSAPIC interrupts via static tables and namespace
722 * methods. This provides an interface to register those interrupts and
723 * program the IOSAPIC RTE.
726 iosapic_register_intr (unsigned int gsi
,
727 unsigned long polarity
, unsigned long trigger
)
729 int irq
, mask
= 1, err
;
732 struct iosapic_rte_info
*rte
;
737 * If this GSI has already been registered (i.e., it's a
738 * shared interrupt, or we lost a race to register it),
739 * don't touch the RTE.
741 spin_lock_irqsave(&iosapic_lock
, flags
);
742 irq
= __gsi_to_irq(gsi
);
744 rte
= find_rte(irq
, gsi
);
745 if(iosapic_intr_info
[irq
].count
== 0) {
746 assign_irq_vector(irq
);
747 dynamic_irq_init(irq
);
748 } else if (rte
->refcnt
!= NO_REF_RTE
) {
750 goto unlock_iosapic_lock
;
755 /* If vector is running out, we try to find a sharable vector */
757 irq
= iosapic_find_sharable_irq(trigger
, polarity
);
759 goto unlock_iosapic_lock
;
762 raw_spin_lock(&irq_desc
[irq
].lock
);
763 dest
= get_target_cpu(gsi
, irq
);
764 dmode
= choose_dmode();
765 err
= register_intr(gsi
, irq
, dmode
, polarity
, trigger
);
767 raw_spin_unlock(&irq_desc
[irq
].lock
);
769 goto unlock_iosapic_lock
;
773 * If the vector is shared and already unmasked for other
774 * interrupt sources, don't mask it.
776 low32
= iosapic_intr_info
[irq
].low32
;
777 if (irq_is_shared(irq
) && !(low32
& IOSAPIC_MASK
))
779 set_rte(gsi
, irq
, dest
, mask
);
781 printk(KERN_INFO
"GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
782 gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
783 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
784 cpu_logical_id(dest
), dest
, irq_to_vector(irq
));
786 raw_spin_unlock(&irq_desc
[irq
].lock
);
788 spin_unlock_irqrestore(&iosapic_lock
, flags
);
793 iosapic_unregister_intr (unsigned int gsi
)
797 struct irq_desc
*idesc
;
799 unsigned long trigger
, polarity
;
801 struct iosapic_rte_info
*rte
;
804 * If the irq associated with the gsi is not found,
805 * iosapic_unregister_intr() is unbalanced. We need to check
806 * this again after getting locks.
808 irq
= gsi_to_irq(gsi
);
810 printk(KERN_ERR
"iosapic_unregister_intr(%u) unbalanced\n",
816 spin_lock_irqsave(&iosapic_lock
, flags
);
817 if ((rte
= find_rte(irq
, gsi
)) == NULL
) {
818 printk(KERN_ERR
"iosapic_unregister_intr(%u) unbalanced\n",
824 if (--rte
->refcnt
> 0)
827 idesc
= irq_desc
+ irq
;
828 rte
->refcnt
= NO_REF_RTE
;
830 /* Mask the interrupt */
831 low32
= iosapic_intr_info
[irq
].low32
| IOSAPIC_MASK
;
832 iosapic_write(rte
->iosapic
, IOSAPIC_RTE_LOW(rte
->rte_index
), low32
);
834 iosapic_intr_info
[irq
].count
--;
835 index
= find_iosapic(gsi
);
836 iosapic_lists
[index
].rtes_inuse
--;
837 WARN_ON(iosapic_lists
[index
].rtes_inuse
< 0);
839 trigger
= iosapic_intr_info
[irq
].trigger
;
840 polarity
= iosapic_intr_info
[irq
].polarity
;
841 dest
= iosapic_intr_info
[irq
].dest
;
843 "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
844 gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
845 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
846 cpu_logical_id(dest
), dest
, irq_to_vector(irq
));
848 if (iosapic_intr_info
[irq
].count
== 0) {
851 cpumask_setall(idesc
->affinity
);
853 /* Clear the interrupt information */
854 iosapic_intr_info
[irq
].dest
= 0;
855 iosapic_intr_info
[irq
].dmode
= 0;
856 iosapic_intr_info
[irq
].polarity
= 0;
857 iosapic_intr_info
[irq
].trigger
= 0;
858 iosapic_intr_info
[irq
].low32
|= IOSAPIC_MASK
;
860 /* Destroy and reserve IRQ */
861 destroy_and_reserve_irq(irq
);
864 spin_unlock_irqrestore(&iosapic_lock
, flags
);
868 * ACPI calls this when it finds an entry for a platform interrupt.
871 iosapic_register_platform_intr (u32 int_type
, unsigned int gsi
,
872 int iosapic_vector
, u16 eid
, u16 id
,
873 unsigned long polarity
, unsigned long trigger
)
875 static const char * const name
[] = {"unknown", "PMI", "INIT", "CPEI"};
876 unsigned char delivery
;
877 int irq
, vector
, mask
= 0;
878 unsigned int dest
= ((id
<< 8) | eid
) & 0xffff;
881 case ACPI_INTERRUPT_PMI
:
882 irq
= vector
= iosapic_vector
;
883 bind_irq_vector(irq
, vector
, CPU_MASK_ALL
);
885 * since PMI vector is alloc'd by FW(ACPI) not by kernel,
886 * we need to make sure the vector is available
888 iosapic_reassign_vector(irq
);
889 delivery
= IOSAPIC_PMI
;
891 case ACPI_INTERRUPT_INIT
:
894 panic("%s: out of interrupt vectors!\n", __func__
);
895 vector
= irq_to_vector(irq
);
896 delivery
= IOSAPIC_INIT
;
898 case ACPI_INTERRUPT_CPEI
:
899 irq
= vector
= IA64_CPE_VECTOR
;
900 BUG_ON(bind_irq_vector(irq
, vector
, CPU_MASK_ALL
));
901 delivery
= IOSAPIC_FIXED
;
905 printk(KERN_ERR
"%s: invalid int type 0x%x\n", __func__
,
910 register_intr(gsi
, irq
, delivery
, polarity
, trigger
);
913 "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
915 int_type
< ARRAY_SIZE(name
) ? name
[int_type
] : "unknown",
916 int_type
, gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
917 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
918 cpu_logical_id(dest
), dest
, vector
);
920 set_rte(gsi
, irq
, dest
, mask
);
925 * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
928 iosapic_override_isa_irq (unsigned int isa_irq
, unsigned int gsi
,
929 unsigned long polarity
,
930 unsigned long trigger
)
933 unsigned int dest
= cpu_physical_id(smp_processor_id());
936 irq
= vector
= isa_irq_to_vector(isa_irq
);
937 BUG_ON(bind_irq_vector(irq
, vector
, CPU_MASK_ALL
));
938 dmode
= choose_dmode();
939 register_intr(gsi
, irq
, dmode
, polarity
, trigger
);
941 DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
942 isa_irq
, gsi
, trigger
== IOSAPIC_EDGE
? "edge" : "level",
943 polarity
== IOSAPIC_POL_HIGH
? "high" : "low",
944 cpu_logical_id(dest
), dest
, vector
);
946 set_rte(gsi
, irq
, dest
, 1);
950 ia64_native_iosapic_pcat_compat_init(void)
954 * Disable the compatibility mode interrupts (8259 style),
955 * needs IN/OUT support enabled.
958 "%s: Disabling PC-AT compatible 8259 interrupts\n",
966 iosapic_system_init (int system_pcat_compat
)
970 for (irq
= 0; irq
< NR_IRQS
; ++irq
) {
971 iosapic_intr_info
[irq
].low32
= IOSAPIC_MASK
;
973 INIT_LIST_HEAD(&iosapic_intr_info
[irq
].rtes
);
975 iosapic_intr_info
[irq
].count
= 0;
978 pcat_compat
= system_pcat_compat
;
980 iosapic_pcat_compat_init();
988 for (index
= 0; index
< NR_IOSAPICS
; index
++)
989 if (!iosapic_lists
[index
].addr
)
992 printk(KERN_WARNING
"%s: failed to allocate iosapic\n", __func__
);
997 iosapic_free (int index
)
999 memset(&iosapic_lists
[index
], 0, sizeof(iosapic_lists
[0]));
1003 iosapic_check_gsi_range (unsigned int gsi_base
, unsigned int ver
)
1006 unsigned int gsi_end
, base
, end
;
1008 /* check gsi range */
1009 gsi_end
= gsi_base
+ ((ver
>> 16) & 0xff);
1010 for (index
= 0; index
< NR_IOSAPICS
; index
++) {
1011 if (!iosapic_lists
[index
].addr
)
1014 base
= iosapic_lists
[index
].gsi_base
;
1015 end
= base
+ iosapic_lists
[index
].num_rte
- 1;
1017 if (gsi_end
< base
|| end
< gsi_base
)
1026 iosapic_init (unsigned long phys_addr
, unsigned int gsi_base
)
1028 int num_rte
, err
, index
;
1029 unsigned int isa_irq
, ver
;
1031 unsigned long flags
;
1033 spin_lock_irqsave(&iosapic_lock
, flags
);
1034 index
= find_iosapic(gsi_base
);
1036 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1040 addr
= ioremap(phys_addr
, 0);
1042 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1045 ver
= iosapic_version(addr
);
1046 if ((err
= iosapic_check_gsi_range(gsi_base
, ver
))) {
1048 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1053 * The MAX_REDIR register holds the highest input pin number
1054 * (starting from 0). We add 1 so that we can use it for
1055 * number of pins (= RTEs)
1057 num_rte
= ((ver
>> 16) & 0xff) + 1;
1059 index
= iosapic_alloc();
1060 iosapic_lists
[index
].addr
= addr
;
1061 iosapic_lists
[index
].gsi_base
= gsi_base
;
1062 iosapic_lists
[index
].num_rte
= num_rte
;
1064 iosapic_lists
[index
].node
= MAX_NUMNODES
;
1066 spin_lock_init(&iosapic_lists
[index
].lock
);
1067 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1069 if ((gsi_base
== 0) && pcat_compat
) {
1071 * Map the legacy ISA devices into the IOSAPIC data. Some of
1072 * these may get reprogrammed later on with data from the ACPI
1073 * Interrupt Source Override table.
1075 for (isa_irq
= 0; isa_irq
< 16; ++isa_irq
)
1076 iosapic_override_isa_irq(isa_irq
, isa_irq
,
1083 #ifdef CONFIG_HOTPLUG
1085 iosapic_remove (unsigned int gsi_base
)
1088 unsigned long flags
;
1090 spin_lock_irqsave(&iosapic_lock
, flags
);
1091 index
= find_iosapic(gsi_base
);
1093 printk(KERN_WARNING
"%s: No IOSAPIC for GSI base %u\n",
1094 __func__
, gsi_base
);
1098 if (iosapic_lists
[index
].rtes_inuse
) {
1100 printk(KERN_WARNING
"%s: IOSAPIC for GSI base %u is busy\n",
1101 __func__
, gsi_base
);
1105 iounmap(iosapic_lists
[index
].addr
);
1106 iosapic_free(index
);
1108 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1111 #endif /* CONFIG_HOTPLUG */
1115 map_iosapic_to_node(unsigned int gsi_base
, int node
)
1119 index
= find_iosapic(gsi_base
);
1121 printk(KERN_WARNING
"%s: No IOSAPIC for GSI %u\n",
1122 __func__
, gsi_base
);
1125 iosapic_lists
[index
].node
= node
;