4 * Copyright (C) 1999 Intel Corp.
5 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
6 * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
7 * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 1999 VA Linux Systems
10 * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
12 * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O APIC code.
13 * In particular, we now have separate handlers for edge
14 * and level triggered interrupts.
15 * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector allocation
16 * PCI to vector mapping, shared PCI interrupts.
17 * 00/10/27 D. Mosberger Document things a bit more to make them more understandable.
18 * Clean up much of the old IOSAPIC cruft.
19 * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts and fixes for
20 * ACPI S5(SoftOff) support.
21 * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT
22 * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt vectors in
23 * iosapic_set_affinity(), initializations for
24 * /proc/irq/#/smp_affinity
25 * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing.
26 * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq
27 * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to IOSAPIC mapping
29 * 02/07/29 T. Kochi Allocate interrupt vectors dynamically
30 * 02/08/04 T. Kochi Cleaned up terminology (irq, global system interrupt, vector, etc.)
31 * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's pci_irq code.
32 * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC.
33 * Remove iosapic_address & gsi_base from external interfaces.
34 * Rationalize __init/__devinit attributes.
35 * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004
36 * Updated to work with irq migration necessary for CPU Hotplug
39 * Here is what the interrupt logic between a PCI device and the kernel looks like:
41 * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC, INTD). The
42 * device is uniquely identified by its bus--, and slot-number (the function
43 * number does not matter here because all functions share the same interrupt
46 * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC controller.
47 * Multiple interrupt lines may have to share the same IOSAPIC pin (if they're level
48 * triggered and use the same polarity). Each interrupt line has a unique Global
49 * System Interrupt (GSI) number which can be calculated as the sum of the controller's
50 * base GSI number and the IOSAPIC pin number to which the line connects.
52 * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the IOSAPIC pin
53 * into the IA-64 interrupt vector. This interrupt vector is then sent to the CPU.
55 * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is used as
56 * architecture-independent interrupt handling mechanism in Linux. As an
57 * IRQ is a number, we have to have IA-64 interrupt vector number <-> IRQ number
58 * mapping. On smaller systems, we use one-to-one mapping between IA-64 vector and
59 * IRQ. A platform can implement platform_irq_to_vector(irq) and
60 * platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
61 * Please see also include/asm-ia64/hw_irq.h for those APIs.
63 * To sum up, there are three levels of mappings involved:
65 * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
67 * Note: The term "IRQ" is loosely used everywhere in Linux kernel to describe interrupts.
68 * Now we use "IRQ" only for Linux IRQ's. ISA IRQ (isa_irq) is the only exception in this
71 #include <linux/config.h>
73 #include <linux/acpi.h>
74 #include <linux/init.h>
75 #include <linux/irq.h>
76 #include <linux/kernel.h>
77 #include <linux/list.h>
78 #include <linux/pci.h>
79 #include <linux/smp.h>
80 #include <linux/smp_lock.h>
81 #include <linux/string.h>
82 #include <linux/bootmem.h>
84 #include <asm/delay.h>
85 #include <asm/hw_irq.h>
87 #include <asm/iosapic.h>
88 #include <asm/machvec.h>
89 #include <asm/processor.h>
90 #include <asm/ptrace.h>
91 #include <asm/system.h>
94 #undef DEBUG_INTERRUPT_ROUTING
96 #ifdef DEBUG_INTERRUPT_ROUTING
97 #define DBG(fmt...) printk(fmt)
102 #define NR_PREALLOCATE_RTE_ENTRIES (PAGE_SIZE / sizeof(struct iosapic_rte_info))
103 #define RTE_PREALLOCATED (1)
105 static DEFINE_SPINLOCK(iosapic_lock
);
107 /* These tables map IA-64 vectors to the IOSAPIC pin that generates this vector. */
109 struct iosapic_rte_info
{
110 struct list_head rte_list
; /* node in list of RTEs sharing the same vector */
111 char __iomem
*addr
; /* base address of IOSAPIC */
112 unsigned int gsi_base
; /* first GSI assigned to this IOSAPIC */
113 char rte_index
; /* IOSAPIC RTE index */
114 int refcnt
; /* reference counter */
115 unsigned int flags
; /* flags */
116 } ____cacheline_aligned
;
118 static struct iosapic_intr_info
{
119 struct list_head rtes
; /* RTEs using this vector (empty => not an IOSAPIC interrupt) */
120 int count
; /* # of RTEs that shares this vector */
121 u32 low32
; /* current value of low word of Redirection table entry */
122 unsigned int dest
; /* destination CPU physical ID */
123 unsigned char dmode
: 3; /* delivery mode (see iosapic.h) */
124 unsigned char polarity
: 1; /* interrupt polarity (see iosapic.h) */
125 unsigned char trigger
: 1; /* trigger mode (see iosapic.h) */
126 } iosapic_intr_info
[IA64_NUM_VECTORS
];
128 static struct iosapic
{
129 char __iomem
*addr
; /* base address of IOSAPIC */
130 unsigned int gsi_base
; /* first GSI assigned to this IOSAPIC */
131 unsigned short num_rte
; /* number of RTE in this IOSAPIC */
132 int rtes_inuse
; /* # of RTEs in use on this IOSAPIC */
134 unsigned short node
; /* numa node association via pxm */
136 } iosapic_lists
[NR_IOSAPICS
];
138 static unsigned char pcat_compat __devinitdata
; /* 8259 compatibility flag */
140 static int iosapic_kmalloc_ok
;
141 static LIST_HEAD(free_rte_list
);
144 * Find an IOSAPIC associated with a GSI
147 find_iosapic (unsigned int gsi
)
151 for (i
= 0; i
< NR_IOSAPICS
; i
++) {
152 if ((unsigned) (gsi
- iosapic_lists
[i
].gsi_base
) < iosapic_lists
[i
].num_rte
)
160 _gsi_to_vector (unsigned int gsi
)
162 struct iosapic_intr_info
*info
;
163 struct iosapic_rte_info
*rte
;
165 for (info
= iosapic_intr_info
; info
< iosapic_intr_info
+ IA64_NUM_VECTORS
; ++info
)
166 list_for_each_entry(rte
, &info
->rtes
, rte_list
)
167 if (rte
->gsi_base
+ rte
->rte_index
== gsi
)
168 return info
- iosapic_intr_info
;
173 * Translate GSI number to the corresponding IA-64 interrupt vector. If no
174 * entry exists, return -1.
177 gsi_to_vector (unsigned int gsi
)
179 return _gsi_to_vector(gsi
);
183 gsi_to_irq (unsigned int gsi
)
188 * XXX fix me: this assumes an identity mapping vetween IA-64 vector and Linux irq
191 spin_lock_irqsave(&iosapic_lock
, flags
);
193 irq
= _gsi_to_vector(gsi
);
195 spin_unlock_irqrestore(&iosapic_lock
, flags
);
200 static struct iosapic_rte_info
*gsi_vector_to_rte(unsigned int gsi
, unsigned int vec
)
202 struct iosapic_rte_info
*rte
;
204 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
, rte_list
)
205 if (rte
->gsi_base
+ rte
->rte_index
== gsi
)
211 set_rte (unsigned int gsi
, unsigned int vector
, unsigned int dest
, int mask
)
213 unsigned long pol
, trigger
, dmode
;
218 struct iosapic_rte_info
*rte
;
220 DBG(KERN_DEBUG
"IOSAPIC: routing vector %d to 0x%x\n", vector
, dest
);
222 rte
= gsi_vector_to_rte(gsi
, vector
);
224 return; /* not an IOSAPIC interrupt */
226 rte_index
= rte
->rte_index
;
228 pol
= iosapic_intr_info
[vector
].polarity
;
229 trigger
= iosapic_intr_info
[vector
].trigger
;
230 dmode
= iosapic_intr_info
[vector
].dmode
;
232 redir
= (dmode
== IOSAPIC_LOWEST_PRIORITY
) ? 1 : 0;
238 for (irq
= 0; irq
< NR_IRQS
; ++irq
)
239 if (irq_to_vector(irq
) == vector
) {
240 set_irq_affinity_info(irq
, (int)(dest
& 0xffff), redir
);
246 low32
= ((pol
<< IOSAPIC_POLARITY_SHIFT
) |
247 (trigger
<< IOSAPIC_TRIGGER_SHIFT
) |
248 (dmode
<< IOSAPIC_DELIVERY_SHIFT
) |
249 ((mask
? 1 : 0) << IOSAPIC_MASK_SHIFT
) |
252 /* dest contains both id and eid */
253 high32
= (dest
<< IOSAPIC_DEST_SHIFT
);
255 iosapic_write(addr
, IOSAPIC_RTE_HIGH(rte_index
), high32
);
256 iosapic_write(addr
, IOSAPIC_RTE_LOW(rte_index
), low32
);
257 iosapic_intr_info
[vector
].low32
= low32
;
258 iosapic_intr_info
[vector
].dest
= dest
;
262 nop (unsigned int vector
)
268 mask_irq (unsigned int irq
)
274 ia64_vector vec
= irq_to_vector(irq
);
275 struct iosapic_rte_info
*rte
;
277 if (list_empty(&iosapic_intr_info
[vec
].rtes
))
278 return; /* not an IOSAPIC interrupt! */
280 spin_lock_irqsave(&iosapic_lock
, flags
);
282 /* set only the mask bit */
283 low32
= iosapic_intr_info
[vec
].low32
|= IOSAPIC_MASK
;
284 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
, rte_list
) {
286 rte_index
= rte
->rte_index
;
287 iosapic_write(addr
, IOSAPIC_RTE_LOW(rte_index
), low32
);
290 spin_unlock_irqrestore(&iosapic_lock
, flags
);
294 unmask_irq (unsigned int irq
)
300 ia64_vector vec
= irq_to_vector(irq
);
301 struct iosapic_rte_info
*rte
;
303 if (list_empty(&iosapic_intr_info
[vec
].rtes
))
304 return; /* not an IOSAPIC interrupt! */
306 spin_lock_irqsave(&iosapic_lock
, flags
);
308 low32
= iosapic_intr_info
[vec
].low32
&= ~IOSAPIC_MASK
;
309 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
, rte_list
) {
311 rte_index
= rte
->rte_index
;
312 iosapic_write(addr
, IOSAPIC_RTE_LOW(rte_index
), low32
);
315 spin_unlock_irqrestore(&iosapic_lock
, flags
);
320 iosapic_set_affinity (unsigned int irq
, cpumask_t mask
)
327 int redir
= (irq
& IA64_IRQ_REDIRECTED
) ? 1 : 0;
329 struct iosapic_rte_info
*rte
;
331 irq
&= (~IA64_IRQ_REDIRECTED
);
332 vec
= irq_to_vector(irq
);
334 if (cpus_empty(mask
))
337 dest
= cpu_physical_id(first_cpu(mask
));
339 if (list_empty(&iosapic_intr_info
[vec
].rtes
))
340 return; /* not an IOSAPIC interrupt */
342 set_irq_affinity_info(irq
, dest
, redir
);
344 /* dest contains both id and eid */
345 high32
= dest
<< IOSAPIC_DEST_SHIFT
;
347 spin_lock_irqsave(&iosapic_lock
, flags
);
349 low32
= iosapic_intr_info
[vec
].low32
& ~(7 << IOSAPIC_DELIVERY_SHIFT
);
352 /* change delivery mode to lowest priority */
353 low32
|= (IOSAPIC_LOWEST_PRIORITY
<< IOSAPIC_DELIVERY_SHIFT
);
355 /* change delivery mode to fixed */
356 low32
|= (IOSAPIC_FIXED
<< IOSAPIC_DELIVERY_SHIFT
);
358 iosapic_intr_info
[vec
].low32
= low32
;
359 iosapic_intr_info
[vec
].dest
= dest
;
360 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
, rte_list
) {
362 rte_index
= rte
->rte_index
;
363 iosapic_write(addr
, IOSAPIC_RTE_HIGH(rte_index
), high32
);
364 iosapic_write(addr
, IOSAPIC_RTE_LOW(rte_index
), low32
);
367 spin_unlock_irqrestore(&iosapic_lock
, flags
);
372 * Handlers for level-triggered interrupts.
376 iosapic_startup_level_irq (unsigned int irq
)
383 iosapic_end_level_irq (unsigned int irq
)
385 ia64_vector vec
= irq_to_vector(irq
);
386 struct iosapic_rte_info
*rte
;
389 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
, rte_list
)
390 iosapic_eoi(rte
->addr
, vec
);
393 #define iosapic_shutdown_level_irq mask_irq
394 #define iosapic_enable_level_irq unmask_irq
395 #define iosapic_disable_level_irq mask_irq
396 #define iosapic_ack_level_irq nop
398 struct hw_interrupt_type irq_type_iosapic_level
= {
399 .typename
= "IO-SAPIC-level",
400 .startup
= iosapic_startup_level_irq
,
401 .shutdown
= iosapic_shutdown_level_irq
,
402 .enable
= iosapic_enable_level_irq
,
403 .disable
= iosapic_disable_level_irq
,
404 .ack
= iosapic_ack_level_irq
,
405 .end
= iosapic_end_level_irq
,
406 .set_affinity
= iosapic_set_affinity
410 * Handlers for edge-triggered interrupts.
414 iosapic_startup_edge_irq (unsigned int irq
)
418 * IOSAPIC simply drops interrupts pended while the
419 * corresponding pin was masked, so we can't know if an
420 * interrupt is pending already. Let's hope not...
426 iosapic_ack_edge_irq (unsigned int irq
)
428 irq_desc_t
*idesc
= irq_descp(irq
);
432 * Once we have recorded IRQ_PENDING already, we can mask the
433 * interrupt for real. This prevents IRQ storms from unhandled
436 if ((idesc
->status
& (IRQ_PENDING
|IRQ_DISABLED
)) == (IRQ_PENDING
|IRQ_DISABLED
))
440 #define iosapic_enable_edge_irq unmask_irq
441 #define iosapic_disable_edge_irq nop
442 #define iosapic_end_edge_irq nop
444 struct hw_interrupt_type irq_type_iosapic_edge
= {
445 .typename
= "IO-SAPIC-edge",
446 .startup
= iosapic_startup_edge_irq
,
447 .shutdown
= iosapic_disable_edge_irq
,
448 .enable
= iosapic_enable_edge_irq
,
449 .disable
= iosapic_disable_edge_irq
,
450 .ack
= iosapic_ack_edge_irq
,
451 .end
= iosapic_end_edge_irq
,
452 .set_affinity
= iosapic_set_affinity
456 iosapic_version (char __iomem
*addr
)
459 * IOSAPIC Version Register return 32 bit structure like:
461 * unsigned int version : 8;
462 * unsigned int reserved1 : 8;
463 * unsigned int max_redir : 8;
464 * unsigned int reserved2 : 8;
467 return iosapic_read(addr
, IOSAPIC_VERSION
);
470 static int iosapic_find_sharable_vector (unsigned long trigger
, unsigned long pol
)
472 int i
, vector
= -1, min_count
= -1;
473 struct iosapic_intr_info
*info
;
476 * shared vectors for edge-triggered interrupts are not
479 if (trigger
== IOSAPIC_EDGE
)
482 for (i
= IA64_FIRST_DEVICE_VECTOR
; i
<= IA64_LAST_DEVICE_VECTOR
; i
++) {
483 info
= &iosapic_intr_info
[i
];
484 if (info
->trigger
== trigger
&& info
->polarity
== pol
&&
485 (info
->dmode
== IOSAPIC_FIXED
|| info
->dmode
== IOSAPIC_LOWEST_PRIORITY
)) {
486 if (min_count
== -1 || info
->count
< min_count
) {
488 min_count
= info
->count
;
497 * if the given vector is already owned by other,
498 * assign a new vector for the other and make the vector available
501 iosapic_reassign_vector (int vector
)
505 if (!list_empty(&iosapic_intr_info
[vector
].rtes
)) {
506 new_vector
= assign_irq_vector(AUTO_ASSIGN
);
508 panic("%s: out of interrupt vectors!\n", __FUNCTION__
);
509 printk(KERN_INFO
"Reassigning vector %d to %d\n", vector
, new_vector
);
510 memcpy(&iosapic_intr_info
[new_vector
], &iosapic_intr_info
[vector
],
511 sizeof(struct iosapic_intr_info
));
512 INIT_LIST_HEAD(&iosapic_intr_info
[new_vector
].rtes
);
513 list_move(iosapic_intr_info
[vector
].rtes
.next
, &iosapic_intr_info
[new_vector
].rtes
);
514 memset(&iosapic_intr_info
[vector
], 0, sizeof(struct iosapic_intr_info
));
515 iosapic_intr_info
[vector
].low32
= IOSAPIC_MASK
;
516 INIT_LIST_HEAD(&iosapic_intr_info
[vector
].rtes
);
520 static struct iosapic_rte_info
*iosapic_alloc_rte (void)
523 struct iosapic_rte_info
*rte
;
524 int preallocated
= 0;
526 if (!iosapic_kmalloc_ok
&& list_empty(&free_rte_list
)) {
527 rte
= alloc_bootmem(sizeof(struct iosapic_rte_info
) * NR_PREALLOCATE_RTE_ENTRIES
);
530 for (i
= 0; i
< NR_PREALLOCATE_RTE_ENTRIES
; i
++, rte
++)
531 list_add(&rte
->rte_list
, &free_rte_list
);
534 if (!list_empty(&free_rte_list
)) {
535 rte
= list_entry(free_rte_list
.next
, struct iosapic_rte_info
, rte_list
);
536 list_del(&rte
->rte_list
);
539 rte
= kmalloc(sizeof(struct iosapic_rte_info
), GFP_ATOMIC
);
544 memset(rte
, 0, sizeof(struct iosapic_rte_info
));
546 rte
->flags
|= RTE_PREALLOCATED
;
551 static void iosapic_free_rte (struct iosapic_rte_info
*rte
)
553 if (rte
->flags
& RTE_PREALLOCATED
)
554 list_add_tail(&rte
->rte_list
, &free_rte_list
);
559 static inline int vector_is_shared (int vector
)
561 return (iosapic_intr_info
[vector
].count
> 1);
565 register_intr (unsigned int gsi
, int vector
, unsigned char delivery
,
566 unsigned long polarity
, unsigned long trigger
)
569 struct hw_interrupt_type
*irq_type
;
572 unsigned long gsi_base
;
573 void __iomem
*iosapic_address
;
574 struct iosapic_rte_info
*rte
;
576 index
= find_iosapic(gsi
);
578 printk(KERN_WARNING
"%s: No IOSAPIC for GSI %u\n", __FUNCTION__
, gsi
);
582 iosapic_address
= iosapic_lists
[index
].addr
;
583 gsi_base
= iosapic_lists
[index
].gsi_base
;
585 rte
= gsi_vector_to_rte(gsi
, vector
);
587 rte
= iosapic_alloc_rte();
589 printk(KERN_WARNING
"%s: cannot allocate memory\n", __FUNCTION__
);
593 rte_index
= gsi
- gsi_base
;
594 rte
->rte_index
= rte_index
;
595 rte
->addr
= iosapic_address
;
596 rte
->gsi_base
= gsi_base
;
598 list_add_tail(&rte
->rte_list
, &iosapic_intr_info
[vector
].rtes
);
599 iosapic_intr_info
[vector
].count
++;
600 iosapic_lists
[index
].rtes_inuse
++;
602 else if (vector_is_shared(vector
)) {
603 struct iosapic_intr_info
*info
= &iosapic_intr_info
[vector
];
604 if (info
->trigger
!= trigger
|| info
->polarity
!= polarity
) {
605 printk (KERN_WARNING
"%s: cannot override the interrupt\n", __FUNCTION__
);
610 iosapic_intr_info
[vector
].polarity
= polarity
;
611 iosapic_intr_info
[vector
].dmode
= delivery
;
612 iosapic_intr_info
[vector
].trigger
= trigger
;
614 if (trigger
== IOSAPIC_EDGE
)
615 irq_type
= &irq_type_iosapic_edge
;
617 irq_type
= &irq_type_iosapic_level
;
619 idesc
= irq_descp(vector
);
620 if (idesc
->handler
!= irq_type
) {
621 if (idesc
->handler
!= &no_irq_type
)
622 printk(KERN_WARNING
"%s: changing vector %d from %s to %s\n",
623 __FUNCTION__
, vector
, idesc
->handler
->typename
, irq_type
->typename
);
624 idesc
->handler
= irq_type
;
629 get_target_cpu (unsigned int gsi
, int vector
)
635 * In case of vector shared by multiple RTEs, all RTEs that
636 * share the vector need to use the same destination CPU.
638 if (!list_empty(&iosapic_intr_info
[vector
].rtes
))
639 return iosapic_intr_info
[vector
].dest
;
642 * If the platform supports redirection via XTP, let it
643 * distribute interrupts.
645 if (smp_int_redirect
& SMP_IRQ_REDIRECTION
)
646 return cpu_physical_id(smp_processor_id());
649 * Some interrupts (ACPI SCI, for instance) are registered
650 * before the BSP is marked as online.
652 if (!cpu_online(smp_processor_id()))
653 return cpu_physical_id(smp_processor_id());
657 int num_cpus
, cpu_index
, iosapic_index
, numa_cpu
, i
= 0;
660 iosapic_index
= find_iosapic(gsi
);
661 if (iosapic_index
< 0 ||
662 iosapic_lists
[iosapic_index
].node
== MAX_NUMNODES
)
663 goto skip_numa_setup
;
665 cpu_mask
= node_to_cpumask(iosapic_lists
[iosapic_index
].node
);
667 for_each_cpu_mask(numa_cpu
, cpu_mask
) {
668 if (!cpu_online(numa_cpu
))
669 cpu_clear(numa_cpu
, cpu_mask
);
672 num_cpus
= cpus_weight(cpu_mask
);
675 goto skip_numa_setup
;
677 /* Use vector assigment to distribute across cpus in node */
678 cpu_index
= vector
% num_cpus
;
680 for (numa_cpu
= first_cpu(cpu_mask
) ; i
< cpu_index
; i
++)
681 numa_cpu
= next_cpu(numa_cpu
, cpu_mask
);
683 if (numa_cpu
!= NR_CPUS
)
684 return cpu_physical_id(numa_cpu
);
689 * Otherwise, round-robin interrupt vectors across all the
690 * processors. (It'd be nice if we could be smarter in the
694 if (++cpu
>= NR_CPUS
)
696 } while (!cpu_online(cpu
));
698 return cpu_physical_id(cpu
);
700 return cpu_physical_id(smp_processor_id());
705 * ACPI can describe IOSAPIC interrupts via static tables and namespace
706 * methods. This provides an interface to register those interrupts and
707 * program the IOSAPIC RTE.
710 iosapic_register_intr (unsigned int gsi
,
711 unsigned long polarity
, unsigned long trigger
)
713 int vector
, mask
= 1;
716 struct iosapic_rte_info
*rte
;
720 * If this GSI has already been registered (i.e., it's a
721 * shared interrupt, or we lost a race to register it),
722 * don't touch the RTE.
724 spin_lock_irqsave(&iosapic_lock
, flags
);
726 vector
= gsi_to_vector(gsi
);
728 rte
= gsi_vector_to_rte(gsi
, vector
);
730 spin_unlock_irqrestore(&iosapic_lock
, flags
);
734 spin_unlock_irqrestore(&iosapic_lock
, flags
);
736 /* If vector is running out, we try to find a sharable vector */
737 vector
= assign_irq_vector(AUTO_ASSIGN
);
739 vector
= iosapic_find_sharable_vector(trigger
, polarity
);
741 panic("%s: out of interrupt vectors!\n", __FUNCTION__
);
744 spin_lock_irqsave(&irq_descp(vector
)->lock
, flags
);
745 spin_lock(&iosapic_lock
);
747 if (gsi_to_vector(gsi
) > 0) {
748 if (list_empty(&iosapic_intr_info
[vector
].rtes
))
749 free_irq_vector(vector
);
750 spin_unlock(&iosapic_lock
);
751 spin_unlock_irqrestore(&irq_descp(vector
)->lock
, flags
);
755 dest
= get_target_cpu(gsi
, vector
);
756 register_intr(gsi
, vector
, IOSAPIC_LOWEST_PRIORITY
,
760 * If the vector is shared and already unmasked for
761 * other interrupt sources, don't mask it.
763 low32
= iosapic_intr_info
[vector
].low32
;
764 if (vector_is_shared(vector
) && !(low32
& IOSAPIC_MASK
))
766 set_rte(gsi
, vector
, dest
, mask
);
768 spin_unlock(&iosapic_lock
);
769 spin_unlock_irqrestore(&irq_descp(vector
)->lock
, flags
);
771 printk(KERN_INFO
"GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
772 gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
773 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
774 cpu_logical_id(dest
), dest
, vector
);
779 #ifdef CONFIG_ACPI_DEALLOCATE_IRQ
781 iosapic_unregister_intr (unsigned int gsi
)
784 int irq
, vector
, index
;
787 unsigned long trigger
, polarity
;
789 struct iosapic_rte_info
*rte
;
792 * If the irq associated with the gsi is not found,
793 * iosapic_unregister_intr() is unbalanced. We need to check
794 * this again after getting locks.
796 irq
= gsi_to_irq(gsi
);
798 printk(KERN_ERR
"iosapic_unregister_intr(%u) unbalanced\n", gsi
);
802 vector
= irq_to_vector(irq
);
804 idesc
= irq_descp(irq
);
805 spin_lock_irqsave(&idesc
->lock
, flags
);
806 spin_lock(&iosapic_lock
);
808 if ((rte
= gsi_vector_to_rte(gsi
, vector
)) == NULL
) {
809 printk(KERN_ERR
"iosapic_unregister_intr(%u) unbalanced\n", gsi
);
814 if (--rte
->refcnt
> 0)
817 /* Mask the interrupt */
818 low32
= iosapic_intr_info
[vector
].low32
| IOSAPIC_MASK
;
819 iosapic_write(rte
->addr
, IOSAPIC_RTE_LOW(rte
->rte_index
), low32
);
821 /* Remove the rte entry from the list */
822 list_del(&rte
->rte_list
);
823 iosapic_intr_info
[vector
].count
--;
824 iosapic_free_rte(rte
);
825 index
= find_iosapic(gsi
);
826 iosapic_lists
[index
].rtes_inuse
--;
827 WARN_ON(iosapic_lists
[index
].rtes_inuse
< 0);
829 trigger
= iosapic_intr_info
[vector
].trigger
;
830 polarity
= iosapic_intr_info
[vector
].polarity
;
831 dest
= iosapic_intr_info
[vector
].dest
;
832 printk(KERN_INFO
"GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
833 gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
834 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
835 cpu_logical_id(dest
), dest
, vector
);
837 if (list_empty(&iosapic_intr_info
[vector
].rtes
)) {
839 BUG_ON(iosapic_intr_info
[vector
].count
);
841 /* Clear the interrupt controller descriptor */
842 idesc
->handler
= &no_irq_type
;
844 /* Clear the interrupt information */
845 memset(&iosapic_intr_info
[vector
], 0, sizeof(struct iosapic_intr_info
));
846 iosapic_intr_info
[vector
].low32
|= IOSAPIC_MASK
;
847 INIT_LIST_HEAD(&iosapic_intr_info
[vector
].rtes
);
850 printk(KERN_ERR
"interrupt handlers still exist on IRQ %u\n", irq
);
854 /* Free the interrupt vector */
855 free_irq_vector(vector
);
859 spin_unlock(&iosapic_lock
);
860 spin_unlock_irqrestore(&idesc
->lock
, flags
);
862 #endif /* CONFIG_ACPI_DEALLOCATE_IRQ */
865 * ACPI calls this when it finds an entry for a platform interrupt.
866 * Note that the irq_base and IOSAPIC address must be set in iosapic_init().
869 iosapic_register_platform_intr (u32 int_type
, unsigned int gsi
,
870 int iosapic_vector
, u16 eid
, u16 id
,
871 unsigned long polarity
, unsigned long trigger
)
873 static const char * const name
[] = {"unknown", "PMI", "INIT", "CPEI"};
874 unsigned char delivery
;
875 int vector
, mask
= 0;
876 unsigned int dest
= ((id
<< 8) | eid
) & 0xffff;
879 case ACPI_INTERRUPT_PMI
:
880 vector
= iosapic_vector
;
882 * since PMI vector is alloc'd by FW(ACPI) not by kernel,
883 * we need to make sure the vector is available
885 iosapic_reassign_vector(vector
);
886 delivery
= IOSAPIC_PMI
;
888 case ACPI_INTERRUPT_INIT
:
889 vector
= assign_irq_vector(AUTO_ASSIGN
);
891 panic("%s: out of interrupt vectors!\n", __FUNCTION__
);
892 delivery
= IOSAPIC_INIT
;
894 case ACPI_INTERRUPT_CPEI
:
895 vector
= IA64_CPE_VECTOR
;
896 delivery
= IOSAPIC_LOWEST_PRIORITY
;
900 printk(KERN_ERR
"iosapic_register_platform_irq(): invalid int type 0x%x\n", int_type
);
904 register_intr(gsi
, vector
, delivery
, polarity
, trigger
);
906 printk(KERN_INFO
"PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
907 int_type
< ARRAY_SIZE(name
) ? name
[int_type
] : "unknown",
908 int_type
, gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
909 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
910 cpu_logical_id(dest
), dest
, vector
);
912 set_rte(gsi
, vector
, dest
, mask
);
918 * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
919 * Note that the gsi_base and IOSAPIC address must be set in iosapic_init().
922 iosapic_override_isa_irq (unsigned int isa_irq
, unsigned int gsi
,
923 unsigned long polarity
,
924 unsigned long trigger
)
927 unsigned int dest
= cpu_physical_id(smp_processor_id());
929 vector
= isa_irq_to_vector(isa_irq
);
931 register_intr(gsi
, vector
, IOSAPIC_LOWEST_PRIORITY
, polarity
, trigger
);
933 DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
934 isa_irq
, gsi
, trigger
== IOSAPIC_EDGE
? "edge" : "level",
935 polarity
== IOSAPIC_POL_HIGH
? "high" : "low",
936 cpu_logical_id(dest
), dest
, vector
);
938 set_rte(gsi
, vector
, dest
, 1);
942 iosapic_system_init (int system_pcat_compat
)
946 for (vector
= 0; vector
< IA64_NUM_VECTORS
; ++vector
) {
947 iosapic_intr_info
[vector
].low32
= IOSAPIC_MASK
;
948 INIT_LIST_HEAD(&iosapic_intr_info
[vector
].rtes
); /* mark as unused */
951 pcat_compat
= system_pcat_compat
;
954 * Disable the compatibility mode interrupts (8259 style), needs IN/OUT support
957 printk(KERN_INFO
"%s: Disabling PC-AT compatible 8259 interrupts\n", __FUNCTION__
);
968 for (index
= 0; index
< NR_IOSAPICS
; index
++)
969 if (!iosapic_lists
[index
].addr
)
972 printk(KERN_WARNING
"%s: failed to allocate iosapic\n", __FUNCTION__
);
977 iosapic_free (int index
)
979 memset(&iosapic_lists
[index
], 0, sizeof(iosapic_lists
[0]));
983 iosapic_check_gsi_range (unsigned int gsi_base
, unsigned int ver
)
986 unsigned int gsi_end
, base
, end
;
988 /* check gsi range */
989 gsi_end
= gsi_base
+ ((ver
>> 16) & 0xff);
990 for (index
= 0; index
< NR_IOSAPICS
; index
++) {
991 if (!iosapic_lists
[index
].addr
)
994 base
= iosapic_lists
[index
].gsi_base
;
995 end
= base
+ iosapic_lists
[index
].num_rte
- 1;
997 if (gsi_base
< base
&& gsi_end
< base
)
1000 if (gsi_base
> end
&& gsi_end
> end
)
1009 iosapic_init (unsigned long phys_addr
, unsigned int gsi_base
)
1011 int num_rte
, err
, index
;
1012 unsigned int isa_irq
, ver
;
1014 unsigned long flags
;
1016 spin_lock_irqsave(&iosapic_lock
, flags
);
1018 addr
= ioremap(phys_addr
, 0);
1019 ver
= iosapic_version(addr
);
1021 if ((err
= iosapic_check_gsi_range(gsi_base
, ver
))) {
1023 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1028 * The MAX_REDIR register holds the highest input pin
1029 * number (starting from 0).
1030 * We add 1 so that we can use it for number of pins (= RTEs)
1032 num_rte
= ((ver
>> 16) & 0xff) + 1;
1034 index
= iosapic_alloc();
1035 iosapic_lists
[index
].addr
= addr
;
1036 iosapic_lists
[index
].gsi_base
= gsi_base
;
1037 iosapic_lists
[index
].num_rte
= num_rte
;
1039 iosapic_lists
[index
].node
= MAX_NUMNODES
;
1042 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1044 if ((gsi_base
== 0) && pcat_compat
) {
1046 * Map the legacy ISA devices into the IOSAPIC data. Some of these may
1047 * get reprogrammed later on with data from the ACPI Interrupt Source
1050 for (isa_irq
= 0; isa_irq
< 16; ++isa_irq
)
1051 iosapic_override_isa_irq(isa_irq
, isa_irq
, IOSAPIC_POL_HIGH
, IOSAPIC_EDGE
);
1056 #ifdef CONFIG_HOTPLUG
1058 iosapic_remove (unsigned int gsi_base
)
1061 unsigned long flags
;
1063 spin_lock_irqsave(&iosapic_lock
, flags
);
1065 index
= find_iosapic(gsi_base
);
1067 printk(KERN_WARNING
"%s: No IOSAPIC for GSI base %u\n",
1068 __FUNCTION__
, gsi_base
);
1072 if (iosapic_lists
[index
].rtes_inuse
) {
1074 printk(KERN_WARNING
"%s: IOSAPIC for GSI base %u is busy\n",
1075 __FUNCTION__
, gsi_base
);
1079 iounmap(iosapic_lists
[index
].addr
);
1080 iosapic_free(index
);
1083 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1086 #endif /* CONFIG_HOTPLUG */
1090 map_iosapic_to_node(unsigned int gsi_base
, int node
)
1094 index
= find_iosapic(gsi_base
);
1096 printk(KERN_WARNING
"%s: No IOSAPIC for GSI %u\n",
1097 __FUNCTION__
, gsi_base
);
1100 iosapic_lists
[index
].node
= node
;
1105 static int __init
iosapic_enable_kmalloc (void)
1107 iosapic_kmalloc_ok
= 1;
1110 core_initcall (iosapic_enable_kmalloc
);