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[IA64] Support irq migration across domain
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1 /*
2 * linux/arch/ia64/kernel/irq_ia64.c
3 *
4 * Copyright (C) 1998-2001 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 *
8 * 6/10/99: Updated to bring in sync with x86 version to facilitate
9 * support for SMP and different interrupt controllers.
10 *
11 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
12 * PCI to vector allocation routine.
13 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
14 * Added CPU Hotplug handling for IPF.
15 */
16
17 #include <linux/module.h>
18
19 #include <linux/jiffies.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/ioport.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/slab.h>
26 #include <linux/ptrace.h>
27 #include <linux/random.h> /* for rand_initialize_irq() */
28 #include <linux/signal.h>
29 #include <linux/smp.h>
30 #include <linux/threads.h>
31 #include <linux/bitops.h>
32 #include <linux/irq.h>
33
34 #include <asm/delay.h>
35 #include <asm/intrinsics.h>
36 #include <asm/io.h>
37 #include <asm/hw_irq.h>
38 #include <asm/machvec.h>
39 #include <asm/pgtable.h>
40 #include <asm/system.h>
41 #include <asm/tlbflush.h>
42
43 #ifdef CONFIG_PERFMON
44 # include <asm/perfmon.h>
45 #endif
46
47 #define IRQ_DEBUG 0
48
49 #define IRQ_VECTOR_UNASSIGNED (0)
50
51 #define IRQ_UNUSED (0)
52 #define IRQ_USED (1)
53 #define IRQ_RSVD (2)
54
55 /* These can be overridden in platform_irq_init */
56 int ia64_first_device_vector = IA64_DEF_FIRST_DEVICE_VECTOR;
57 int ia64_last_device_vector = IA64_DEF_LAST_DEVICE_VECTOR;
58
59 /* default base addr of IPI table */
60 void __iomem *ipi_base_addr = ((void __iomem *)
61 (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));
62
63 static cpumask_t vector_allocation_domain(int cpu);
64
65 /*
66 * Legacy IRQ to IA-64 vector translation table.
67 */
68 __u8 isa_irq_to_vector_map[16] = {
69 /* 8259 IRQ translation, first 16 entries */
70 0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
71 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
72 };
73 EXPORT_SYMBOL(isa_irq_to_vector_map);
74
75 DEFINE_SPINLOCK(vector_lock);
76
77 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
78 [0 ... NR_IRQS - 1] = {
79 .vector = IRQ_VECTOR_UNASSIGNED,
80 .domain = CPU_MASK_NONE
81 }
82 };
83
84 DEFINE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq) = {
85 [0 ... IA64_NUM_VECTORS - 1] = IA64_SPURIOUS_INT_VECTOR
86 };
87
88 static cpumask_t vector_table[IA64_MAX_DEVICE_VECTORS] = {
89 [0 ... IA64_MAX_DEVICE_VECTORS - 1] = CPU_MASK_NONE
90 };
91
92 static int irq_status[NR_IRQS] = {
93 [0 ... NR_IRQS -1] = IRQ_UNUSED
94 };
95
96 int check_irq_used(int irq)
97 {
98 if (irq_status[irq] == IRQ_USED)
99 return 1;
100
101 return -1;
102 }
103
104 static void reserve_irq(unsigned int irq)
105 {
106 unsigned long flags;
107
108 spin_lock_irqsave(&vector_lock, flags);
109 irq_status[irq] = IRQ_RSVD;
110 spin_unlock_irqrestore(&vector_lock, flags);
111 }
112
113 static inline int find_unassigned_irq(void)
114 {
115 int irq;
116
117 for (irq = IA64_FIRST_DEVICE_VECTOR; irq < NR_IRQS; irq++)
118 if (irq_status[irq] == IRQ_UNUSED)
119 return irq;
120 return -ENOSPC;
121 }
122
123 static inline int find_unassigned_vector(cpumask_t domain)
124 {
125 cpumask_t mask;
126 int pos;
127
128 cpus_and(mask, domain, cpu_online_map);
129 if (cpus_empty(mask))
130 return -EINVAL;
131
132 for (pos = 0; pos < IA64_NUM_DEVICE_VECTORS; pos++) {
133 cpus_and(mask, domain, vector_table[pos]);
134 if (!cpus_empty(mask))
135 continue;
136 return IA64_FIRST_DEVICE_VECTOR + pos;
137 }
138 return -ENOSPC;
139 }
140
141 static int __bind_irq_vector(int irq, int vector, cpumask_t domain)
142 {
143 cpumask_t mask;
144 int cpu, pos;
145 struct irq_cfg *cfg = &irq_cfg[irq];
146
147 cpus_and(mask, domain, cpu_online_map);
148 if (cpus_empty(mask))
149 return -EINVAL;
150 if ((cfg->vector == vector) && cpus_equal(cfg->domain, domain))
151 return 0;
152 if (cfg->vector != IRQ_VECTOR_UNASSIGNED)
153 return -EBUSY;
154 for_each_cpu_mask(cpu, mask)
155 per_cpu(vector_irq, cpu)[vector] = irq;
156 cfg->vector = vector;
157 cfg->domain = domain;
158 irq_status[irq] = IRQ_USED;
159 pos = vector - IA64_FIRST_DEVICE_VECTOR;
160 cpus_or(vector_table[pos], vector_table[pos], domain);
161 return 0;
162 }
163
164 int bind_irq_vector(int irq, int vector, cpumask_t domain)
165 {
166 unsigned long flags;
167 int ret;
168
169 spin_lock_irqsave(&vector_lock, flags);
170 ret = __bind_irq_vector(irq, vector, domain);
171 spin_unlock_irqrestore(&vector_lock, flags);
172 return ret;
173 }
174
175 static void __clear_irq_vector(int irq)
176 {
177 int vector, cpu, pos;
178 cpumask_t mask;
179 cpumask_t domain;
180 struct irq_cfg *cfg = &irq_cfg[irq];
181
182 BUG_ON((unsigned)irq >= NR_IRQS);
183 BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED);
184 vector = cfg->vector;
185 domain = cfg->domain;
186 cpus_and(mask, cfg->domain, cpu_online_map);
187 for_each_cpu_mask(cpu, mask)
188 per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
189 cfg->vector = IRQ_VECTOR_UNASSIGNED;
190 cfg->domain = CPU_MASK_NONE;
191 irq_status[irq] = IRQ_UNUSED;
192 pos = vector - IA64_FIRST_DEVICE_VECTOR;
193 cpus_andnot(vector_table[pos], vector_table[pos], domain);
194 }
195
196 static void clear_irq_vector(int irq)
197 {
198 unsigned long flags;
199
200 spin_lock_irqsave(&vector_lock, flags);
201 __clear_irq_vector(irq);
202 spin_unlock_irqrestore(&vector_lock, flags);
203 }
204
205 int
206 assign_irq_vector (int irq)
207 {
208 unsigned long flags;
209 int vector, cpu;
210 cpumask_t domain;
211
212 vector = -ENOSPC;
213
214 spin_lock_irqsave(&vector_lock, flags);
215 if (irq < 0) {
216 goto out;
217 }
218 for_each_online_cpu(cpu) {
219 domain = vector_allocation_domain(cpu);
220 vector = find_unassigned_vector(domain);
221 if (vector >= 0)
222 break;
223 }
224 if (vector < 0)
225 goto out;
226 BUG_ON(__bind_irq_vector(irq, vector, domain));
227 out:
228 spin_unlock_irqrestore(&vector_lock, flags);
229 return vector;
230 }
231
232 void
233 free_irq_vector (int vector)
234 {
235 if (vector < IA64_FIRST_DEVICE_VECTOR ||
236 vector > IA64_LAST_DEVICE_VECTOR)
237 return;
238 clear_irq_vector(vector);
239 }
240
241 int
242 reserve_irq_vector (int vector)
243 {
244 if (vector < IA64_FIRST_DEVICE_VECTOR ||
245 vector > IA64_LAST_DEVICE_VECTOR)
246 return -EINVAL;
247 return !!bind_irq_vector(vector, vector, CPU_MASK_ALL);
248 }
249
250 /*
251 * Initialize vector_irq on a new cpu. This function must be called
252 * with vector_lock held.
253 */
254 void __setup_vector_irq(int cpu)
255 {
256 int irq, vector;
257
258 /* Clear vector_irq */
259 for (vector = 0; vector < IA64_NUM_VECTORS; ++vector)
260 per_cpu(vector_irq, cpu)[vector] = IA64_SPURIOUS_INT_VECTOR;
261 /* Mark the inuse vectors */
262 for (irq = 0; irq < NR_IRQS; ++irq) {
263 if (!cpu_isset(cpu, irq_cfg[irq].domain))
264 continue;
265 vector = irq_to_vector(irq);
266 per_cpu(vector_irq, cpu)[vector] = irq;
267 }
268 }
269
270 static cpumask_t vector_allocation_domain(int cpu)
271 {
272 return CPU_MASK_ALL;
273 }
274
275
276 void destroy_and_reserve_irq(unsigned int irq)
277 {
278 dynamic_irq_cleanup(irq);
279
280 clear_irq_vector(irq);
281 reserve_irq(irq);
282 }
283
284 static int __reassign_irq_vector(int irq, int cpu)
285 {
286 struct irq_cfg *cfg = &irq_cfg[irq];
287 int vector;
288 cpumask_t domain;
289
290 if (cfg->vector == IRQ_VECTOR_UNASSIGNED || !cpu_online(cpu))
291 return -EINVAL;
292 if (cpu_isset(cpu, cfg->domain))
293 return 0;
294 domain = vector_allocation_domain(cpu);
295 vector = find_unassigned_vector(domain);
296 if (vector < 0)
297 return -ENOSPC;
298 __clear_irq_vector(irq);
299 BUG_ON(__bind_irq_vector(irq, vector, domain));
300 return 0;
301 }
302
303 int reassign_irq_vector(int irq, int cpu)
304 {
305 unsigned long flags;
306 int ret;
307
308 spin_lock_irqsave(&vector_lock, flags);
309 ret = __reassign_irq_vector(irq, cpu);
310 spin_unlock_irqrestore(&vector_lock, flags);
311 return ret;
312 }
313
314 /*
315 * Dynamic irq allocate and deallocation for MSI
316 */
317 int create_irq(void)
318 {
319 unsigned long flags;
320 int irq, vector, cpu;
321 cpumask_t domain;
322
323 irq = vector = -ENOSPC;
324 spin_lock_irqsave(&vector_lock, flags);
325 for_each_online_cpu(cpu) {
326 domain = vector_allocation_domain(cpu);
327 vector = find_unassigned_vector(domain);
328 if (vector >= 0)
329 break;
330 }
331 if (vector < 0)
332 goto out;
333 irq = find_unassigned_irq();
334 if (irq < 0)
335 goto out;
336 BUG_ON(__bind_irq_vector(irq, vector, domain));
337 out:
338 spin_unlock_irqrestore(&vector_lock, flags);
339 if (irq >= 0)
340 dynamic_irq_init(irq);
341 return irq;
342 }
343
344 void destroy_irq(unsigned int irq)
345 {
346 dynamic_irq_cleanup(irq);
347 clear_irq_vector(irq);
348 }
349
350 #ifdef CONFIG_SMP
351 # define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
352 # define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
353 #else
354 # define IS_RESCHEDULE(vec) (0)
355 # define IS_LOCAL_TLB_FLUSH(vec) (0)
356 #endif
357 /*
358 * That's where the IVT branches when we get an external
359 * interrupt. This branches to the correct hardware IRQ handler via
360 * function ptr.
361 */
362 void
363 ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
364 {
365 struct pt_regs *old_regs = set_irq_regs(regs);
366 unsigned long saved_tpr;
367
368 #if IRQ_DEBUG
369 {
370 unsigned long bsp, sp;
371
372 /*
373 * Note: if the interrupt happened while executing in
374 * the context switch routine (ia64_switch_to), we may
375 * get a spurious stack overflow here. This is
376 * because the register and the memory stack are not
377 * switched atomically.
378 */
379 bsp = ia64_getreg(_IA64_REG_AR_BSP);
380 sp = ia64_getreg(_IA64_REG_SP);
381
382 if ((sp - bsp) < 1024) {
383 static unsigned char count;
384 static long last_time;
385
386 if (jiffies - last_time > 5*HZ)
387 count = 0;
388 if (++count < 5) {
389 last_time = jiffies;
390 printk("ia64_handle_irq: DANGER: less than "
391 "1KB of free stack space!!\n"
392 "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
393 }
394 }
395 }
396 #endif /* IRQ_DEBUG */
397
398 /*
399 * Always set TPR to limit maximum interrupt nesting depth to
400 * 16 (without this, it would be ~240, which could easily lead
401 * to kernel stack overflows).
402 */
403 irq_enter();
404 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
405 ia64_srlz_d();
406 while (vector != IA64_SPURIOUS_INT_VECTOR) {
407 if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
408 smp_local_flush_tlb();
409 kstat_this_cpu.irqs[vector]++;
410 } else if (unlikely(IS_RESCHEDULE(vector)))
411 kstat_this_cpu.irqs[vector]++;
412 else {
413 ia64_setreg(_IA64_REG_CR_TPR, vector);
414 ia64_srlz_d();
415
416 generic_handle_irq(local_vector_to_irq(vector));
417
418 /*
419 * Disable interrupts and send EOI:
420 */
421 local_irq_disable();
422 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
423 }
424 ia64_eoi();
425 vector = ia64_get_ivr();
426 }
427 /*
428 * This must be done *after* the ia64_eoi(). For example, the keyboard softirq
429 * handler needs to be able to wait for further keyboard interrupts, which can't
430 * come through until ia64_eoi() has been done.
431 */
432 irq_exit();
433 set_irq_regs(old_regs);
434 }
435
436 #ifdef CONFIG_HOTPLUG_CPU
437 /*
438 * This function emulates a interrupt processing when a cpu is about to be
439 * brought down.
440 */
441 void ia64_process_pending_intr(void)
442 {
443 ia64_vector vector;
444 unsigned long saved_tpr;
445 extern unsigned int vectors_in_migration[NR_IRQS];
446
447 vector = ia64_get_ivr();
448
449 irq_enter();
450 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
451 ia64_srlz_d();
452
453 /*
454 * Perform normal interrupt style processing
455 */
456 while (vector != IA64_SPURIOUS_INT_VECTOR) {
457 if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) {
458 smp_local_flush_tlb();
459 kstat_this_cpu.irqs[vector]++;
460 } else if (unlikely(IS_RESCHEDULE(vector)))
461 kstat_this_cpu.irqs[vector]++;
462 else {
463 struct pt_regs *old_regs = set_irq_regs(NULL);
464
465 ia64_setreg(_IA64_REG_CR_TPR, vector);
466 ia64_srlz_d();
467
468 /*
469 * Now try calling normal ia64_handle_irq as it would have got called
470 * from a real intr handler. Try passing null for pt_regs, hopefully
471 * it will work. I hope it works!.
472 * Probably could shared code.
473 */
474 vectors_in_migration[local_vector_to_irq(vector)]=0;
475 generic_handle_irq(local_vector_to_irq(vector));
476 set_irq_regs(old_regs);
477
478 /*
479 * Disable interrupts and send EOI
480 */
481 local_irq_disable();
482 ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
483 }
484 ia64_eoi();
485 vector = ia64_get_ivr();
486 }
487 irq_exit();
488 }
489 #endif
490
491
492 #ifdef CONFIG_SMP
493
494 static irqreturn_t dummy_handler (int irq, void *dev_id)
495 {
496 BUG();
497 }
498 extern irqreturn_t handle_IPI (int irq, void *dev_id);
499
500 static struct irqaction ipi_irqaction = {
501 .handler = handle_IPI,
502 .flags = IRQF_DISABLED,
503 .name = "IPI"
504 };
505
506 static struct irqaction resched_irqaction = {
507 .handler = dummy_handler,
508 .flags = IRQF_DISABLED,
509 .name = "resched"
510 };
511
512 static struct irqaction tlb_irqaction = {
513 .handler = dummy_handler,
514 .flags = IRQF_DISABLED,
515 .name = "tlb_flush"
516 };
517
518 #endif
519
520 void
521 register_percpu_irq (ia64_vector vec, struct irqaction *action)
522 {
523 irq_desc_t *desc;
524 unsigned int irq;
525
526 irq = vec;
527 BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
528 desc = irq_desc + irq;
529 desc->status |= IRQ_PER_CPU;
530 desc->chip = &irq_type_ia64_lsapic;
531 if (action)
532 setup_irq(irq, action);
533 }
534
535 void __init
536 init_IRQ (void)
537 {
538 register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
539 #ifdef CONFIG_SMP
540 register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
541 register_percpu_irq(IA64_IPI_RESCHEDULE, &resched_irqaction);
542 register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &tlb_irqaction);
543 #endif
544 #ifdef CONFIG_PERFMON
545 pfm_init_percpu();
546 #endif
547 platform_irq_init();
548 }
549
550 void
551 ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
552 {
553 void __iomem *ipi_addr;
554 unsigned long ipi_data;
555 unsigned long phys_cpu_id;
556
557 #ifdef CONFIG_SMP
558 phys_cpu_id = cpu_physical_id(cpu);
559 #else
560 phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
561 #endif
562
563 /*
564 * cpu number is in 8bit ID and 8bit EID
565 */
566
567 ipi_data = (delivery_mode << 8) | (vector & 0xff);
568 ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));
569
570 writeq(ipi_data, ipi_addr);
571 }