2 * linux/arch/ia64/kernel/irq_ia64.c
4 * Copyright (C) 1998-2001 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * 6/10/99: Updated to bring in sync with x86 version to facilitate
9 * support for SMP and different interrupt controllers.
11 * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
12 * PCI to vector allocation routine.
13 * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
14 * Added CPU Hotplug handling for IPF.
17 #include <linux/module.h>
19 #include <linux/jiffies.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/ioport.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/slab.h>
26 #include <linux/ptrace.h>
27 #include <linux/random.h> /* for rand_initialize_irq() */
28 #include <linux/signal.h>
29 #include <linux/smp.h>
30 #include <linux/threads.h>
31 #include <linux/bitops.h>
32 #include <linux/irq.h>
34 #include <asm/delay.h>
35 #include <asm/intrinsics.h>
37 #include <asm/hw_irq.h>
38 #include <asm/machvec.h>
39 #include <asm/pgtable.h>
40 #include <asm/system.h>
41 #include <asm/tlbflush.h>
44 # include <asm/perfmon.h>
49 #define IRQ_VECTOR_UNASSIGNED (0)
51 #define IRQ_UNUSED (0)
55 /* These can be overridden in platform_irq_init */
56 int ia64_first_device_vector
= IA64_DEF_FIRST_DEVICE_VECTOR
;
57 int ia64_last_device_vector
= IA64_DEF_LAST_DEVICE_VECTOR
;
59 /* default base addr of IPI table */
60 void __iomem
*ipi_base_addr
= ((void __iomem
*)
61 (__IA64_UNCACHED_OFFSET
| IA64_IPI_DEFAULT_BASE_ADDR
));
63 static cpumask_t
vector_allocation_domain(int cpu
);
66 * Legacy IRQ to IA-64 vector translation table.
68 __u8 isa_irq_to_vector_map
[16] = {
69 /* 8259 IRQ translation, first 16 entries */
70 0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
71 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
73 EXPORT_SYMBOL(isa_irq_to_vector_map
);
75 DEFINE_SPINLOCK(vector_lock
);
77 struct irq_cfg irq_cfg
[NR_IRQS
] __read_mostly
= {
78 [0 ... NR_IRQS
- 1] = {
79 .vector
= IRQ_VECTOR_UNASSIGNED
,
80 .domain
= CPU_MASK_NONE
84 DEFINE_PER_CPU(int[IA64_NUM_VECTORS
], vector_irq
) = {
85 [0 ... IA64_NUM_VECTORS
- 1] = IA64_SPURIOUS_INT_VECTOR
88 static cpumask_t vector_table
[IA64_MAX_DEVICE_VECTORS
] = {
89 [0 ... IA64_MAX_DEVICE_VECTORS
- 1] = CPU_MASK_NONE
92 static int irq_status
[NR_IRQS
] = {
93 [0 ... NR_IRQS
-1] = IRQ_UNUSED
96 int check_irq_used(int irq
)
98 if (irq_status
[irq
] == IRQ_USED
)
104 static void reserve_irq(unsigned int irq
)
108 spin_lock_irqsave(&vector_lock
, flags
);
109 irq_status
[irq
] = IRQ_RSVD
;
110 spin_unlock_irqrestore(&vector_lock
, flags
);
113 static inline int find_unassigned_irq(void)
117 for (irq
= IA64_FIRST_DEVICE_VECTOR
; irq
< NR_IRQS
; irq
++)
118 if (irq_status
[irq
] == IRQ_UNUSED
)
123 static inline int find_unassigned_vector(cpumask_t domain
)
128 cpus_and(mask
, domain
, cpu_online_map
);
129 if (cpus_empty(mask
))
132 for (pos
= 0; pos
< IA64_NUM_DEVICE_VECTORS
; pos
++) {
133 cpus_and(mask
, domain
, vector_table
[pos
]);
134 if (!cpus_empty(mask
))
136 return IA64_FIRST_DEVICE_VECTOR
+ pos
;
141 static int __bind_irq_vector(int irq
, int vector
, cpumask_t domain
)
145 struct irq_cfg
*cfg
= &irq_cfg
[irq
];
147 cpus_and(mask
, domain
, cpu_online_map
);
148 if (cpus_empty(mask
))
150 if ((cfg
->vector
== vector
) && cpus_equal(cfg
->domain
, domain
))
152 if (cfg
->vector
!= IRQ_VECTOR_UNASSIGNED
)
154 for_each_cpu_mask(cpu
, mask
)
155 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
156 cfg
->vector
= vector
;
157 cfg
->domain
= domain
;
158 irq_status
[irq
] = IRQ_USED
;
159 pos
= vector
- IA64_FIRST_DEVICE_VECTOR
;
160 cpus_or(vector_table
[pos
], vector_table
[pos
], domain
);
164 int bind_irq_vector(int irq
, int vector
, cpumask_t domain
)
169 spin_lock_irqsave(&vector_lock
, flags
);
170 ret
= __bind_irq_vector(irq
, vector
, domain
);
171 spin_unlock_irqrestore(&vector_lock
, flags
);
175 static void __clear_irq_vector(int irq
)
177 int vector
, cpu
, pos
;
180 struct irq_cfg
*cfg
= &irq_cfg
[irq
];
182 BUG_ON((unsigned)irq
>= NR_IRQS
);
183 BUG_ON(cfg
->vector
== IRQ_VECTOR_UNASSIGNED
);
184 vector
= cfg
->vector
;
185 domain
= cfg
->domain
;
186 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
187 for_each_cpu_mask(cpu
, mask
)
188 per_cpu(vector_irq
, cpu
)[vector
] = IA64_SPURIOUS_INT_VECTOR
;
189 cfg
->vector
= IRQ_VECTOR_UNASSIGNED
;
190 cfg
->domain
= CPU_MASK_NONE
;
191 irq_status
[irq
] = IRQ_UNUSED
;
192 pos
= vector
- IA64_FIRST_DEVICE_VECTOR
;
193 cpus_andnot(vector_table
[pos
], vector_table
[pos
], domain
);
196 static void clear_irq_vector(int irq
)
200 spin_lock_irqsave(&vector_lock
, flags
);
201 __clear_irq_vector(irq
);
202 spin_unlock_irqrestore(&vector_lock
, flags
);
206 assign_irq_vector (int irq
)
214 spin_lock_irqsave(&vector_lock
, flags
);
218 for_each_online_cpu(cpu
) {
219 domain
= vector_allocation_domain(cpu
);
220 vector
= find_unassigned_vector(domain
);
226 BUG_ON(__bind_irq_vector(irq
, vector
, domain
));
228 spin_unlock_irqrestore(&vector_lock
, flags
);
233 free_irq_vector (int vector
)
235 if (vector
< IA64_FIRST_DEVICE_VECTOR
||
236 vector
> IA64_LAST_DEVICE_VECTOR
)
238 clear_irq_vector(vector
);
242 reserve_irq_vector (int vector
)
244 if (vector
< IA64_FIRST_DEVICE_VECTOR
||
245 vector
> IA64_LAST_DEVICE_VECTOR
)
247 return !!bind_irq_vector(vector
, vector
, CPU_MASK_ALL
);
251 * Initialize vector_irq on a new cpu. This function must be called
252 * with vector_lock held.
254 void __setup_vector_irq(int cpu
)
258 /* Clear vector_irq */
259 for (vector
= 0; vector
< IA64_NUM_VECTORS
; ++vector
)
260 per_cpu(vector_irq
, cpu
)[vector
] = IA64_SPURIOUS_INT_VECTOR
;
261 /* Mark the inuse vectors */
262 for (irq
= 0; irq
< NR_IRQS
; ++irq
) {
263 if (!cpu_isset(cpu
, irq_cfg
[irq
].domain
))
265 vector
= irq_to_vector(irq
);
266 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
270 static cpumask_t
vector_allocation_domain(int cpu
)
276 void destroy_and_reserve_irq(unsigned int irq
)
278 dynamic_irq_cleanup(irq
);
280 clear_irq_vector(irq
);
284 static int __reassign_irq_vector(int irq
, int cpu
)
286 struct irq_cfg
*cfg
= &irq_cfg
[irq
];
290 if (cfg
->vector
== IRQ_VECTOR_UNASSIGNED
|| !cpu_online(cpu
))
292 if (cpu_isset(cpu
, cfg
->domain
))
294 domain
= vector_allocation_domain(cpu
);
295 vector
= find_unassigned_vector(domain
);
298 __clear_irq_vector(irq
);
299 BUG_ON(__bind_irq_vector(irq
, vector
, domain
));
303 int reassign_irq_vector(int irq
, int cpu
)
308 spin_lock_irqsave(&vector_lock
, flags
);
309 ret
= __reassign_irq_vector(irq
, cpu
);
310 spin_unlock_irqrestore(&vector_lock
, flags
);
315 * Dynamic irq allocate and deallocation for MSI
320 int irq
, vector
, cpu
;
323 irq
= vector
= -ENOSPC
;
324 spin_lock_irqsave(&vector_lock
, flags
);
325 for_each_online_cpu(cpu
) {
326 domain
= vector_allocation_domain(cpu
);
327 vector
= find_unassigned_vector(domain
);
333 irq
= find_unassigned_irq();
336 BUG_ON(__bind_irq_vector(irq
, vector
, domain
));
338 spin_unlock_irqrestore(&vector_lock
, flags
);
340 dynamic_irq_init(irq
);
344 void destroy_irq(unsigned int irq
)
346 dynamic_irq_cleanup(irq
);
347 clear_irq_vector(irq
);
351 # define IS_RESCHEDULE(vec) (vec == IA64_IPI_RESCHEDULE)
352 # define IS_LOCAL_TLB_FLUSH(vec) (vec == IA64_IPI_LOCAL_TLB_FLUSH)
354 # define IS_RESCHEDULE(vec) (0)
355 # define IS_LOCAL_TLB_FLUSH(vec) (0)
358 * That's where the IVT branches when we get an external
359 * interrupt. This branches to the correct hardware IRQ handler via
363 ia64_handle_irq (ia64_vector vector
, struct pt_regs
*regs
)
365 struct pt_regs
*old_regs
= set_irq_regs(regs
);
366 unsigned long saved_tpr
;
370 unsigned long bsp
, sp
;
373 * Note: if the interrupt happened while executing in
374 * the context switch routine (ia64_switch_to), we may
375 * get a spurious stack overflow here. This is
376 * because the register and the memory stack are not
377 * switched atomically.
379 bsp
= ia64_getreg(_IA64_REG_AR_BSP
);
380 sp
= ia64_getreg(_IA64_REG_SP
);
382 if ((sp
- bsp
) < 1024) {
383 static unsigned char count
;
384 static long last_time
;
386 if (jiffies
- last_time
> 5*HZ
)
390 printk("ia64_handle_irq: DANGER: less than "
391 "1KB of free stack space!!\n"
392 "(bsp=0x%lx, sp=%lx)\n", bsp
, sp
);
396 #endif /* IRQ_DEBUG */
399 * Always set TPR to limit maximum interrupt nesting depth to
400 * 16 (without this, it would be ~240, which could easily lead
401 * to kernel stack overflows).
404 saved_tpr
= ia64_getreg(_IA64_REG_CR_TPR
);
406 while (vector
!= IA64_SPURIOUS_INT_VECTOR
) {
407 if (unlikely(IS_LOCAL_TLB_FLUSH(vector
))) {
408 smp_local_flush_tlb();
409 kstat_this_cpu
.irqs
[vector
]++;
410 } else if (unlikely(IS_RESCHEDULE(vector
)))
411 kstat_this_cpu
.irqs
[vector
]++;
413 ia64_setreg(_IA64_REG_CR_TPR
, vector
);
416 generic_handle_irq(local_vector_to_irq(vector
));
419 * Disable interrupts and send EOI:
422 ia64_setreg(_IA64_REG_CR_TPR
, saved_tpr
);
425 vector
= ia64_get_ivr();
428 * This must be done *after* the ia64_eoi(). For example, the keyboard softirq
429 * handler needs to be able to wait for further keyboard interrupts, which can't
430 * come through until ia64_eoi() has been done.
433 set_irq_regs(old_regs
);
436 #ifdef CONFIG_HOTPLUG_CPU
438 * This function emulates a interrupt processing when a cpu is about to be
441 void ia64_process_pending_intr(void)
444 unsigned long saved_tpr
;
445 extern unsigned int vectors_in_migration
[NR_IRQS
];
447 vector
= ia64_get_ivr();
450 saved_tpr
= ia64_getreg(_IA64_REG_CR_TPR
);
454 * Perform normal interrupt style processing
456 while (vector
!= IA64_SPURIOUS_INT_VECTOR
) {
457 if (unlikely(IS_LOCAL_TLB_FLUSH(vector
))) {
458 smp_local_flush_tlb();
459 kstat_this_cpu
.irqs
[vector
]++;
460 } else if (unlikely(IS_RESCHEDULE(vector
)))
461 kstat_this_cpu
.irqs
[vector
]++;
463 struct pt_regs
*old_regs
= set_irq_regs(NULL
);
465 ia64_setreg(_IA64_REG_CR_TPR
, vector
);
469 * Now try calling normal ia64_handle_irq as it would have got called
470 * from a real intr handler. Try passing null for pt_regs, hopefully
471 * it will work. I hope it works!.
472 * Probably could shared code.
474 vectors_in_migration
[local_vector_to_irq(vector
)]=0;
475 generic_handle_irq(local_vector_to_irq(vector
));
476 set_irq_regs(old_regs
);
479 * Disable interrupts and send EOI
482 ia64_setreg(_IA64_REG_CR_TPR
, saved_tpr
);
485 vector
= ia64_get_ivr();
494 static irqreturn_t
dummy_handler (int irq
, void *dev_id
)
498 extern irqreturn_t
handle_IPI (int irq
, void *dev_id
);
500 static struct irqaction ipi_irqaction
= {
501 .handler
= handle_IPI
,
502 .flags
= IRQF_DISABLED
,
506 static struct irqaction resched_irqaction
= {
507 .handler
= dummy_handler
,
508 .flags
= IRQF_DISABLED
,
512 static struct irqaction tlb_irqaction
= {
513 .handler
= dummy_handler
,
514 .flags
= IRQF_DISABLED
,
521 register_percpu_irq (ia64_vector vec
, struct irqaction
*action
)
527 BUG_ON(bind_irq_vector(irq
, vec
, CPU_MASK_ALL
));
528 desc
= irq_desc
+ irq
;
529 desc
->status
|= IRQ_PER_CPU
;
530 desc
->chip
= &irq_type_ia64_lsapic
;
532 setup_irq(irq
, action
);
538 register_percpu_irq(IA64_SPURIOUS_INT_VECTOR
, NULL
);
540 register_percpu_irq(IA64_IPI_VECTOR
, &ipi_irqaction
);
541 register_percpu_irq(IA64_IPI_RESCHEDULE
, &resched_irqaction
);
542 register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH
, &tlb_irqaction
);
544 #ifdef CONFIG_PERFMON
551 ia64_send_ipi (int cpu
, int vector
, int delivery_mode
, int redirect
)
553 void __iomem
*ipi_addr
;
554 unsigned long ipi_data
;
555 unsigned long phys_cpu_id
;
558 phys_cpu_id
= cpu_physical_id(cpu
);
560 phys_cpu_id
= (ia64_getreg(_IA64_REG_CR_LID
) >> 16) & 0xffff;
564 * cpu number is in 8bit ID and 8bit EID
567 ipi_data
= (delivery_mode
<< 8) | (vector
& 0xff);
568 ipi_addr
= ipi_base_addr
+ ((phys_cpu_id
<< 4) | ((redirect
& 1) << 3));
570 writeq(ipi_data
, ipi_addr
);