2 * pci.c - Low-Level PCI Access in IA-64
4 * Derived from bios32.c of i386 tree.
6 * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Bjorn Helgaas <bjorn.helgaas@hp.com>
9 * Copyright (C) 2004 Silicon Graphics, Inc.
11 * Note: Above list of copyright holders is incomplete...
14 #include <linux/acpi.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/bootmem.h>
23 #include <linux/export.h>
25 #include <asm/machvec.h>
31 #include <asm/hw_irq.h>
34 * Low-level SAL-based PCI configuration access functions. Note that SAL
35 * calls are already serialized (via sal_lock), so we don't need another
36 * synchronization mechanism here.
39 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
40 (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
42 /* SAL 3.2 adds support for extended config space. */
44 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
45 (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
47 int raw_pci_read(unsigned int seg
, unsigned int bus
, unsigned int devfn
,
48 int reg
, int len
, u32
*value
)
53 if (!value
|| (seg
> 65535) || (bus
> 255) || (devfn
> 255) || (reg
> 4095))
56 if ((seg
| reg
) <= 255) {
57 addr
= PCI_SAL_ADDRESS(seg
, bus
, devfn
, reg
);
59 } else if (sal_revision
>= SAL_VERSION_CODE(3,2)) {
60 addr
= PCI_SAL_EXT_ADDRESS(seg
, bus
, devfn
, reg
);
66 result
= ia64_sal_pci_config_read(addr
, mode
, len
, &data
);
74 int raw_pci_write(unsigned int seg
, unsigned int bus
, unsigned int devfn
,
75 int reg
, int len
, u32 value
)
80 if ((seg
> 65535) || (bus
> 255) || (devfn
> 255) || (reg
> 4095))
83 if ((seg
| reg
) <= 255) {
84 addr
= PCI_SAL_ADDRESS(seg
, bus
, devfn
, reg
);
86 } else if (sal_revision
>= SAL_VERSION_CODE(3,2)) {
87 addr
= PCI_SAL_EXT_ADDRESS(seg
, bus
, devfn
, reg
);
92 result
= ia64_sal_pci_config_write(addr
, mode
, len
, value
);
98 static int pci_read(struct pci_bus
*bus
, unsigned int devfn
, int where
,
101 return raw_pci_read(pci_domain_nr(bus
), bus
->number
,
102 devfn
, where
, size
, value
);
105 static int pci_write(struct pci_bus
*bus
, unsigned int devfn
, int where
,
108 return raw_pci_write(pci_domain_nr(bus
), bus
->number
,
109 devfn
, where
, size
, value
);
112 struct pci_ops pci_root_ops
= {
117 /* Called by ACPI when it finds a new root bus. */
119 static struct pci_controller
*alloc_pci_controller(int seg
)
121 struct pci_controller
*controller
;
123 controller
= kzalloc(sizeof(*controller
), GFP_KERNEL
);
127 controller
->segment
= seg
;
128 controller
->node
= -1;
132 struct pci_root_info
{
133 struct acpi_device
*bridge
;
134 struct pci_controller
*controller
;
135 struct list_head resources
;
140 new_space (u64 phys_base
, int sparse
)
146 return 0; /* legacy I/O port space */
148 mmio_base
= (u64
) ioremap(phys_base
, 0);
149 for (i
= 0; i
< num_io_spaces
; i
++)
150 if (io_space
[i
].mmio_base
== mmio_base
&&
151 io_space
[i
].sparse
== sparse
)
154 if (num_io_spaces
== MAX_IO_SPACES
) {
155 printk(KERN_ERR
"PCI: Too many IO port spaces "
156 "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES
);
161 io_space
[i
].mmio_base
= mmio_base
;
162 io_space
[i
].sparse
= sparse
;
167 static u64
add_io_space(struct pci_root_info
*info
,
168 struct acpi_resource_address64
*addr
)
170 struct resource
*resource
;
172 unsigned long base
, min
, max
, base_port
;
173 unsigned int sparse
= 0, space_nr
, len
;
175 resource
= kzalloc(sizeof(*resource
), GFP_KERNEL
);
177 printk(KERN_ERR
"PCI: No memory for %s I/O port space\n",
182 len
= strlen(info
->name
) + 32;
183 name
= kzalloc(len
, GFP_KERNEL
);
185 printk(KERN_ERR
"PCI: No memory for %s I/O port space name\n",
191 max
= min
+ addr
->address_length
- 1;
192 if (addr
->info
.io
.translation_type
== ACPI_SPARSE_TRANSLATION
)
195 space_nr
= new_space(addr
->translation_offset
, sparse
);
199 base
= __pa(io_space
[space_nr
].mmio_base
);
200 base_port
= IO_SPACE_BASE(space_nr
);
201 snprintf(name
, len
, "%s I/O Ports %08lx-%08lx", info
->name
,
202 base_port
+ min
, base_port
+ max
);
205 * The SDM guarantees the legacy 0-64K space is sparse, but if the
206 * mapping is done by the processor (not the bridge), ACPI may not
212 resource
->name
= name
;
213 resource
->flags
= IORESOURCE_MEM
;
214 resource
->start
= base
+ (sparse
? IO_SPACE_SPARSE_ENCODING(min
) : min
);
215 resource
->end
= base
+ (sparse
? IO_SPACE_SPARSE_ENCODING(max
) : max
);
216 insert_resource(&iomem_resource
, resource
);
228 static acpi_status
resource_to_window(struct acpi_resource
*resource
,
229 struct acpi_resource_address64
*addr
)
234 * We're only interested in _CRS descriptors that are
235 * - address space descriptors for memory or I/O space
237 * - producers, i.e., the address space is routed downstream,
238 * not consumed by the bridge itself
240 status
= acpi_resource_to_address64(resource
, addr
);
241 if (ACPI_SUCCESS(status
) &&
242 (addr
->resource_type
== ACPI_MEMORY_RANGE
||
243 addr
->resource_type
== ACPI_IO_RANGE
) &&
244 addr
->address_length
&&
245 addr
->producer_consumer
== ACPI_PRODUCER
)
251 static acpi_status
count_window(struct acpi_resource
*resource
, void *data
)
253 unsigned int *windows
= (unsigned int *) data
;
254 struct acpi_resource_address64 addr
;
257 status
= resource_to_window(resource
, &addr
);
258 if (ACPI_SUCCESS(status
))
264 static acpi_status
add_window(struct acpi_resource
*res
, void *data
)
266 struct pci_root_info
*info
= data
;
267 struct pci_window
*window
;
268 struct acpi_resource_address64 addr
;
270 unsigned long flags
, offset
= 0;
271 struct resource
*root
;
273 /* Return AE_OK for non-window resources to keep scanning for more */
274 status
= resource_to_window(res
, &addr
);
275 if (!ACPI_SUCCESS(status
))
278 if (addr
.resource_type
== ACPI_MEMORY_RANGE
) {
279 flags
= IORESOURCE_MEM
;
280 root
= &iomem_resource
;
281 offset
= addr
.translation_offset
;
282 } else if (addr
.resource_type
== ACPI_IO_RANGE
) {
283 flags
= IORESOURCE_IO
;
284 root
= &ioport_resource
;
285 offset
= add_io_space(info
, &addr
);
291 window
= &info
->controller
->window
[info
->controller
->windows
++];
292 window
->resource
.name
= info
->name
;
293 window
->resource
.flags
= flags
;
294 window
->resource
.start
= addr
.minimum
+ offset
;
295 window
->resource
.end
= window
->resource
.start
+ addr
.address_length
- 1;
296 window
->offset
= offset
;
298 if (insert_resource(root
, &window
->resource
)) {
299 dev_err(&info
->bridge
->dev
,
300 "can't allocate host bridge window %pR\n",
304 dev_info(&info
->bridge
->dev
, "host bridge window %pR "
305 "(PCI address [%#llx-%#llx])\n",
307 window
->resource
.start
- offset
,
308 window
->resource
.end
- offset
);
310 dev_info(&info
->bridge
->dev
,
311 "host bridge window %pR\n",
315 /* HP's firmware has a hack to work around a Windows bug.
316 * Ignore these tiny memory ranges */
317 if (!((window
->resource
.flags
& IORESOURCE_MEM
) &&
318 (window
->resource
.end
- window
->resource
.start
< 16)))
319 pci_add_resource_offset(&info
->resources
, &window
->resource
,
325 struct pci_bus
*pci_acpi_scan_root(struct acpi_pci_root
*root
)
327 struct acpi_device
*device
= root
->device
;
328 int domain
= root
->segment
;
329 int bus
= root
->secondary
.start
;
330 struct pci_controller
*controller
;
331 unsigned int windows
= 0;
332 struct pci_root_info info
;
333 struct pci_bus
*pbus
;
337 controller
= alloc_pci_controller(domain
);
341 controller
->acpi_handle
= device
->handle
;
343 pxm
= acpi_get_pxm(controller
->acpi_handle
);
346 controller
->node
= pxm_to_node(pxm
);
349 INIT_LIST_HEAD(&info
.resources
);
350 /* insert busn resource at first */
351 pci_add_resource(&info
.resources
, &root
->secondary
);
352 acpi_walk_resources(device
->handle
, METHOD_NAME__CRS
, count_window
,
356 kzalloc_node(sizeof(*controller
->window
) * windows
,
357 GFP_KERNEL
, controller
->node
);
358 if (!controller
->window
)
361 name
= kmalloc(16, GFP_KERNEL
);
365 sprintf(name
, "PCI Bus %04x:%02x", domain
, bus
);
366 info
.bridge
= device
;
367 info
.controller
= controller
;
369 acpi_walk_resources(device
->handle
, METHOD_NAME__CRS
,
373 * See arch/x86/pci/acpi.c.
374 * The desired pci bus might already be scanned in a quirk. We
375 * should handle the case here, but it appears that IA64 hasn't
376 * such quirk. So we just ignore the case now.
378 pbus
= pci_create_root_bus(NULL
, bus
, &pci_root_ops
, controller
,
381 pci_free_resource_list(&info
.resources
);
385 pci_scan_child_bus(pbus
);
389 kfree(controller
->window
);
396 int pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
)
398 struct pci_controller
*controller
= bridge
->bus
->sysdata
;
400 ACPI_HANDLE_SET(&bridge
->dev
, controller
->acpi_handle
);
404 static int is_valid_resource(struct pci_dev
*dev
, int idx
)
406 unsigned int i
, type_mask
= IORESOURCE_IO
| IORESOURCE_MEM
;
407 struct resource
*devr
= &dev
->resource
[idx
], *busr
;
412 pci_bus_for_each_resource(dev
->bus
, busr
, i
) {
413 if (!busr
|| ((busr
->flags
^ devr
->flags
) & type_mask
))
415 if ((devr
->start
) && (devr
->start
>= busr
->start
) &&
416 (devr
->end
<= busr
->end
))
422 static void pcibios_fixup_resources(struct pci_dev
*dev
, int start
, int limit
)
426 for (i
= start
; i
< limit
; i
++) {
427 if (!dev
->resource
[i
].flags
)
429 if ((is_valid_resource(dev
, i
)))
430 pci_claim_resource(dev
, i
);
434 void pcibios_fixup_device_resources(struct pci_dev
*dev
)
436 pcibios_fixup_resources(dev
, 0, PCI_BRIDGE_RESOURCES
);
438 EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources
);
440 static void pcibios_fixup_bridge_resources(struct pci_dev
*dev
)
442 pcibios_fixup_resources(dev
, PCI_BRIDGE_RESOURCES
, PCI_NUM_RESOURCES
);
446 * Called after each bus is probed, but before its children are examined.
448 void pcibios_fixup_bus(struct pci_bus
*b
)
453 pci_read_bridge_bases(b
);
454 pcibios_fixup_bridge_resources(b
->self
);
456 list_for_each_entry(dev
, &b
->devices
, bus_list
)
457 pcibios_fixup_device_resources(dev
);
458 platform_pci_fixup_bus(b
);
461 void pcibios_set_master (struct pci_dev
*dev
)
463 /* No special bus mastering setup handling */
467 pcibios_enable_device (struct pci_dev
*dev
, int mask
)
471 ret
= pci_enable_resources(dev
, mask
);
475 if (!dev
->msi_enabled
)
476 return acpi_pci_irq_enable(dev
);
481 pcibios_disable_device (struct pci_dev
*dev
)
483 BUG_ON(atomic_read(&dev
->enable_cnt
));
484 if (!dev
->msi_enabled
)
485 acpi_pci_irq_disable(dev
);
489 pcibios_align_resource (void *data
, const struct resource
*res
,
490 resource_size_t size
, resource_size_t align
)
496 pci_mmap_page_range (struct pci_dev
*dev
, struct vm_area_struct
*vma
,
497 enum pci_mmap_state mmap_state
, int write_combine
)
499 unsigned long size
= vma
->vm_end
- vma
->vm_start
;
503 * I/O space cannot be accessed via normal processor loads and
504 * stores on this platform.
506 if (mmap_state
== pci_mmap_io
)
508 * XXX we could relax this for I/O spaces for which ACPI
509 * indicates that the space is 1-to-1 mapped. But at the
510 * moment, we don't support multiple PCI address spaces and
511 * the legacy I/O space is not 1-to-1 mapped, so this is moot.
515 if (!valid_mmap_phys_addr_range(vma
->vm_pgoff
, size
))
518 prot
= phys_mem_access_prot(NULL
, vma
->vm_pgoff
, size
,
522 * If the user requested WC, the kernel uses UC or WC for this region,
523 * and the chipset supports WC, we can use WC. Otherwise, we have to
524 * use the same attribute the kernel uses.
527 ((pgprot_val(prot
) & _PAGE_MA_MASK
) == _PAGE_MA_UC
||
528 (pgprot_val(prot
) & _PAGE_MA_MASK
) == _PAGE_MA_WC
) &&
529 efi_range_is_wc(vma
->vm_start
, vma
->vm_end
- vma
->vm_start
))
530 vma
->vm_page_prot
= pgprot_writecombine(vma
->vm_page_prot
);
532 vma
->vm_page_prot
= prot
;
534 if (remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
535 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
))
542 * ia64_pci_get_legacy_mem - generic legacy mem routine
543 * @bus: bus to get legacy memory base address for
545 * Find the base of legacy memory for @bus. This is typically the first
546 * megabyte of bus address space for @bus or is simply 0 on platforms whose
547 * chipsets support legacy I/O and memory routing. Returns the base address
548 * or an error pointer if an error occurred.
550 * This is the ia64 generic version of this routine. Other platforms
551 * are free to override it with a machine vector.
553 char *ia64_pci_get_legacy_mem(struct pci_bus
*bus
)
555 return (char *)__IA64_UNCACHED_OFFSET
;
559 * pci_mmap_legacy_page_range - map legacy memory space to userland
560 * @bus: bus whose legacy space we're mapping
561 * @vma: vma passed in by mmap
563 * Map legacy memory space for this device back to userspace using a machine
564 * vector to get the base address.
567 pci_mmap_legacy_page_range(struct pci_bus
*bus
, struct vm_area_struct
*vma
,
568 enum pci_mmap_state mmap_state
)
570 unsigned long size
= vma
->vm_end
- vma
->vm_start
;
574 /* We only support mmap'ing of legacy memory space */
575 if (mmap_state
!= pci_mmap_mem
)
579 * Avoid attribute aliasing. See Documentation/ia64/aliasing.txt
582 if (!valid_mmap_phys_addr_range(vma
->vm_pgoff
, size
))
584 prot
= phys_mem_access_prot(NULL
, vma
->vm_pgoff
, size
,
587 addr
= pci_get_legacy_mem(bus
);
589 return PTR_ERR(addr
);
591 vma
->vm_pgoff
+= (unsigned long)addr
>> PAGE_SHIFT
;
592 vma
->vm_page_prot
= prot
;
594 if (remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
595 size
, vma
->vm_page_prot
))
602 * ia64_pci_legacy_read - read from legacy I/O space
604 * @port: legacy port value
605 * @val: caller allocated storage for returned value
606 * @size: number of bytes to read
608 * Simply reads @size bytes from @port and puts the result in @val.
610 * Again, this (and the write routine) are generic versions that can be
611 * overridden by the platform. This is necessary on platforms that don't
612 * support legacy I/O routing or that hard fail on legacy I/O timeouts.
614 int ia64_pci_legacy_read(struct pci_bus
*bus
, u16 port
, u32
*val
, u8 size
)
637 * ia64_pci_legacy_write - perform a legacy I/O write
639 * @port: port to write
640 * @val: value to write
641 * @size: number of bytes to write from @val
643 * Simply writes @size bytes of @val to @port.
645 int ia64_pci_legacy_write(struct pci_bus
*bus
, u16 port
, u32 val
, u8 size
)
668 * set_pci_cacheline_size - determine cacheline size for PCI devices
670 * We want to use the line-size of the outer-most cache. We assume
671 * that this line-size is the same for all CPUs.
673 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
675 static void __init
set_pci_dfl_cacheline_size(void)
677 unsigned long levels
, unique_caches
;
679 pal_cache_config_info_t cci
;
681 status
= ia64_pal_cache_summary(&levels
, &unique_caches
);
683 printk(KERN_ERR
"%s: ia64_pal_cache_summary() failed "
684 "(status=%ld)\n", __func__
, status
);
688 status
= ia64_pal_cache_config_info(levels
- 1,
689 /* cache_type (data_or_unified)= */ 2, &cci
);
691 printk(KERN_ERR
"%s: ia64_pal_cache_config_info() failed "
692 "(status=%ld)\n", __func__
, status
);
695 pci_dfl_cache_line_size
= (1 << cci
.pcci_line_size
) / 4;
698 u64
ia64_dma_get_required_mask(struct device
*dev
)
700 u32 low_totalram
= ((max_pfn
- 1) << PAGE_SHIFT
);
701 u32 high_totalram
= ((max_pfn
- 1) >> (32 - PAGE_SHIFT
));
704 if (!high_totalram
) {
705 /* convert to mask just covering totalram */
706 low_totalram
= (1 << (fls(low_totalram
) - 1));
707 low_totalram
+= low_totalram
- 1;
710 high_totalram
= (1 << (fls(high_totalram
) - 1));
711 high_totalram
+= high_totalram
- 1;
712 mask
= (((u64
)high_totalram
) << 32) + 0xffffffff;
716 EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask
);
718 u64
dma_get_required_mask(struct device
*dev
)
720 return platform_dma_get_required_mask(dev
);
722 EXPORT_SYMBOL_GPL(dma_get_required_mask
);
724 static int __init
pcibios_init(void)
726 set_pci_dfl_cacheline_size();
730 subsys_initcall(pcibios_init
);