arch/m32r/boot/compressed/m32r_sio.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * arch/m32r/boot/compressed/m32r_sio.c
   4  *
   5  * 2003-02-12:  Takeo Takahashi
   6  * 2006-11-30:  OPSPUT support by Kazuhiro Inaoka
   7  *
   8  */
   9
  10 #include <asm/processor.h>
  11
  12 static void m32r_putc(char c);
  13
  14 static int puts(const char *s)
  15 {
  16         char c;
  17         while ((c = *s++))
  18                 m32r_putc(c);
  19         return 0;
  20 }
  21
  22 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT)
  23 #include <asm/m32r.h>
  24 #include <asm/io.h>
  25
  26 #define USE_FPGA_MAP    0
  27
  28 #if USE_FPGA_MAP
  29 /*
  30  * fpga configuration program uses MMU, and define map as same as
  31  * M32104 uT-Engine board.
  32  */
  33 #define BOOT_SIO0STS    (volatile unsigned short *)(0x02c00000 + 0x20006)
  34 #define BOOT_SIO0TXB    (volatile unsigned short *)(0x02c00000 + 0x2000c)
  35 #else
  36 #undef PLD_BASE
  37 #if defined(CONFIG_PLAT_OPSPUT)
  38 #define PLD_BASE        0x1cc00000
  39 #else
  40 #define PLD_BASE        0xa4c00000
  41 #endif
  42 #define BOOT_SIO0STS    PLD_ESIO0STS
  43 #define BOOT_SIO0TXB    PLD_ESIO0TXB
  44 #endif
  45
  46 static void m32r_putc(char c)
  47 {
  48         while ((*BOOT_SIO0STS & 0x3) != 0x3)
  49                 cpu_relax();
  50         if (c == '\n') {
  51                 *BOOT_SIO0TXB = '\r';
  52                 while ((*BOOT_SIO0STS & 0x3) != 0x3)
  53                         cpu_relax();
  54         }
  55         *BOOT_SIO0TXB = c;
  56 }
  57 #else /* !(CONFIG_PLAT_M32700UT) */
  58 #if defined(CONFIG_PLAT_MAPPI2)
  59 #define SIO0STS (volatile unsigned short *)(0xa0efd000 + 14)
  60 #define SIO0TXB (volatile unsigned short *)(0xa0efd000 + 30)
  61 #else
  62 #define SIO0STS (volatile unsigned short *)(0x00efd000 + 14)
  63 #define SIO0TXB (volatile unsigned short *)(0x00efd000 + 30)
  64 #endif
  65
  66 static void m32r_putc(char c)
  67 {
  68         while ((*SIO0STS & 0x1) == 0)
  69                 cpu_relax();
  70         if (c == '\n') {
  71                 *SIO0TXB = '\r';
  72                 while ((*SIO0STS & 0x1) == 0)
  73                         cpu_relax();
  74         }
  75         *SIO0TXB = c;
  76 }
  77 #endif