arch/m32r/kernel/setup_opsput.c

   1 /*
   2  *  linux/arch/m32r/kernel/setup_opsput.c
   3  *
   4  *  Setup routines for Renesas OPSPUT Board
   5  *
   6  *  Copyright (c) 2002-2005
   7  *      Hiroyuki Kondo, Hirokazu Takata,
   8  *      Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa
   9  *
  10  *  This file is subject to the terms and conditions of the GNU General
  11  *  Public License.  See the file "COPYING" in the main directory of this
  12  *  archive for more details.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/irq.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/platform_device.h>
  20
  21 #include <asm/system.h>
  22 #include <asm/m32r.h>
  23 #include <asm/io.h>
  24
  25 /*
  26  * OPSP Interrupt Control Unit (Level 1)
  27  */
  28 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
  29
  30 icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];
  31
  32 static void disable_opsput_irq(unsigned int irq)
  33 {
  34         unsigned long port, data;
  35
  36         port = irq2port(irq);
  37         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
  38         outl(data, port);
  39 }
  40
  41 static void enable_opsput_irq(unsigned int irq)
  42 {
  43         unsigned long port, data;
  44
  45         port = irq2port(irq);
  46         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
  47         outl(data, port);
  48 }
  49
  50 static void mask_and_ack_opsput(unsigned int irq)
  51 {
  52         disable_opsput_irq(irq);
  53 }
  54
  55 static void end_opsput_irq(unsigned int irq)
  56 {
  57         enable_opsput_irq(irq);
  58 }
  59
  60 static unsigned int startup_opsput_irq(unsigned int irq)
  61 {
  62         enable_opsput_irq(irq);
  63         return (0);
  64 }
  65
  66 static void shutdown_opsput_irq(unsigned int irq)
  67 {
  68         unsigned long port;
  69
  70         port = irq2port(irq);
  71         outl(M32R_ICUCR_ILEVEL7, port);
  72 }
  73
  74 static struct hw_interrupt_type opsput_irq_type =
  75 {
  76         .typename = "OPSPUT-IRQ",
  77         .startup = startup_opsput_irq,
  78         .shutdown = shutdown_opsput_irq,
  79         .enable = enable_opsput_irq,
  80         .disable = disable_opsput_irq,
  81         .ack = mask_and_ack_opsput,
  82         .end = end_opsput_irq
  83 };
  84
  85 /*
  86  * Interrupt Control Unit of PLD on OPSPUT (Level 2)
  87  */
  88 #define irq2pldirq(x)           ((x) - OPSPUT_PLD_IRQ_BASE)
  89 #define pldirq2port(x)          (unsigned long)((int)PLD_ICUCR1 + \
  90                                  (((x) - 1) * sizeof(unsigned short)))
  91
  92 typedef struct {
  93         unsigned short icucr;  /* ICU Control Register */
  94 } pld_icu_data_t;
  95
  96 static pld_icu_data_t pld_icu_data[OPSPUT_NUM_PLD_IRQ];
  97
  98 static void disable_opsput_pld_irq(unsigned int irq)
  99 {
 100         unsigned long port, data;
 101         unsigned int pldirq;
 102
 103         pldirq = irq2pldirq(irq);
 104 //      disable_opsput_irq(M32R_IRQ_INT1);
 105         port = pldirq2port(pldirq);
 106         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
 107         outw(data, port);
 108 }
 109
 110 static void enable_opsput_pld_irq(unsigned int irq)
 111 {
 112         unsigned long port, data;
 113         unsigned int pldirq;
 114
 115         pldirq = irq2pldirq(irq);
 116 //      enable_opsput_irq(M32R_IRQ_INT1);
 117         port = pldirq2port(pldirq);
 118         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
 119         outw(data, port);
 120 }
 121
 122 static void mask_and_ack_opsput_pld(unsigned int irq)
 123 {
 124         disable_opsput_pld_irq(irq);
 125 //      mask_and_ack_opsput(M32R_IRQ_INT1);
 126 }
 127
 128 static void end_opsput_pld_irq(unsigned int irq)
 129 {
 130         enable_opsput_pld_irq(irq);
 131         end_opsput_irq(M32R_IRQ_INT1);
 132 }
 133
 134 static unsigned int startup_opsput_pld_irq(unsigned int irq)
 135 {
 136         enable_opsput_pld_irq(irq);
 137         return (0);
 138 }
 139
 140 static void shutdown_opsput_pld_irq(unsigned int irq)
 141 {
 142         unsigned long port;
 143         unsigned int pldirq;
 144
 145         pldirq = irq2pldirq(irq);
 146 //      shutdown_opsput_irq(M32R_IRQ_INT1);
 147         port = pldirq2port(pldirq);
 148         outw(PLD_ICUCR_ILEVEL7, port);
 149 }
 150
 151 static struct hw_interrupt_type opsput_pld_irq_type =
 152 {
 153         .typename = "OPSPUT-PLD-IRQ",
 154         .startup = startup_opsput_pld_irq,
 155         .shutdown = shutdown_opsput_pld_irq,
 156         .enable = enable_opsput_pld_irq,
 157         .disable = disable_opsput_pld_irq,
 158         .ack = mask_and_ack_opsput_pld,
 159         .end = end_opsput_pld_irq
 160 };
 161
 162 /*
 163  * Interrupt Control Unit of PLD on OPSPUT-LAN (Level 2)
 164  */
 165 #define irq2lanpldirq(x)        ((x) - OPSPUT_LAN_PLD_IRQ_BASE)
 166 #define lanpldirq2port(x)       (unsigned long)((int)OPSPUT_LAN_ICUCR1 + \
 167                                  (((x) - 1) * sizeof(unsigned short)))
 168
 169 static pld_icu_data_t lanpld_icu_data[OPSPUT_NUM_LAN_PLD_IRQ];
 170
 171 static void disable_opsput_lanpld_irq(unsigned int irq)
 172 {
 173         unsigned long port, data;
 174         unsigned int pldirq;
 175
 176         pldirq = irq2lanpldirq(irq);
 177         port = lanpldirq2port(pldirq);
 178         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
 179         outw(data, port);
 180 }
 181
 182 static void enable_opsput_lanpld_irq(unsigned int irq)
 183 {
 184         unsigned long port, data;
 185         unsigned int pldirq;
 186
 187         pldirq = irq2lanpldirq(irq);
 188         port = lanpldirq2port(pldirq);
 189         data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
 190         outw(data, port);
 191 }
 192
 193 static void mask_and_ack_opsput_lanpld(unsigned int irq)
 194 {
 195         disable_opsput_lanpld_irq(irq);
 196 }
 197
 198 static void end_opsput_lanpld_irq(unsigned int irq)
 199 {
 200         enable_opsput_lanpld_irq(irq);
 201         end_opsput_irq(M32R_IRQ_INT0);
 202 }
 203
 204 static unsigned int startup_opsput_lanpld_irq(unsigned int irq)
 205 {
 206         enable_opsput_lanpld_irq(irq);
 207         return (0);
 208 }
 209
 210 static void shutdown_opsput_lanpld_irq(unsigned int irq)
 211 {
 212         unsigned long port;
 213         unsigned int pldirq;
 214
 215         pldirq = irq2lanpldirq(irq);
 216         port = lanpldirq2port(pldirq);
 217         outw(PLD_ICUCR_ILEVEL7, port);
 218 }
 219
 220 static struct hw_interrupt_type opsput_lanpld_irq_type =
 221 {
 222         "OPSPUT-PLD-LAN-IRQ",
 223         startup_opsput_lanpld_irq,
 224         shutdown_opsput_lanpld_irq,
 225         enable_opsput_lanpld_irq,
 226         disable_opsput_lanpld_irq,
 227         mask_and_ack_opsput_lanpld,
 228         end_opsput_lanpld_irq
 229 };
 230
 231 /*
 232  * Interrupt Control Unit of PLD on OPSPUT-LCD (Level 2)
 233  */
 234 #define irq2lcdpldirq(x)        ((x) - OPSPUT_LCD_PLD_IRQ_BASE)
 235 #define lcdpldirq2port(x)       (unsigned long)((int)OPSPUT_LCD_ICUCR1 + \
 236                                  (((x) - 1) * sizeof(unsigned short)))
 237
 238 static pld_icu_data_t lcdpld_icu_data[OPSPUT_NUM_LCD_PLD_IRQ];
 239
 240 static void disable_opsput_lcdpld_irq(unsigned int irq)
 241 {
 242         unsigned long port, data;
 243         unsigned int pldirq;
 244
 245         pldirq = irq2lcdpldirq(irq);
 246         port = lcdpldirq2port(pldirq);
 247         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
 248         outw(data, port);
 249 }
 250
 251 static void enable_opsput_lcdpld_irq(unsigned int irq)
 252 {
 253         unsigned long port, data;
 254         unsigned int pldirq;
 255
 256         pldirq = irq2lcdpldirq(irq);
 257         port = lcdpldirq2port(pldirq);
 258         data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
 259         outw(data, port);
 260 }
 261
 262 static void mask_and_ack_opsput_lcdpld(unsigned int irq)
 263 {
 264         disable_opsput_lcdpld_irq(irq);
 265 }
 266
 267 static void end_opsput_lcdpld_irq(unsigned int irq)
 268 {
 269         enable_opsput_lcdpld_irq(irq);
 270         end_opsput_irq(M32R_IRQ_INT2);
 271 }
 272
 273 static unsigned int startup_opsput_lcdpld_irq(unsigned int irq)
 274 {
 275         enable_opsput_lcdpld_irq(irq);
 276         return (0);
 277 }
 278
 279 static void shutdown_opsput_lcdpld_irq(unsigned int irq)
 280 {
 281         unsigned long port;
 282         unsigned int pldirq;
 283
 284         pldirq = irq2lcdpldirq(irq);
 285         port = lcdpldirq2port(pldirq);
 286         outw(PLD_ICUCR_ILEVEL7, port);
 287 }
 288
 289 static struct hw_interrupt_type opsput_lcdpld_irq_type =
 290 {
 291         "OPSPUT-PLD-LCD-IRQ",
 292         startup_opsput_lcdpld_irq,
 293         shutdown_opsput_lcdpld_irq,
 294         enable_opsput_lcdpld_irq,
 295         disable_opsput_lcdpld_irq,
 296         mask_and_ack_opsput_lcdpld,
 297         end_opsput_lcdpld_irq
 298 };
 299
 300 void __init init_IRQ(void)
 301 {
 302 #if defined(CONFIG_SMC91X)
 303         /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
 304         irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED;
 305         irq_desc[OPSPUT_LAN_IRQ_LAN].handler = &opsput_lanpld_irq_type;
 306         irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0;
 307         irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
 308         lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;     /* "H" edge sense */
 309         disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
 310 #endif  /* CONFIG_SMC91X */
 311
 312         /* MFT2 : system timer */
 313         irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
 314         irq_desc[M32R_IRQ_MFT2].handler = &opsput_irq_type;
 315         irq_desc[M32R_IRQ_MFT2].action = 0;
 316         irq_desc[M32R_IRQ_MFT2].depth = 1;
 317         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
 318         disable_opsput_irq(M32R_IRQ_MFT2);
 319
 320         /* SIO0 : receive */
 321         irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
 322         irq_desc[M32R_IRQ_SIO0_R].handler = &opsput_irq_type;
 323         irq_desc[M32R_IRQ_SIO0_R].action = 0;
 324         irq_desc[M32R_IRQ_SIO0_R].depth = 1;
 325         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
 326         disable_opsput_irq(M32R_IRQ_SIO0_R);
 327
 328         /* SIO0 : send */
 329         irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
 330         irq_desc[M32R_IRQ_SIO0_S].handler = &opsput_irq_type;
 331         irq_desc[M32R_IRQ_SIO0_S].action = 0;
 332         irq_desc[M32R_IRQ_SIO0_S].depth = 1;
 333         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
 334         disable_opsput_irq(M32R_IRQ_SIO0_S);
 335
 336         /* SIO1 : receive */
 337         irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
 338         irq_desc[M32R_IRQ_SIO1_R].handler = &opsput_irq_type;
 339         irq_desc[M32R_IRQ_SIO1_R].action = 0;
 340         irq_desc[M32R_IRQ_SIO1_R].depth = 1;
 341         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
 342         disable_opsput_irq(M32R_IRQ_SIO1_R);
 343
 344         /* SIO1 : send */
 345         irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
 346         irq_desc[M32R_IRQ_SIO1_S].handler = &opsput_irq_type;
 347         irq_desc[M32R_IRQ_SIO1_S].action = 0;
 348         irq_desc[M32R_IRQ_SIO1_S].depth = 1;
 349         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
 350         disable_opsput_irq(M32R_IRQ_SIO1_S);
 351
 352         /* DMA1 : */
 353         irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
 354         irq_desc[M32R_IRQ_DMA1].handler = &opsput_irq_type;
 355         irq_desc[M32R_IRQ_DMA1].action = 0;
 356         irq_desc[M32R_IRQ_DMA1].depth = 1;
 357         icu_data[M32R_IRQ_DMA1].icucr = 0;
 358         disable_opsput_irq(M32R_IRQ_DMA1);
 359
 360 #ifdef CONFIG_SERIAL_M32R_PLDSIO
 361         /* INT#1: SIO0 Receive on PLD */
 362         irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
 363         irq_desc[PLD_IRQ_SIO0_RCV].handler = &opsput_pld_irq_type;
 364         irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
 365         irq_desc[PLD_IRQ_SIO0_RCV].depth = 1;   /* disable nested irq */
 366         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
 367         disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
 368
 369         /* INT#1: SIO0 Send on PLD */
 370         irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
 371         irq_desc[PLD_IRQ_SIO0_SND].handler = &opsput_pld_irq_type;
 372         irq_desc[PLD_IRQ_SIO0_SND].action = 0;
 373         irq_desc[PLD_IRQ_SIO0_SND].depth = 1;   /* disable nested irq */
 374         pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
 375         disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
 376 #endif  /* CONFIG_SERIAL_M32R_PLDSIO */
 377
 378 #if defined(CONFIG_M32R_CFC)
 379         /* INT#1: CFC IREQ on PLD */
 380         irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
 381         irq_desc[PLD_IRQ_CFIREQ].handler = &opsput_pld_irq_type;
 382         irq_desc[PLD_IRQ_CFIREQ].action = 0;
 383         irq_desc[PLD_IRQ_CFIREQ].depth = 1;     /* disable nested irq */
 384         pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;       /* 'L' level sense */
 385         disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
 386
 387         /* INT#1: CFC Insert on PLD */
 388         irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
 389         irq_desc[PLD_IRQ_CFC_INSERT].handler = &opsput_pld_irq_type;
 390         irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
 391         irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
 392         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;   /* 'L' edge sense */
 393         disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
 394
 395         /* INT#1: CFC Eject on PLD */
 396         irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
 397         irq_desc[PLD_IRQ_CFC_EJECT].handler = &opsput_pld_irq_type;
 398         irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
 399         irq_desc[PLD_IRQ_CFC_EJECT].depth = 1;  /* disable nested irq */
 400         pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;    /* 'H' edge sense */
 401         disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
 402 #endif /* CONFIG_M32R_CFC */
 403
 404
 405         /*
 406          * INT0# is used for LAN, DIO
 407          * We enable it here.
 408          */
 409         icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
 410         enable_opsput_irq(M32R_IRQ_INT0);
 411
 412         /*
 413          * INT1# is used for UART, MMC, CF Controller in FPGA.
 414          * We enable it here.
 415          */
 416         icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
 417         enable_opsput_irq(M32R_IRQ_INT1);
 418
 419 #if defined(CONFIG_USB)
 420         outw(USBCR_OTGS, USBCR);        /* USBCR: non-OTG */
 421
 422     irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
 423     irq_desc[OPSPUT_LCD_IRQ_USB_INT1].handler = &opsput_lcdpld_irq_type;
 424     irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0;
 425     irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1;
 426     lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;    /* "L" level sense */
 427     disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
 428 #endif
 429         /*
 430          * INT2# is used for BAT, USB, AUDIO
 431          * We enable it here.
 432          */
 433         icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
 434         enable_opsput_irq(M32R_IRQ_INT2);
 435
 436 #if defined(CONFIG_VIDEO_M32R_AR)
 437         /*
 438          * INT3# is used for AR
 439          */
 440         irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
 441         irq_desc[M32R_IRQ_INT3].handler = &opsput_irq_type;
 442         irq_desc[M32R_IRQ_INT3].action = 0;
 443         irq_desc[M32R_IRQ_INT3].depth = 1;
 444         icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
 445         disable_opsput_irq(M32R_IRQ_INT3);
 446 #endif /* CONFIG_VIDEO_M32R_AR */
 447 }
 448
 449 #if defined(CONFIG_SMC91X)
 450
 451 #define LAN_IOSTART     0x300
 452 #define LAN_IOEND       0x320
 453 static struct resource smc91x_resources[] = {
 454         [0] = {
 455                 .start  = (LAN_IOSTART),
 456                 .end    = (LAN_IOEND),
 457                 .flags  = IORESOURCE_MEM,
 458         },
 459         [1] = {
 460                 .start  = OPSPUT_LAN_IRQ_LAN,
 461                 .end    = OPSPUT_LAN_IRQ_LAN,
 462                 .flags  = IORESOURCE_IRQ,
 463         }
 464 };
 465
 466 static struct platform_device smc91x_device = {
 467         .name           = "smc91x",
 468         .id             = 0,
 469         .num_resources  = ARRAY_SIZE(smc91x_resources),
 470         .resource       = smc91x_resources,
 471 };
 472 #endif
 473
 474 #if defined(CONFIG_FB_S1D13XXX)
 475
 476 #include <video/s1d13xxxfb.h>
 477 #include <asm/s1d13806.h>
 478
 479 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
 480         .initregs               = s1d13xxxfb_initregs,
 481         .initregssize           = ARRAY_SIZE(s1d13xxxfb_initregs),
 482         .platform_init_video    = NULL,
 483 #ifdef CONFIG_PM
 484         .platform_suspend_video = NULL,
 485         .platform_resume_video  = NULL,
 486 #endif
 487 };
 488
 489 static struct resource s1d13xxxfb_resources[] = {
 490         [0] = {
 491                 .start  = 0x10600000UL,
 492                 .end    = 0x1073FFFFUL,
 493                 .flags  = IORESOURCE_MEM,
 494         },
 495         [1] = {
 496                 .start  = 0x10400000UL,
 497                 .end    = 0x104001FFUL,
 498                 .flags  = IORESOURCE_MEM,
 499         }
 500 };
 501
 502 static struct platform_device s1d13xxxfb_device = {
 503         .name           = S1D_DEVICENAME,
 504         .id             = 0,
 505         .dev            = {
 506                 .platform_data  = &s1d13xxxfb_data,
 507         },
 508         .num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
 509         .resource       = s1d13xxxfb_resources,
 510 };
 511 #endif
 512
 513 static int __init platform_init(void)
 514 {
 515 #if defined(CONFIG_SMC91X)
 516         platform_device_register(&smc91x_device);
 517 #endif
 518 #if defined(CONFIG_FB_S1D13XXX)
 519         platform_device_register(&s1d13xxxfb_device);
 520 #endif
 521         return 0;
 522 }
 523 arch_initcall(platform_init);