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License cleanup: add SPDX GPL-2.0 license identifier to files with no license
[mirror_ubuntu-bionic-kernel.git] / arch / m68k / include / asm / MC68EZ328.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
4 *
5 * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
6 * Bear & Hare Software, Inc.
7 *
8 * Based on include/asm-m68knommu/MC68332.h
9 * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
10 * The Silver Hammer Group, Ltd.
11 *
12 */
13 #include <linux/compiler.h>
14
15 #ifndef _MC68EZ328_H_
16 #define _MC68EZ328_H_
17
18 #define BYTE_REF(addr) (*((volatile unsigned char*)addr))
19 #define WORD_REF(addr) (*((volatile unsigned short*)addr))
20 #define LONG_REF(addr) (*((volatile unsigned long*)addr))
21
22 #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
23 #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
24
25 /**********
26 *
27 * 0xFFFFF0xx -- System Control
28 *
29 **********/
30
31 /*
32 * System Control Register (SCR)
33 */
34 #define SCR_ADDR 0xfffff000
35 #define SCR BYTE_REF(SCR_ADDR)
36
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
38 #define SCR_DMAP 0x04 /* Double Map */
39 #define SCR_SO 0x08 /* Supervisor Only */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
41 #define SCR_PRV 0x20 /* Privilege Violation */
42 #define SCR_WPV 0x40 /* Write Protect Violation */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
44
45 /*
46 * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
47 */
48 #define MRR_ADDR 0xfffff004
49 #define MRR LONG_REF(MRR_ADDR)
50
51 /**********
52 *
53 * 0xFFFFF1xx -- Chip-Select logic
54 *
55 **********/
56
57 /*
58 * Chip Select Group Base Registers
59 */
60 #define CSGBA_ADDR 0xfffff100
61 #define CSGBB_ADDR 0xfffff102
62
63 #define CSGBC_ADDR 0xfffff104
64 #define CSGBD_ADDR 0xfffff106
65
66 #define CSGBA WORD_REF(CSGBA_ADDR)
67 #define CSGBB WORD_REF(CSGBB_ADDR)
68 #define CSGBC WORD_REF(CSGBC_ADDR)
69 #define CSGBD WORD_REF(CSGBD_ADDR)
70
71 /*
72 * Chip Select Registers
73 */
74 #define CSA_ADDR 0xfffff110
75 #define CSB_ADDR 0xfffff112
76 #define CSC_ADDR 0xfffff114
77 #define CSD_ADDR 0xfffff116
78
79 #define CSA WORD_REF(CSA_ADDR)
80 #define CSB WORD_REF(CSB_ADDR)
81 #define CSC WORD_REF(CSC_ADDR)
82 #define CSD WORD_REF(CSD_ADDR)
83
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
86 #define CSA_SIZ_SHIFT 1
87 #define CSA_WS_MASK 0x0070 /* Wait State */
88 #define CSA_WS_SHIFT 4
89 #define CSA_BSW 0x0080 /* Data Bus Width */
90 #define CSA_FLASH 0x0100 /* FLASH Memory Support */
91 #define CSA_RO 0x8000 /* Read-Only */
92
93 #define CSB_EN 0x0001 /* Chip-Select Enable */
94 #define CSB_SIZ_MASK 0x000e /* Chip-Select Size */
95 #define CSB_SIZ_SHIFT 1
96 #define CSB_WS_MASK 0x0070 /* Wait State */
97 #define CSB_WS_SHIFT 4
98 #define CSB_BSW 0x0080 /* Data Bus Width */
99 #define CSB_FLASH 0x0100 /* FLASH Memory Support */
100 #define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
101 #define CSB_UPSIZ_SHIFT 11
102 #define CSB_ROP 0x2000 /* Readonly if protected */
103 #define CSB_SOP 0x4000 /* Supervisor only if protected */
104 #define CSB_RO 0x8000 /* Read-Only */
105
106 #define CSC_EN 0x0001 /* Chip-Select Enable */
107 #define CSC_SIZ_MASK 0x000e /* Chip-Select Size */
108 #define CSC_SIZ_SHIFT 1
109 #define CSC_WS_MASK 0x0070 /* Wait State */
110 #define CSC_WS_SHIFT 4
111 #define CSC_BSW 0x0080 /* Data Bus Width */
112 #define CSC_FLASH 0x0100 /* FLASH Memory Support */
113 #define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
114 #define CSC_UPSIZ_SHIFT 11
115 #define CSC_ROP 0x2000 /* Readonly if protected */
116 #define CSC_SOP 0x4000 /* Supervisor only if protected */
117 #define CSC_RO 0x8000 /* Read-Only */
118
119 #define CSD_EN 0x0001 /* Chip-Select Enable */
120 #define CSD_SIZ_MASK 0x000e /* Chip-Select Size */
121 #define CSD_SIZ_SHIFT 1
122 #define CSD_WS_MASK 0x0070 /* Wait State */
123 #define CSD_WS_SHIFT 4
124 #define CSD_BSW 0x0080 /* Data Bus Width */
125 #define CSD_FLASH 0x0100 /* FLASH Memory Support */
126 #define CSD_DRAM 0x0200 /* Dram Selection */
127 #define CSD_COMB 0x0400 /* Combining */
128 #define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */
129 #define CSD_UPSIZ_SHIFT 11
130 #define CSD_ROP 0x2000 /* Readonly if protected */
131 #define CSD_SOP 0x4000 /* Supervisor only if protected */
132 #define CSD_RO 0x8000 /* Read-Only */
133
134 /*
135 * Emulation Chip-Select Register
136 */
137 #define EMUCS_ADDR 0xfffff118
138 #define EMUCS WORD_REF(EMUCS_ADDR)
139
140 #define EMUCS_WS_MASK 0x0070
141 #define EMUCS_WS_SHIFT 4
142
143 /**********
144 *
145 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
146 *
147 **********/
148
149 /*
150 * PLL Control Register
151 */
152 #define PLLCR_ADDR 0xfffff200
153 #define PLLCR WORD_REF(PLLCR_ADDR)
154
155 #define PLLCR_DISPLL 0x0008 /* Disable PLL */
156 #define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */
157 #define PLLCR_PRESC 0x0020 /* VCO prescaler */
158 #define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */
159 #define PLLCR_SYSCLK_SEL_SHIFT 8
160 #define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */
161 #define PLLCR_LCDCLK_SEL_SHIFT 11
162
163 /* '328-compatible definitions */
164 #define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK
165 #define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT
166
167 /*
168 * PLL Frequency Select Register
169 */
170 #define PLLFSR_ADDR 0xfffff202
171 #define PLLFSR WORD_REF(PLLFSR_ADDR)
172
173 #define PLLFSR_PC_MASK 0x00ff /* P Count */
174 #define PLLFSR_PC_SHIFT 0
175 #define PLLFSR_QC_MASK 0x0f00 /* Q Count */
176 #define PLLFSR_QC_SHIFT 8
177 #define PLLFSR_PROT 0x4000 /* Protect P & Q */
178 #define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */
179
180 /*
181 * Power Control Register
182 */
183 #define PCTRL_ADDR 0xfffff207
184 #define PCTRL BYTE_REF(PCTRL_ADDR)
185
186 #define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */
187 #define PCTRL_WIDTH_SHIFT 0
188 #define PCTRL_PCEN 0x80 /* Power Control Enable */
189
190 /**********
191 *
192 * 0xFFFFF3xx -- Interrupt Controller
193 *
194 **********/
195
196 /*
197 * Interrupt Vector Register
198 */
199 #define IVR_ADDR 0xfffff300
200 #define IVR BYTE_REF(IVR_ADDR)
201
202 #define IVR_VECTOR_MASK 0xF8
203
204 /*
205 * Interrupt control Register
206 */
207 #define ICR_ADDR 0xfffff302
208 #define ICR WORD_REF(ICR_ADDR)
209
210 #define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */
211 #define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */
212 #define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */
213 #define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */
214 #define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */
215 #define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */
216 #define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */
217 #define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */
218 #define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */
219
220 /*
221 * Interrupt Mask Register
222 */
223 #define IMR_ADDR 0xfffff304
224 #define IMR LONG_REF(IMR_ADDR)
225
226 /*
227 * Define the names for bit positions first. This is useful for
228 * request_irq
229 */
230 #define SPI_IRQ_NUM 0 /* SPI interrupt */
231 #define TMR_IRQ_NUM 1 /* Timer interrupt */
232 #define UART_IRQ_NUM 2 /* UART interrupt */
233 #define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */
234 #define RTC_IRQ_NUM 4 /* RTC interrupt */
235 #define KB_IRQ_NUM 6 /* Keyboard Interrupt */
236 #define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */
237 #define INT0_IRQ_NUM 8 /* External INT0 */
238 #define INT1_IRQ_NUM 9 /* External INT1 */
239 #define INT2_IRQ_NUM 10 /* External INT2 */
240 #define INT3_IRQ_NUM 11 /* External INT3 */
241 #define IRQ1_IRQ_NUM 16 /* IRQ1 */
242 #define IRQ2_IRQ_NUM 17 /* IRQ2 */
243 #define IRQ3_IRQ_NUM 18 /* IRQ3 */
244 #define IRQ6_IRQ_NUM 19 /* IRQ6 */
245 #define IRQ5_IRQ_NUM 20 /* IRQ5 */
246 #define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */
247 #define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */
248
249 /* '328-compatible definitions */
250 #define SPIM_IRQ_NUM SPI_IRQ_NUM
251 #define TMR1_IRQ_NUM TMR_IRQ_NUM
252
253 /*
254 * Here go the bitmasks themselves
255 */
256 #define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */
257 #define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */
258 #define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */
259 #define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */
260 #define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */
261 #define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */
262 #define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */
263 #define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */
264 #define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */
265 #define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */
266 #define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */
267 #define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */
268 #define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */
269 #define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */
270 #define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */
271 #define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */
272 #define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */
273 #define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */
274
275 /* '328-compatible definitions */
276 #define IMR_MSPIM IMR_MSPI
277 #define IMR_MTMR1 IMR_MTMR
278
279 /*
280 * Interrupt Status Register
281 */
282 #define ISR_ADDR 0xfffff30c
283 #define ISR LONG_REF(ISR_ADDR)
284
285 #define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
286 #define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
287 #define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
288 #define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
289 #define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
290 #define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
291 #define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
292 #define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
293 #define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
294 #define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
295 #define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
296 #define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
297 #define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
298 #define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
299 #define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
300 #define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
301 #define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
302 #define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
303
304 /* '328-compatible definitions */
305 #define ISR_SPIM ISR_SPI
306 #define ISR_TMR1 ISR_TMR
307
308 /*
309 * Interrupt Pending Register
310 */
311 #define IPR_ADDR 0xfffff30c
312 #define IPR LONG_REF(IPR_ADDR)
313
314 #define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */
315 #define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */
316 #define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */
317 #define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */
318 #define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */
319 #define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */
320 #define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */
321 #define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */
322 #define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */
323 #define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */
324 #define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */
325 #define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */
326 #define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */
327 #define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */
328 #define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */
329 #define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */
330 #define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */
331 #define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */
332
333 /* '328-compatible definitions */
334 #define IPR_SPIM IPR_SPI
335 #define IPR_TMR1 IPR_TMR
336
337 /**********
338 *
339 * 0xFFFFF4xx -- Parallel Ports
340 *
341 **********/
342
343 /*
344 * Port A
345 */
346 #define PADIR_ADDR 0xfffff400 /* Port A direction reg */
347 #define PADATA_ADDR 0xfffff401 /* Port A data register */
348 #define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */
349
350 #define PADIR BYTE_REF(PADIR_ADDR)
351 #define PADATA BYTE_REF(PADATA_ADDR)
352 #define PAPUEN BYTE_REF(PAPUEN_ADDR)
353
354 #define PA(x) (1 << (x))
355
356 /*
357 * Port B
358 */
359 #define PBDIR_ADDR 0xfffff408 /* Port B direction reg */
360 #define PBDATA_ADDR 0xfffff409 /* Port B data register */
361 #define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */
362 #define PBSEL_ADDR 0xfffff40b /* Port B Select Register */
363
364 #define PBDIR BYTE_REF(PBDIR_ADDR)
365 #define PBDATA BYTE_REF(PBDATA_ADDR)
366 #define PBPUEN BYTE_REF(PBPUEN_ADDR)
367 #define PBSEL BYTE_REF(PBSEL_ADDR)
368
369 #define PB(x) (1 << (x))
370
371 #define PB_CSB0 0x01 /* Use CSB0 as PB[0] */
372 #define PB_CSB1 0x02 /* Use CSB1 as PB[1] */
373 #define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */
374 #define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */
375 #define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */
376 #define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */
377 #define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */
378 #define PB_PWMO 0x80 /* Use PWMO as PB[7] */
379
380 /*
381 * Port C
382 */
383 #define PCDIR_ADDR 0xfffff410 /* Port C direction reg */
384 #define PCDATA_ADDR 0xfffff411 /* Port C data register */
385 #define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */
386 #define PCSEL_ADDR 0xfffff413 /* Port C Select Register */
387
388 #define PCDIR BYTE_REF(PCDIR_ADDR)
389 #define PCDATA BYTE_REF(PCDATA_ADDR)
390 #define PCPDEN BYTE_REF(PCPDEN_ADDR)
391 #define PCSEL BYTE_REF(PCSEL_ADDR)
392
393 #define PC(x) (1 << (x))
394
395 #define PC_LD0 0x01 /* Use LD0 as PC[0] */
396 #define PC_LD1 0x02 /* Use LD1 as PC[1] */
397 #define PC_LD2 0x04 /* Use LD2 as PC[2] */
398 #define PC_LD3 0x08 /* Use LD3 as PC[3] */
399 #define PC_LFLM 0x10 /* Use LFLM as PC[4] */
400 #define PC_LLP 0x20 /* Use LLP as PC[5] */
401 #define PC_LCLK 0x40 /* Use LCLK as PC[6] */
402 #define PC_LACD 0x80 /* Use LACD as PC[7] */
403
404 /*
405 * Port D
406 */
407 #define PDDIR_ADDR 0xfffff418 /* Port D direction reg */
408 #define PDDATA_ADDR 0xfffff419 /* Port D data register */
409 #define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */
410 #define PDSEL_ADDR 0xfffff41b /* Port D Select Register */
411 #define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */
412 #define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */
413 #define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */
414 #define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */
415
416 #define PDDIR BYTE_REF(PDDIR_ADDR)
417 #define PDDATA BYTE_REF(PDDATA_ADDR)
418 #define PDPUEN BYTE_REF(PDPUEN_ADDR)
419 #define PDSEL BYTE_REF(PDSEL_ADDR)
420 #define PDPOL BYTE_REF(PDPOL_ADDR)
421 #define PDIRQEN BYTE_REF(PDIRQEN_ADDR)
422 #define PDKBEN BYTE_REF(PDKBEN_ADDR)
423 #define PDIQEG BYTE_REF(PDIQEG_ADDR)
424
425 #define PD(x) (1 << (x))
426
427 #define PD_INT0 0x01 /* Use INT0 as PD[0] */
428 #define PD_INT1 0x02 /* Use INT1 as PD[1] */
429 #define PD_INT2 0x04 /* Use INT2 as PD[2] */
430 #define PD_INT3 0x08 /* Use INT3 as PD[3] */
431 #define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */
432 #define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */
433 #define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */
434 #define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */
435
436 /*
437 * Port E
438 */
439 #define PEDIR_ADDR 0xfffff420 /* Port E direction reg */
440 #define PEDATA_ADDR 0xfffff421 /* Port E data register */
441 #define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */
442 #define PESEL_ADDR 0xfffff423 /* Port E Select Register */
443
444 #define PEDIR BYTE_REF(PEDIR_ADDR)
445 #define PEDATA BYTE_REF(PEDATA_ADDR)
446 #define PEPUEN BYTE_REF(PEPUEN_ADDR)
447 #define PESEL BYTE_REF(PESEL_ADDR)
448
449 #define PE(x) (1 << (x))
450
451 #define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */
452 #define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */
453 #define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */
454 #define PE_DWE 0x08 /* Use DWE as PE[3] */
455 #define PE_RXD 0x10 /* Use RXD as PE[4] */
456 #define PE_TXD 0x20 /* Use TXD as PE[5] */
457 #define PE_RTS 0x40 /* Use RTS as PE[6] */
458 #define PE_CTS 0x80 /* Use CTS as PE[7] */
459
460 /*
461 * Port F
462 */
463 #define PFDIR_ADDR 0xfffff428 /* Port F direction reg */
464 #define PFDATA_ADDR 0xfffff429 /* Port F data register */
465 #define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */
466 #define PFSEL_ADDR 0xfffff42b /* Port F Select Register */
467
468 #define PFDIR BYTE_REF(PFDIR_ADDR)
469 #define PFDATA BYTE_REF(PFDATA_ADDR)
470 #define PFPUEN BYTE_REF(PFPUEN_ADDR)
471 #define PFSEL BYTE_REF(PFSEL_ADDR)
472
473 #define PF(x) (1 << (x))
474
475 #define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */
476 #define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */
477 #define PF_CLKO 0x04 /* Use CLKO as PF[2] */
478 #define PF_A20 0x08 /* Use A20 as PF[3] */
479 #define PF_A21 0x10 /* Use A21 as PF[4] */
480 #define PF_A22 0x20 /* Use A22 as PF[5] */
481 #define PF_A23 0x40 /* Use A23 as PF[6] */
482 #define PF_CSA1 0x80 /* Use CSA1 as PF[7] */
483
484 /*
485 * Port G
486 */
487 #define PGDIR_ADDR 0xfffff430 /* Port G direction reg */
488 #define PGDATA_ADDR 0xfffff431 /* Port G data register */
489 #define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */
490 #define PGSEL_ADDR 0xfffff433 /* Port G Select Register */
491
492 #define PGDIR BYTE_REF(PGDIR_ADDR)
493 #define PGDATA BYTE_REF(PGDATA_ADDR)
494 #define PGPUEN BYTE_REF(PGPUEN_ADDR)
495 #define PGSEL BYTE_REF(PGSEL_ADDR)
496
497 #define PG(x) (1 << (x))
498
499 #define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */
500 #define PG_A0 0x02 /* Use A0 as PG[1] */
501 #define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */
502 #define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */
503 #define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */
504 #define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */
505
506 /**********
507 *
508 * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
509 *
510 **********/
511
512 /*
513 * PWM Control Register
514 */
515 #define PWMC_ADDR 0xfffff500
516 #define PWMC WORD_REF(PWMC_ADDR)
517
518 #define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */
519 #define PWMC_CLKSEL_SHIFT 0
520 #define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */
521 #define PWMC_REPEAT_SHIFT 2
522 #define PWMC_EN 0x0010 /* Enable PWM */
523 #define PMNC_FIFOAV 0x0020 /* FIFO Available */
524 #define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */
525 #define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */
526 #define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */
527 #define PWMC_PRESCALER_SHIFT 8
528 #define PWMC_CLKSRC 0x8000 /* Clock Source Select */
529
530 /* '328-compatible definitions */
531 #define PWMC_PWMEN PWMC_EN
532
533 /*
534 * PWM Sample Register
535 */
536 #define PWMS_ADDR 0xfffff502
537 #define PWMS WORD_REF(PWMS_ADDR)
538
539 /*
540 * PWM Period Register
541 */
542 #define PWMP_ADDR 0xfffff504
543 #define PWMP BYTE_REF(PWMP_ADDR)
544
545 /*
546 * PWM Counter Register
547 */
548 #define PWMCNT_ADDR 0xfffff505
549 #define PWMCNT BYTE_REF(PWMCNT_ADDR)
550
551 /**********
552 *
553 * 0xFFFFF6xx -- General-Purpose Timer
554 *
555 **********/
556
557 /*
558 * Timer Control register
559 */
560 #define TCTL_ADDR 0xfffff600
561 #define TCTL WORD_REF(TCTL_ADDR)
562
563 #define TCTL_TEN 0x0001 /* Timer Enable */
564 #define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */
565 #define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */
566 #define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */
567 #define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */
568 #define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */
569 #define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */
570 #define TCTL_IRQEN 0x0010 /* IRQ Enable */
571 #define TCTL_OM 0x0020 /* Output Mode */
572 #define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */
573 #define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */
574 #define TCTL_CAP_FE 0x0080 /* Capture on falling edge */
575 #define TCTL_FRR 0x0010 /* Free-Run Mode */
576
577 /* '328-compatible definitions */
578 #define TCTL1_ADDR TCTL_ADDR
579 #define TCTL1 TCTL
580
581 /*
582 * Timer Prescaler Register
583 */
584 #define TPRER_ADDR 0xfffff602
585 #define TPRER WORD_REF(TPRER_ADDR)
586
587 /* '328-compatible definitions */
588 #define TPRER1_ADDR TPRER_ADDR
589 #define TPRER1 TPRER
590
591 /*
592 * Timer Compare Register
593 */
594 #define TCMP_ADDR 0xfffff604
595 #define TCMP WORD_REF(TCMP_ADDR)
596
597 /* '328-compatible definitions */
598 #define TCMP1_ADDR TCMP_ADDR
599 #define TCMP1 TCMP
600
601 /*
602 * Timer Capture register
603 */
604 #define TCR_ADDR 0xfffff606
605 #define TCR WORD_REF(TCR_ADDR)
606
607 /* '328-compatible definitions */
608 #define TCR1_ADDR TCR_ADDR
609 #define TCR1 TCR
610
611 /*
612 * Timer Counter Register
613 */
614 #define TCN_ADDR 0xfffff608
615 #define TCN WORD_REF(TCN_ADDR)
616
617 /* '328-compatible definitions */
618 #define TCN1_ADDR TCN_ADDR
619 #define TCN1 TCN
620
621 /*
622 * Timer Status Register
623 */
624 #define TSTAT_ADDR 0xfffff60a
625 #define TSTAT WORD_REF(TSTAT_ADDR)
626
627 #define TSTAT_COMP 0x0001 /* Compare Event occurred */
628 #define TSTAT_CAPT 0x0001 /* Capture Event occurred */
629
630 /* '328-compatible definitions */
631 #define TSTAT1_ADDR TSTAT_ADDR
632 #define TSTAT1 TSTAT
633
634 /**********
635 *
636 * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
637 *
638 **********/
639
640 /*
641 * SPIM Data Register
642 */
643 #define SPIMDATA_ADDR 0xfffff800
644 #define SPIMDATA WORD_REF(SPIMDATA_ADDR)
645
646 /*
647 * SPIM Control/Status Register
648 */
649 #define SPIMCONT_ADDR 0xfffff802
650 #define SPIMCONT WORD_REF(SPIMCONT_ADDR)
651
652 #define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */
653 #define SPIMCONT_BIT_COUNT_SHIFT 0
654 #define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */
655 #define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */
656 #define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */
657 #define SPIMCONT_IRQ 0x0080 /* Interrupt Request */
658 #define SPIMCONT_XCH 0x0100 /* Exchange */
659 #define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */
660 #define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */
661 #define SPIMCONT_DATA_RATE_SHIFT 13
662
663 /* '328-compatible definitions */
664 #define SPIMCONT_SPIMIRQ SPIMCONT_IRQ
665 #define SPIMCONT_SPIMEN SPIMCONT_ENABLE
666
667 /**********
668 *
669 * 0xFFFFF9xx -- UART
670 *
671 **********/
672
673 /*
674 * UART Status/Control Register
675 */
676 #define USTCNT_ADDR 0xfffff900
677 #define USTCNT WORD_REF(USTCNT_ADDR)
678
679 #define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */
680 #define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */
681 #define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */
682 #define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */
683 #define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */
684 #define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */
685 #define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */
686 #define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */
687 #define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */
688 #define USTCNT_STOP 0x0200 /* Stop bit transmission */
689 #define USTCNT_ODD 0x0400 /* Odd Parity */
690 #define USTCNT_PEN 0x0800 /* Parity Enable */
691 #define USTCNT_CLKM 0x1000 /* Clock Mode Select */
692 #define USTCNT_TXEN 0x2000 /* Transmitter Enable */
693 #define USTCNT_RXEN 0x4000 /* Receiver Enable */
694 #define USTCNT_UEN 0x8000 /* UART Enable */
695
696 /* '328-compatible definitions */
697 #define USTCNT_TXAVAILEN USTCNT_TXAE
698 #define USTCNT_TXHALFEN USTCNT_TXHE
699 #define USTCNT_TXEMPTYEN USTCNT_TXEE
700 #define USTCNT_RXREADYEN USTCNT_RXRE
701 #define USTCNT_RXHALFEN USTCNT_RXHE
702 #define USTCNT_RXFULLEN USTCNT_RXFE
703 #define USTCNT_CTSDELTAEN USTCNT_CTSD
704 #define USTCNT_ODD_EVEN USTCNT_ODD
705 #define USTCNT_PARITYEN USTCNT_PEN
706 #define USTCNT_CLKMODE USTCNT_CLKM
707 #define USTCNT_UARTEN USTCNT_UEN
708
709 /*
710 * UART Baud Control Register
711 */
712 #define UBAUD_ADDR 0xfffff902
713 #define UBAUD WORD_REF(UBAUD_ADDR)
714
715 #define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
716 #define UBAUD_PRESCALER_SHIFT 0
717 #define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divisor */
718 #define UBAUD_DIVIDE_SHIFT 8
719 #define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
720 #define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
721
722 /*
723 * UART Receiver Register
724 */
725 #define URX_ADDR 0xfffff904
726 #define URX WORD_REF(URX_ADDR)
727
728 #define URX_RXDATA_ADDR 0xfffff905
729 #define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
730
731 #define URX_RXDATA_MASK 0x00ff /* Received data */
732 #define URX_RXDATA_SHIFT 0
733 #define URX_PARITY_ERROR 0x0100 /* Parity Error */
734 #define URX_BREAK 0x0200 /* Break Detected */
735 #define URX_FRAME_ERROR 0x0400 /* Framing Error */
736 #define URX_OVRUN 0x0800 /* Serial Overrun */
737 #define URX_OLD_DATA 0x1000 /* Old data in FIFO */
738 #define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
739 #define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
740 #define URX_FIFO_FULL 0x8000 /* FIFO is Full */
741
742 /*
743 * UART Transmitter Register
744 */
745 #define UTX_ADDR 0xfffff906
746 #define UTX WORD_REF(UTX_ADDR)
747
748 #define UTX_TXDATA_ADDR 0xfffff907
749 #define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
750
751 #define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
752 #define UTX_TXDATA_SHIFT 0
753 #define UTX_CTS_DELTA 0x0100 /* CTS changed */
754 #define UTX_CTS_STAT 0x0200 /* CTS State */
755 #define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */
756 #define UTX_NOCTS 0x0800 /* Ignore CTS */
757 #define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
758 #define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
759 #define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
760 #define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
761
762 /* '328-compatible definitions */
763 #define UTX_CTS_STATUS UTX_CTS_STAT
764 #define UTX_IGNORE_CTS UTX_NOCTS
765
766 /*
767 * UART Miscellaneous Register
768 */
769 #define UMISC_ADDR 0xfffff908
770 #define UMISC WORD_REF(UMISC_ADDR)
771
772 #define UMISC_TX_POL 0x0004 /* Transmit Polarity */
773 #define UMISC_RX_POL 0x0008 /* Receive Polarity */
774 #define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
775 #define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
776 #define UMISC_RTS 0x0040 /* Set RTS status */
777 #define UMISC_RTSCONT 0x0080 /* Choose RTS control */
778 #define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */
779 #define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */
780 #define UMISC_LOOP 0x1000 /* Serial Loopback Enable */
781 #define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */
782 #define UMISC_CLKSRC 0x4000 /* Clock Source */
783 #define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */
784
785 /*
786 * UART Non-integer Prescaler Register
787 */
788 #define NIPR_ADDR 0xfffff90a
789 #define NIPR WORD_REF(NIPR_ADDR)
790
791 #define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */
792 #define NIPR_STEP_VALUE_SHIFT 0
793 #define NIPR_SELECT_MASK 0x0700 /* Tap Selection */
794 #define NIPR_SELECT_SHIFT 8
795 #define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */
796
797
798 /* generalization of uart control registers to support multiple ports: */
799 typedef volatile struct {
800 volatile unsigned short int ustcnt;
801 volatile unsigned short int ubaud;
802 union {
803 volatile unsigned short int w;
804 struct {
805 volatile unsigned char status;
806 volatile unsigned char rxdata;
807 } b;
808 } urx;
809 union {
810 volatile unsigned short int w;
811 struct {
812 volatile unsigned char status;
813 volatile unsigned char txdata;
814 } b;
815 } utx;
816 volatile unsigned short int umisc;
817 volatile unsigned short int nipr;
818 volatile unsigned short int pad1;
819 volatile unsigned short int pad2;
820 } __packed m68328_uart;
821
822
823 /**********
824 *
825 * 0xFFFFFAxx -- LCD Controller
826 *
827 **********/
828
829 /*
830 * LCD Screen Starting Address Register
831 */
832 #define LSSA_ADDR 0xfffffa00
833 #define LSSA LONG_REF(LSSA_ADDR)
834
835 #define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */
836
837 /*
838 * LCD Virtual Page Width Register
839 */
840 #define LVPW_ADDR 0xfffffa05
841 #define LVPW BYTE_REF(LVPW_ADDR)
842
843 /*
844 * LCD Screen Width Register (not compatible with '328 !!!)
845 */
846 #define LXMAX_ADDR 0xfffffa08
847 #define LXMAX WORD_REF(LXMAX_ADDR)
848
849 #define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */
850
851 /*
852 * LCD Screen Height Register
853 */
854 #define LYMAX_ADDR 0xfffffa0a
855 #define LYMAX WORD_REF(LYMAX_ADDR)
856
857 #define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */
858
859 /*
860 * LCD Cursor X Position Register
861 */
862 #define LCXP_ADDR 0xfffffa18
863 #define LCXP WORD_REF(LCXP_ADDR)
864
865 #define LCXP_CC_MASK 0xc000 /* Cursor Control */
866 #define LCXP_CC_TRAMSPARENT 0x0000
867 #define LCXP_CC_BLACK 0x4000
868 #define LCXP_CC_REVERSED 0x8000
869 #define LCXP_CC_WHITE 0xc000
870 #define LCXP_CXP_MASK 0x02ff /* Cursor X position */
871
872 /*
873 * LCD Cursor Y Position Register
874 */
875 #define LCYP_ADDR 0xfffffa1a
876 #define LCYP WORD_REF(LCYP_ADDR)
877
878 #define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */
879
880 /*
881 * LCD Cursor Width and Heigth Register
882 */
883 #define LCWCH_ADDR 0xfffffa1c
884 #define LCWCH WORD_REF(LCWCH_ADDR)
885
886 #define LCWCH_CH_MASK 0x001f /* Cursor Height */
887 #define LCWCH_CH_SHIFT 0
888 #define LCWCH_CW_MASK 0x1f00 /* Cursor Width */
889 #define LCWCH_CW_SHIFT 8
890
891 /*
892 * LCD Blink Control Register
893 */
894 #define LBLKC_ADDR 0xfffffa1f
895 #define LBLKC BYTE_REF(LBLKC_ADDR)
896
897 #define LBLKC_BD_MASK 0x7f /* Blink Divisor */
898 #define LBLKC_BD_SHIFT 0
899 #define LBLKC_BKEN 0x80 /* Blink Enabled */
900
901 /*
902 * LCD Panel Interface Configuration Register
903 */
904 #define LPICF_ADDR 0xfffffa20
905 #define LPICF BYTE_REF(LPICF_ADDR)
906
907 #define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
908 #define LPICF_GS_BW 0x00
909 #define LPICF_GS_GRAY_4 0x01
910 #define LPICF_GS_GRAY_16 0x02
911 #define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */
912 #define LPICF_PBSIZ_1 0x00
913 #define LPICF_PBSIZ_2 0x04
914 #define LPICF_PBSIZ_4 0x08
915
916 /*
917 * LCD Polarity Configuration Register
918 */
919 #define LPOLCF_ADDR 0xfffffa21
920 #define LPOLCF BYTE_REF(LPOLCF_ADDR)
921
922 #define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
923 #define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
924 #define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
925 #define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
926
927 /*
928 * LACD (LCD Alternate Crystal Direction) Rate Control Register
929 */
930 #define LACDRC_ADDR 0xfffffa23
931 #define LACDRC BYTE_REF(LACDRC_ADDR)
932
933 #define LACDRC_ACDSLT 0x80 /* Signal Source Select */
934 #define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
935 #define LACDRC_ACD_SHIFT 0
936
937 /*
938 * LCD Pixel Clock Divider Register
939 */
940 #define LPXCD_ADDR 0xfffffa25
941 #define LPXCD BYTE_REF(LPXCD_ADDR)
942
943 #define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
944 #define LPXCD_PCD_SHIFT 0
945
946 /*
947 * LCD Clocking Control Register
948 */
949 #define LCKCON_ADDR 0xfffffa27
950 #define LCKCON BYTE_REF(LCKCON_ADDR)
951
952 #define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
953 #define LCKCON_DWS_SHIFT 0
954 #define LCKCON_DWIDTH 0x40 /* Display Memory Width */
955 #define LCKCON_LCDON 0x80 /* Enable LCD Controller */
956
957 /* '328-compatible definitions */
958 #define LCKCON_DW_MASK LCKCON_DWS_MASK
959 #define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
960
961 /*
962 * LCD Refresh Rate Adjustment Register
963 */
964 #define LRRA_ADDR 0xfffffa29
965 #define LRRA BYTE_REF(LRRA_ADDR)
966
967 /*
968 * LCD Panning Offset Register
969 */
970 #define LPOSR_ADDR 0xfffffa2d
971 #define LPOSR BYTE_REF(LPOSR_ADDR)
972
973 #define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */
974 #define LPOSR_POS_SHIFT 0
975
976 /*
977 * LCD Frame Rate Control Modulation Register
978 */
979 #define LFRCM_ADDR 0xfffffa31
980 #define LFRCM BYTE_REF(LFRCM_ADDR)
981
982 #define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
983 #define LFRCM_YMOD_SHIFT 0
984 #define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
985 #define LFRCM_XMOD_SHIFT 4
986
987 /*
988 * LCD Gray Palette Mapping Register
989 */
990 #define LGPMR_ADDR 0xfffffa33
991 #define LGPMR BYTE_REF(LGPMR_ADDR)
992
993 #define LGPMR_G1_MASK 0x0f
994 #define LGPMR_G1_SHIFT 0
995 #define LGPMR_G2_MASK 0xf0
996 #define LGPMR_G2_SHIFT 4
997
998 /*
999 * PWM Contrast Control Register
1000 */
1001 #define PWMR_ADDR 0xfffffa36
1002 #define PWMR WORD_REF(PWMR_ADDR)
1003
1004 #define PWMR_PW_MASK 0x00ff /* Pulse Width */
1005 #define PWMR_PW_SHIFT 0
1006 #define PWMR_CCPEN 0x0100 /* Contrast Control Enable */
1007 #define PWMR_SRC_MASK 0x0600 /* Input Clock Source */
1008 #define PWMR_SRC_LINE 0x0000 /* Line Pulse */
1009 #define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */
1010 #define PWMR_SRC_LCD 0x4000 /* LCD clock */
1011
1012 /**********
1013 *
1014 * 0xFFFFFBxx -- Real-Time Clock (RTC)
1015 *
1016 **********/
1017
1018 /*
1019 * RTC Hours Minutes and Seconds Register
1020 */
1021 #define RTCTIME_ADDR 0xfffffb00
1022 #define RTCTIME LONG_REF(RTCTIME_ADDR)
1023
1024 #define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
1025 #define RTCTIME_SECONDS_SHIFT 0
1026 #define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
1027 #define RTCTIME_MINUTES_SHIFT 16
1028 #define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
1029 #define RTCTIME_HOURS_SHIFT 24
1030
1031 /*
1032 * RTC Alarm Register
1033 */
1034 #define RTCALRM_ADDR 0xfffffb04
1035 #define RTCALRM LONG_REF(RTCALRM_ADDR)
1036
1037 #define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
1038 #define RTCALRM_SECONDS_SHIFT 0
1039 #define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
1040 #define RTCALRM_MINUTES_SHIFT 16
1041 #define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
1042 #define RTCALRM_HOURS_SHIFT 24
1043
1044 /*
1045 * Watchdog Timer Register
1046 */
1047 #define WATCHDOG_ADDR 0xfffffb0a
1048 #define WATCHDOG WORD_REF(WATCHDOG_ADDR)
1049
1050 #define WATCHDOG_EN 0x0001 /* Watchdog Enabled */
1051 #define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */
1052 #define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occurred */
1053 #define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */
1054 #define WATCHDOG_CNT_SHIFT 8
1055
1056 /*
1057 * RTC Control Register
1058 */
1059 #define RTCCTL_ADDR 0xfffffb0c
1060 #define RTCCTL WORD_REF(RTCCTL_ADDR)
1061
1062 #define RTCCTL_XTL 0x0020 /* Crystal Selection */
1063 #define RTCCTL_EN 0x0080 /* RTC Enable */
1064
1065 /* '328-compatible definitions */
1066 #define RTCCTL_384 RTCCTL_XTL
1067 #define RTCCTL_ENABLE RTCCTL_EN
1068
1069 /*
1070 * RTC Interrupt Status Register
1071 */
1072 #define RTCISR_ADDR 0xfffffb0e
1073 #define RTCISR WORD_REF(RTCISR_ADDR)
1074
1075 #define RTCISR_SW 0x0001 /* Stopwatch timed out */
1076 #define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
1077 #define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
1078 #define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
1079 #define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
1080 #define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
1081 #define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */
1082 #define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */
1083 #define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */
1084 #define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */
1085 #define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */
1086 #define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */
1087 #define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */
1088 #define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */
1089
1090 /*
1091 * RTC Interrupt Enable Register
1092 */
1093 #define RTCIENR_ADDR 0xfffffb10
1094 #define RTCIENR WORD_REF(RTCIENR_ADDR)
1095
1096 #define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
1097 #define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
1098 #define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
1099 #define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
1100 #define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
1101 #define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */
1102 #define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */
1103 #define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */
1104 #define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */
1105 #define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */
1106 #define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */
1107 #define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */
1108 #define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */
1109 #define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */
1110
1111 /*
1112 * Stopwatch Minutes Register
1113 */
1114 #define STPWCH_ADDR 0xfffffb12
1115 #define STPWCH WORD_REF(STPWCH)
1116
1117 #define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */
1118 #define SPTWCH_CNT_SHIFT 0
1119
1120 /*
1121 * RTC Day Count Register
1122 */
1123 #define DAYR_ADDR 0xfffffb1a
1124 #define DAYR WORD_REF(DAYR_ADDR)
1125
1126 #define DAYR_DAYS_MASK 0x1ff /* Day Setting */
1127 #define DAYR_DAYS_SHIFT 0
1128
1129 /*
1130 * RTC Day Alarm Register
1131 */
1132 #define DAYALARM_ADDR 0xfffffb1c
1133 #define DAYALARM WORD_REF(DAYALARM_ADDR)
1134
1135 #define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */
1136 #define DAYALARM_DAYSAL_SHIFT 0
1137
1138 /**********
1139 *
1140 * 0xFFFFFCxx -- DRAM Controller
1141 *
1142 **********/
1143
1144 /*
1145 * DRAM Memory Configuration Register
1146 */
1147 #define DRAMMC_ADDR 0xfffffc00
1148 #define DRAMMC WORD_REF(DRAMMC_ADDR)
1149
1150 #define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */
1151 #define DRAMMC_ROW12_PA10 0x0000
1152 #define DRAMMC_ROW12_PA21 0x4000
1153 #define DRAMMC_ROW12_PA23 0x8000
1154 #define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */
1155 #define DRAMMC_ROW0_PA11 0x0000
1156 #define DRAMMC_ROW0_PA22 0x1000
1157 #define DRAMMC_ROW0_PA23 0x2000
1158 #define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */
1159 #define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */
1160 #define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */
1161 #define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */
1162 #define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */
1163 #define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */
1164 #define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */
1165 #define DRAMMC_REF_MASK 0x001f /* Refresh Cycle */
1166 #define DRAMMC_REF_SHIFT 0
1167
1168 /*
1169 * DRAM Control Register
1170 */
1171 #define DRAMC_ADDR 0xfffffc02
1172 #define DRAMC WORD_REF(DRAMC_ADDR)
1173
1174 #define DRAMC_DWE 0x0001 /* DRAM Write Enable */
1175 #define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */
1176 #define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */
1177 #define DRAMC_SLW 0x0008 /* Slow RAM */
1178 #define DRAMC_LSP 0x0010 /* Light Sleep */
1179 #define DRAMC_MSW 0x0020 /* Slow Multiplexing */
1180 #define DRAMC_WS_MASK 0x00c0 /* Wait-states */
1181 #define DRAMC_WS_SHIFT 6
1182 #define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */
1183 #define DRAMC_PGSZ_SHIFT 8
1184 #define DRAMC_PGSZ_256K 0x0000
1185 #define DRAMC_PGSZ_512K 0x0100
1186 #define DRAMC_PGSZ_1024K 0x0200
1187 #define DRAMC_PGSZ_2048K 0x0300
1188 #define DRAMC_EDO 0x0400 /* EDO DRAM */
1189 #define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */
1190 #define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */
1191 #define DRAMC_BC_SHIFT 12
1192 #define DRAMC_RM 0x4000 /* Refresh Mode */
1193 #define DRAMC_EN 0x8000 /* DRAM Controller enable */
1194
1195
1196 /**********
1197 *
1198 * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
1199 *
1200 **********/
1201
1202 /*
1203 * ICE Module Address Compare Register
1204 */
1205 #define ICEMACR_ADDR 0xfffffd00
1206 #define ICEMACR LONG_REF(ICEMACR_ADDR)
1207
1208 /*
1209 * ICE Module Address Mask Register
1210 */
1211 #define ICEMAMR_ADDR 0xfffffd04
1212 #define ICEMAMR LONG_REF(ICEMAMR_ADDR)
1213
1214 /*
1215 * ICE Module Control Compare Register
1216 */
1217 #define ICEMCCR_ADDR 0xfffffd08
1218 #define ICEMCCR WORD_REF(ICEMCCR_ADDR)
1219
1220 #define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */
1221 #define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */
1222
1223 /*
1224 * ICE Module Control Mask Register
1225 */
1226 #define ICEMCMR_ADDR 0xfffffd0a
1227 #define ICEMCMR WORD_REF(ICEMCMR_ADDR)
1228
1229 #define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */
1230 #define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */
1231
1232 /*
1233 * ICE Module Control Register
1234 */
1235 #define ICEMCR_ADDR 0xfffffd0c
1236 #define ICEMCR WORD_REF(ICEMCR_ADDR)
1237
1238 #define ICEMCR_CEN 0x0001 /* Compare Enable */
1239 #define ICEMCR_PBEN 0x0002 /* Program Break Enable */
1240 #define ICEMCR_SB 0x0004 /* Single Breakpoint */
1241 #define ICEMCR_HMDIS 0x0008 /* HardMap disable */
1242 #define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */
1243
1244 /*
1245 * ICE Module Status Register
1246 */
1247 #define ICEMSR_ADDR 0xfffffd0e
1248 #define ICEMSR WORD_REF(ICEMSR_ADDR)
1249
1250 #define ICEMSR_EMUEN 0x0001 /* Emulation Enable */
1251 #define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */
1252 #define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */
1253 #define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */
1254
1255 #endif /* _MC68EZ328_H_ */
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