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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - arch/m68k/include/asm/atomic.h
1 #ifndef __ARCH_M68K_ATOMIC__
2 #define __ARCH_M68K_ATOMIC__
4 #include <linux/types.h>
5 #include <linux/irqflags.h>
6 #include <asm/cmpxchg.h>
7 #include <asm/barrier.h>
10 * Atomic operations that C can't guarantee us. Useful for
11 * resource counting etc..
15 * We do not have SMP m68k systems, so we don't have to deal with that.
18 #define ATOMIC_INIT(i) { (i) }
20 #define atomic_read(v) READ_ONCE((v)->counter)
21 #define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
24 * The ColdFire parts cannot do some immediate to memory operations,
25 * so for them we do not specify the "i" asm constraint.
27 #ifdef CONFIG_COLDFIRE
33 #define ATOMIC_OP(op, c_op, asm_op) \
34 static inline void atomic_##op(int i, atomic_t *v) \
36 __asm__ __volatile__(#asm_op "l %1,%0" : "+m" (*v) : ASM_DI (i));\
39 #ifdef CONFIG_RMW_INSNS
41 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
42 static inline int atomic_##op##_return(int i, atomic_t *v) \
46 __asm__ __volatile__( \
48 " " #asm_op "l %3,%1\n" \
51 : "+m" (*v), "=&d" (t), "=&d" (tmp) \
52 : "g" (i), "2" (atomic_read(v))); \
56 #define ATOMIC_FETCH_OP(op, c_op, asm_op) \
57 static inline int atomic_fetch_##op(int i, atomic_t *v) \
61 __asm__ __volatile__( \
63 " " #asm_op "l %3,%1\n" \
66 : "+m" (*v), "=&d" (t), "=&d" (tmp) \
67 : "g" (i), "2" (atomic_read(v))); \
73 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
74 static inline int atomic_##op##_return(int i, atomic_t * v) \
76 unsigned long flags; \
79 local_irq_save(flags); \
80 t = (v->counter c_op i); \
81 local_irq_restore(flags); \
86 #define ATOMIC_FETCH_OP(op, c_op, asm_op) \
87 static inline int atomic_fetch_##op(int i, atomic_t * v) \
89 unsigned long flags; \
92 local_irq_save(flags); \
95 local_irq_restore(flags); \
100 #endif /* CONFIG_RMW_INSNS */
102 #define ATOMIC_OPS(op, c_op, asm_op) \
103 ATOMIC_OP(op, c_op, asm_op) \
104 ATOMIC_OP_RETURN(op, c_op, asm_op) \
105 ATOMIC_FETCH_OP(op, c_op, asm_op)
107 ATOMIC_OPS(add
, +=, add
)
108 ATOMIC_OPS(sub
, -=, sub
)
111 #define ATOMIC_OPS(op, c_op, asm_op) \
112 ATOMIC_OP(op, c_op, asm_op) \
113 ATOMIC_FETCH_OP(op, c_op, asm_op)
115 ATOMIC_OPS(and, &=, and)
116 ATOMIC_OPS(or, |=, or)
117 ATOMIC_OPS(xor, ^=, eor
)
120 #undef ATOMIC_FETCH_OP
121 #undef ATOMIC_OP_RETURN
124 static inline void atomic_inc(atomic_t
*v
)
126 __asm__
__volatile__("addql #1,%0" : "+m" (*v
));
129 static inline void atomic_dec(atomic_t
*v
)
131 __asm__
__volatile__("subql #1,%0" : "+m" (*v
));
134 static inline int atomic_dec_and_test(atomic_t
*v
)
137 __asm__
__volatile__("subql #1,%1; seq %0" : "=d" (c
), "+m" (*v
));
141 static inline int atomic_dec_and_test_lt(atomic_t
*v
)
144 __asm__
__volatile__(
145 "subql #1,%1; slt %0"
146 : "=d" (c
), "=m" (*v
)
151 static inline int atomic_inc_and_test(atomic_t
*v
)
154 __asm__
__volatile__("addql #1,%1; seq %0" : "=d" (c
), "+m" (*v
));
158 #ifdef CONFIG_RMW_INSNS
160 #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
161 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
163 #else /* !CONFIG_RMW_INSNS */
165 static inline int atomic_cmpxchg(atomic_t
*v
, int old
, int new)
170 local_irq_save(flags
);
171 prev
= atomic_read(v
);
174 local_irq_restore(flags
);
178 static inline int atomic_xchg(atomic_t
*v
, int new)
183 local_irq_save(flags
);
184 prev
= atomic_read(v
);
186 local_irq_restore(flags
);
190 #endif /* !CONFIG_RMW_INSNS */
192 #define atomic_dec_return(v) atomic_sub_return(1, (v))
193 #define atomic_inc_return(v) atomic_add_return(1, (v))
195 static inline int atomic_sub_and_test(int i
, atomic_t
*v
)
198 __asm__
__volatile__("subl %2,%1; seq %0"
199 : "=d" (c
), "+m" (*v
)
204 static inline int atomic_add_negative(int i
, atomic_t
*v
)
207 __asm__
__volatile__("addl %2,%1; smi %0"
208 : "=d" (c
), "+m" (*v
)
213 static __inline__
int __atomic_add_unless(atomic_t
*v
, int a
, int u
)
218 if (unlikely(c
== (u
)))
220 old
= atomic_cmpxchg((v
), c
, c
+ (a
));
221 if (likely(old
== c
))
228 #endif /* __ARCH_M68K_ATOMIC __ */