arch/m68k/include/asm/m525xsim.h

   1 /****************************************************************************/
   2
   3 /*
   4  *      m525xsim.h -- ColdFire 525x System Integration Module support.
   5  *
   6  *      (C) Copyright 2012, Steven king <sfking@fdwdc.com>
   7  *      (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
   8  */
   9
  10 /****************************************************************************/
  11 #ifndef m525xsim_h
  12 #define m525xsim_h
  13 /****************************************************************************/
  14
  15 /*
  16  *      This header supports ColdFire 5249, 5251 and 5253. There are a few
  17  *      little differences between them, but most of the peripheral support
  18  *      can be used by all of them.
  19  */
  20 #define CPU_NAME                "COLDFIRE(m525x)"
  21 #define CPU_INSTR_PER_JIFFY     3
  22 #define MCF_BUSCLK              (MCF_CLK / 2)
  23
  24 #include <asm/m52xxacr.h>
  25
  26 /*
  27  *      The 525x has a second MBAR region, define its address.
  28  */
  29 #define MCF_MBAR2               0x80000000
  30
  31 /*
  32  *      Define the 525x SIM register set addresses.
  33  */
  34 #define MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status */
  35 #define MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
  36 #define MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
  37 #define MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog srv */
  38 #define MCFSIM_MPARK            (MCF_MBAR + 0x0C)       /* BUS Master Ctrl */
  39 #define MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pending */
  40 #define MCFSIM_IMR              (MCF_MBAR + 0x44)       /* Interrupt Mask */
  41 #define MCFSIM_ICR0             (MCF_MBAR + 0x4c)       /* Intr Ctrl reg 0 */
  42 #define MCFSIM_ICR1             (MCF_MBAR + 0x4d)       /* Intr Ctrl reg 1 */
  43 #define MCFSIM_ICR2             (MCF_MBAR + 0x4e)       /* Intr Ctrl reg 2 */
  44 #define MCFSIM_ICR3             (MCF_MBAR + 0x4f)       /* Intr Ctrl reg 3 */
  45 #define MCFSIM_ICR4             (MCF_MBAR + 0x50)       /* Intr Ctrl reg 4 */
  46 #define MCFSIM_ICR5             (MCF_MBAR + 0x51)       /* Intr Ctrl reg 5 */
  47 #define MCFSIM_ICR6             (MCF_MBAR + 0x52)       /* Intr Ctrl reg 6 */
  48 #define MCFSIM_ICR7             (MCF_MBAR + 0x53)       /* Intr Ctrl reg 7 */
  49 #define MCFSIM_ICR8             (MCF_MBAR + 0x54)       /* Intr Ctrl reg 8 */
  50 #define MCFSIM_ICR9             (MCF_MBAR + 0x55)       /* Intr Ctrl reg 9 */
  51 #define MCFSIM_ICR10            (MCF_MBAR + 0x56)       /* Intr Ctrl reg 10 */
  52 #define MCFSIM_ICR11            (MCF_MBAR + 0x57)       /* Intr Ctrl reg 11 */
  53
  54 #define MCFSIM_CSAR0            (MCF_MBAR + 0x80)       /* CS 0 Address reg */
  55 #define MCFSIM_CSMR0            (MCF_MBAR + 0x84)       /* CS 0 Mask reg */
  56 #define MCFSIM_CSCR0            (MCF_MBAR + 0x8a)       /* CS 0 Control reg */
  57 #define MCFSIM_CSAR1            (MCF_MBAR + 0x8c)       /* CS 1 Address reg */
  58 #define MCFSIM_CSMR1            (MCF_MBAR + 0x90)       /* CS 1 Mask reg */
  59 #define MCFSIM_CSCR1            (MCF_MBAR + 0x96)       /* CS 1 Control reg */
  60 #define MCFSIM_CSAR2            (MCF_MBAR + 0x98)       /* CS 2 Address reg */
  61 #define MCFSIM_CSMR2            (MCF_MBAR + 0x9c)       /* CS 2 Mask reg */
  62 #define MCFSIM_CSCR2            (MCF_MBAR + 0xa2)       /* CS 2 Control reg */
  63 #define MCFSIM_CSAR3            (MCF_MBAR + 0xa4)       /* CS 3 Address reg */
  64 #define MCFSIM_CSMR3            (MCF_MBAR + 0xa8)       /* CS 3 Mask reg */
  65 #define MCFSIM_CSCR3            (MCF_MBAR + 0xae)       /* CS 3 Control reg */
  66 #define MCFSIM_CSAR4            (MCF_MBAR + 0xb0)       /* CS 4 Address reg */
  67 #define MCFSIM_CSMR4            (MCF_MBAR + 0xb4)       /* CS 4 Mask reg */
  68 #define MCFSIM_CSCR4            (MCF_MBAR + 0xba)       /* CS 4 Control reg */
  69
  70 #define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
  71 #define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
  72 #define MCFSIM_DMR0             (MCF_MBAR + 0x10c)      /* DRAM 0 Mask */
  73 #define MCFSIM_DACR1            (MCF_MBAR + 0x110)      /* DRAM 1 Addr/Ctrl */
  74 #define MCFSIM_DMR1             (MCF_MBAR + 0x114)      /* DRAM 1 Mask */
  75
  76 /*
  77  * Secondary Interrupt Controller (in MBAR2)
  78 */
  79 #define MCFINTC2_INTBASE        (MCF_MBAR2 + 0x168)     /* Base Vector Reg */
  80 #define MCFINTC2_INTPRI1        (MCF_MBAR2 + 0x140)     /* 0-7 priority */
  81 #define MCFINTC2_INTPRI2        (MCF_MBAR2 + 0x144)     /* 8-15 priority */
  82 #define MCFINTC2_INTPRI3        (MCF_MBAR2 + 0x148)     /* 16-23 priority */
  83 #define MCFINTC2_INTPRI4        (MCF_MBAR2 + 0x14c)     /* 24-31 priority */
  84 #define MCFINTC2_INTPRI5        (MCF_MBAR2 + 0x150)     /* 32-39 priority */
  85 #define MCFINTC2_INTPRI6        (MCF_MBAR2 + 0x154)     /* 40-47 priority */
  86 #define MCFINTC2_INTPRI7        (MCF_MBAR2 + 0x158)     /* 48-55 priority */
  87 #define MCFINTC2_INTPRI8        (MCF_MBAR2 + 0x15c)     /* 56-63 priority */
  88
  89 #define MCFINTC2_INTPRI_REG(i)  (MCFINTC2_INTPRI1 + \
  90                                 ((((i) - MCFINTC2_VECBASE) / 8) * 4))
  91 #define MCFINTC2_INTPRI_BITS(b, i)      ((b) << (((i) % 8) * 4))
  92
  93 /*
  94  *      Timer module.
  95  */
  96 #define MCFTIMER_BASE1          (MCF_MBAR + 0x140)      /* Base of TIMER1 */
  97 #define MCFTIMER_BASE2          (MCF_MBAR + 0x180)      /* Base of TIMER2 */
  98
  99 /*
 100  *      UART module.
 101  */
 102 #define MCFUART_BASE0           (MCF_MBAR + 0x1c0)      /* Base address UART0 */
 103 #define MCFUART_BASE1           (MCF_MBAR + 0x200)      /* Base address UART1 */
 104
 105 /*
 106  *      QSPI module.
 107  */
 108 #define MCFQSPI_BASE            (MCF_MBAR + 0x400)      /* Base address QSPI */
 109 #define MCFQSPI_SIZE            0x40                    /* Register set size */
 110
 111 #ifdef CONFIG_M5249
 112 #define MCFQSPI_CS0             29
 113 #define MCFQSPI_CS1             24
 114 #define MCFQSPI_CS2             21
 115 #define MCFQSPI_CS3             22
 116 #else
 117 #define MCFQSPI_CS0             15
 118 #define MCFQSPI_CS1             16
 119 #define MCFQSPI_CS2             24
 120 #define MCFQSPI_CS3             28
 121 #endif
 122
 123 /*
 124  *      I2C module.
 125  */
 126 #define MCFI2C_BASE0            (MCF_MBAR + 0x280)      /* Base address I2C0 */
 127 #define MCFI2C_SIZE0            0x20                    /* Register set size */
 128
 129 #define MCFI2C_BASE1            (MCF_MBAR2 + 0x440)     /* Base address I2C1 */
 130 #define MCFI2C_SIZE1            0x20                    /* Register set size */
 131
 132 /*
 133  *      DMA unit base addresses.
 134  */
 135 #define MCFDMA_BASE0            (MCF_MBAR + 0x300)      /* Base address DMA 0 */
 136 #define MCFDMA_BASE1            (MCF_MBAR + 0x340)      /* Base address DMA 1 */
 137 #define MCFDMA_BASE2            (MCF_MBAR + 0x380)      /* Base address DMA 2 */
 138 #define MCFDMA_BASE3            (MCF_MBAR + 0x3C0)      /* Base address DMA 3 */
 139
 140 /*
 141  *      Some symbol defines for the above...
 142  */
 143 #define MCFSIM_SWDICR           MCFSIM_ICR0     /* Watchdog timer ICR */
 144 #define MCFSIM_TIMER1ICR        MCFSIM_ICR1     /* Timer 1 ICR */
 145 #define MCFSIM_TIMER2ICR        MCFSIM_ICR2     /* Timer 2 ICR */
 146 #define MCFSIM_I2CICR           MCFSIM_ICR3     /* I2C ICR */
 147 #define MCFSIM_UART1ICR         MCFSIM_ICR4     /* UART 1 ICR */
 148 #define MCFSIM_UART2ICR         MCFSIM_ICR5     /* UART 2 ICR */
 149 #define MCFSIM_DMA0ICR          MCFSIM_ICR6     /* DMA 0 ICR */
 150 #define MCFSIM_DMA1ICR          MCFSIM_ICR7     /* DMA 1 ICR */
 151 #define MCFSIM_DMA2ICR          MCFSIM_ICR8     /* DMA 2 ICR */
 152 #define MCFSIM_DMA3ICR          MCFSIM_ICR9     /* DMA 3 ICR */
 153 #define MCFSIM_QSPIICR          MCFSIM_ICR10    /* QSPI ICR */
 154
 155 /*
 156  *      Define system peripheral IRQ usage.
 157  */
 158 #define MCF_IRQ_QSPI            28              /* QSPI, Level 4 */
 159 #define MCF_IRQ_I2C0            29
 160 #define MCF_IRQ_TIMER           30              /* Timer0, Level 6 */
 161 #define MCF_IRQ_PROFILER        31              /* Timer1, Level 7 */
 162
 163 #define MCF_IRQ_UART0           73              /* UART0 */
 164 #define MCF_IRQ_UART1           74              /* UART1 */
 165
 166 /*
 167  * Define the base interrupt for the second interrupt controller.
 168  * We set it to 128, out of the way of the base interrupts, and plenty
 169  * of room for its 64 interrupts.
 170  */
 171 #define MCFINTC2_VECBASE        128
 172
 173 #define MCF_IRQ_GPIO0           (MCFINTC2_VECBASE + 32)
 174 #define MCF_IRQ_GPIO1           (MCFINTC2_VECBASE + 33)
 175 #define MCF_IRQ_GPIO2           (MCFINTC2_VECBASE + 34)
 176 #define MCF_IRQ_GPIO3           (MCFINTC2_VECBASE + 35)
 177 #define MCF_IRQ_GPIO4           (MCFINTC2_VECBASE + 36)
 178 #define MCF_IRQ_GPIO5           (MCFINTC2_VECBASE + 37)
 179 #define MCF_IRQ_GPIO6           (MCFINTC2_VECBASE + 38)
 180 #define MCF_IRQ_GPIO7           (MCFINTC2_VECBASE + 39)
 181
 182 #define MCF_IRQ_USBWUP          (MCFINTC2_VECBASE + 40)
 183 #define MCF_IRQ_I2C1            (MCFINTC2_VECBASE + 62)
 184
 185 /*
 186  *      General purpose IO registers (in MBAR2).
 187  */
 188 #define MCFSIM2_GPIOREAD        (MCF_MBAR2 + 0x000)     /* GPIO read values */
 189 #define MCFSIM2_GPIOWRITE       (MCF_MBAR2 + 0x004)     /* GPIO write values */
 190 #define MCFSIM2_GPIOENABLE      (MCF_MBAR2 + 0x008)     /* GPIO enabled */
 191 #define MCFSIM2_GPIOFUNC        (MCF_MBAR2 + 0x00C)     /* GPIO function */
 192 #define MCFSIM2_GPIO1READ       (MCF_MBAR2 + 0x0B0)     /* GPIO1 read values */
 193 #define MCFSIM2_GPIO1WRITE      (MCF_MBAR2 + 0x0B4)     /* GPIO1 write values */
 194 #define MCFSIM2_GPIO1ENABLE     (MCF_MBAR2 + 0x0B8)     /* GPIO1 enabled */
 195 #define MCFSIM2_GPIO1FUNC       (MCF_MBAR2 + 0x0BC)     /* GPIO1 function */
 196
 197 #define MCFSIM2_GPIOINTSTAT     (MCF_MBAR2 + 0xc0)      /* GPIO intr status */
 198 #define MCFSIM2_GPIOINTCLEAR    (MCF_MBAR2 + 0xc0)      /* GPIO intr clear */
 199 #define MCFSIM2_GPIOINTENABLE   (MCF_MBAR2 + 0xc4)      /* GPIO intr enable */
 200
 201 #define MCFSIM2_DMAROUTE        (MCF_MBAR2 + 0x188)     /* DMA routing */
 202 #define MCFSIM2_IDECONFIG1      (MCF_MBAR2 + 0x18c)     /* IDEconfig1 */
 203 #define MCFSIM2_IDECONFIG2      (MCF_MBAR2 + 0x190)     /* IDEconfig2 */
 204
 205 /*
 206  * Generic GPIO support
 207  */
 208 #define MCFGPIO_PIN_MAX         64
 209 #ifdef CONFIG_M5249
 210 #define MCFGPIO_IRQ_MAX         -1
 211 #define MCFGPIO_IRQ_VECBASE     -1
 212 #else
 213 #define MCFGPIO_IRQ_MAX         7
 214 #define MCFGPIO_IRQ_VECBASE     MCF_IRQ_GPIO0
 215 #endif
 216
 217 /****************************************************************************/
 218
 219 #ifdef __ASSEMBLER__
 220 #ifdef CONFIG_M5249C3
 221 /*
 222  *      The M5249C3 board needs a little help getting all its SIM devices
 223  *      initialized at kernel start time. dBUG doesn't set much up, so
 224  *      we need to do it manually.
 225  */
 226 .macro m5249c3_setup
 227         /*
 228          *      Set MBAR1 and MBAR2, just incase they are not set.
 229          */
 230         movel   #0x10000001,%a0
 231         movec   %a0,%MBAR                       /* map MBAR region */
 232         subql   #1,%a0                          /* get MBAR address in a0 */
 233
 234         movel   #0x80000001,%a1
 235         movec   %a1,#3086                       /* map MBAR2 region */
 236         subql   #1,%a1                          /* get MBAR2 address in a1 */
 237
 238         /*
 239          *      Move secondary interrupts to their base (128).
 240          */
 241         moveb   #MCFINTC2_VECBASE,%d0
 242         moveb   %d0,0x16b(%a1)                  /* interrupt base register */
 243
 244         /*
 245          *      Work around broken CSMR0/DRAM vector problem.
 246          */
 247         movel   #0x001F0021,%d0                 /* disable C/I bit */
 248         movel   %d0,0x84(%a0)                   /* set CSMR0 */
 249
 250         /*
 251          *      Disable the PLL firstly. (Who knows what state it is
 252          *      in here!).
 253          */
 254         movel   0x180(%a1),%d0                  /* get current PLL value */
 255         andl    #0xfffffffe,%d0                 /* PLL bypass first */
 256         movel   %d0,0x180(%a1)                  /* set PLL register */
 257         nop
 258
 259 #if CONFIG_CLOCK_FREQ == 140000000
 260         /*
 261          *      Set initial clock frequency. This assumes M5249C3 board
 262          *      is fitted with 11.2896MHz crystal. It will program the
 263          *      PLL for 140MHz. Lets go fast :-)
 264          */
 265         movel   #0x125a40f0,%d0                 /* set for 140MHz */
 266         movel   %d0,0x180(%a1)                  /* set PLL register */
 267         orl     #0x1,%d0
 268         movel   %d0,0x180(%a1)                  /* set PLL register */
 269 #endif
 270
 271         /*
 272          *      Setup CS1 for ethernet controller.
 273          *      (Setup as per M5249C3 doco).
 274          */
 275         movel  #0xe0000000,%d0                  /* CS1 mapped at 0xe0000000 */
 276         movel  %d0,0x8c(%a0)
 277         movel  #0x001f0021,%d0                  /* CS1 size of 1Mb */
 278         movel  %d0,0x90(%a0)
 279         movew  #0x0080,%d0                      /* CS1 = 16bit port, AA */
 280         movew  %d0,0x96(%a0)
 281
 282         /*
 283          *      Setup CS2 for IDE interface.
 284          */
 285         movel   #0x50000000,%d0                 /* CS2 mapped at 0x50000000 */
 286         movel   %d0,0x98(%a0)
 287         movel   #0x001f0001,%d0                 /* CS2 size of 1MB */
 288         movel   %d0,0x9c(%a0)
 289         movew   #0x0080,%d0                     /* CS2 = 16bit, TA */
 290         movew   %d0,0xa2(%a0)
 291
 292         movel   #0x00107000,%d0                 /* IDEconfig1 */
 293         movel   %d0,0x18c(%a1)
 294         movel   #0x000c0400,%d0                 /* IDEconfig2 */
 295         movel   %d0,0x190(%a1)
 296
 297         movel   #0x00080000,%d0                 /* GPIO19, IDE reset bit */
 298         orl     %d0,0xc(%a1)                    /* function GPIO19 */
 299         orl     %d0,0x8(%a1)                    /* enable GPIO19 as output */
 300         orl     %d0,0x4(%a1)                    /* de-assert IDE reset */
 301 .endm
 302
 303 #define PLATFORM_SETUP  m5249c3_setup
 304
 305 #endif /* CONFIG_M5249C3 */
 306 #endif /* __ASSEMBLER__ */
 307 /****************************************************************************/
 308 #endif  /* m525xsim_h */