arch/m68k/include/asm/m548xsim.h

   1 /*
   2  *      m548xsim.h -- ColdFire 547x/548x System Integration Unit support.
   3  */
   4
   5 #ifndef m548xsim_h
   6 #define m548xsim_h
   7
   8 #define MCFINT_VECBASE      64
   9
  10 /*
  11  *      Interrupt Controller Registers
  12  */
  13 #define MCFICM_INTC0            0x0700          /* Base for Interrupt Ctrl 0 */
  14 #define MCFINTC_IPRH            0x00            /* Interrupt pending 32-63 */
  15 #define MCFINTC_IPRL            0x04            /* Interrupt pending 1-31 */
  16 #define MCFINTC_IMRH            0x08            /* Interrupt mask 32-63 */
  17 #define MCFINTC_IMRL            0x0c            /* Interrupt mask 1-31 */
  18 #define MCFINTC_INTFRCH         0x10            /* Interrupt force 32-63 */
  19 #define MCFINTC_INTFRCL         0x14            /* Interrupt force 1-31 */
  20 #define MCFINTC_IRLR            0x18            /* */
  21 #define MCFINTC_IACKL           0x19            /* */
  22 #define MCFINTC_ICR0            0x40            /* Base ICR register */
  23
  24 /*
  25  *      Define system peripheral IRQ usage.
  26  */
  27 #define MCF_IRQ_TIMER           (64 + 54)       /* Slice Timer 0 */
  28 #define MCF_IRQ_PROFILER        (64 + 53)       /* Slice Timer 1 */
  29
  30 /*
  31  *      Generic GPIO support
  32  */
  33 #define MCFGPIO_PIN_MAX         0       /* I am too lazy to count */
  34 #define MCFGPIO_IRQ_MAX         -1
  35 #define MCFGPIO_IRQ_VECBASE     -1
  36
  37 /*
  38  *      Some PSC related definitions
  39  */
  40 #define MCF_PAR_PSC(x)          (0x000A4F-((x)&0x3))
  41 #define MCF_PAR_SDA             (0x0008)
  42 #define MCF_PAR_SCL             (0x0004)
  43 #define MCF_PAR_PSC_TXD         (0x04)
  44 #define MCF_PAR_PSC_RXD         (0x08)
  45 #define MCF_PAR_PSC_RTS(x)      (((x)&0x03)<<4)
  46 #define MCF_PAR_PSC_CTS(x)      (((x)&0x03)<<6)
  47 #define MCF_PAR_PSC_CTS_GPIO    (0x00)
  48 #define MCF_PAR_PSC_CTS_BCLK    (0x80)
  49 #define MCF_PAR_PSC_CTS_CTS     (0xC0)
  50 #define MCF_PAR_PSC_RTS_GPIO    (0x00)
  51 #define MCF_PAR_PSC_RTS_FSYNC   (0x20)
  52 #define MCF_PAR_PSC_RTS_RTS     (0x30)
  53 #define MCF_PAR_PSC_CANRX       (0x40)
  54
  55 #endif  /* m548xsim_h */