arch/m68k/mac/psc.c

   1 /*
   2  *      Apple Peripheral System Controller (PSC)
   3  *
   4  *      The PSC is used on the AV Macs to control IO functions not handled
   5  *      by the VIAs (Ethernet, DSP, SCC).
   6  *
   7  * TO DO:
   8  *
   9  * Try to figure out what's going on in pIFR5 and pIFR6. There seem to be
  10  * persisant interrupt conditions in those registers and I have no idea what
  11  * they are. Granted it doesn't affect since we're not enabling any interrupts
  12  * on those levels at the moment, but it would be nice to know. I have a feeling
  13  * they aren't actually interrupt lines but data lines (to the DSP?)
  14  */
  15
  16 #include <linux/types.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mm.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21 #ifdef CONFIG_GENERIC_HARDIRQS
  22 #include <linux/irq.h>
  23 #endif
  24
  25 #include <asm/traps.h>
  26 #include <asm/bootinfo.h>
  27 #include <asm/macintosh.h>
  28 #include <asm/macints.h>
  29 #include <asm/mac_psc.h>
  30
  31 #define DEBUG_PSC
  32
  33 int psc_present;
  34 volatile __u8 *psc;
  35
  36 /*
  37  * Debugging dump, used in various places to see what's going on.
  38  */
  39
  40 static void psc_debug_dump(void)
  41 {
  42         int     i;
  43
  44         if (!psc_present) return;
  45         for (i = 0x30 ; i < 0x70 ; i += 0x10) {
  46                 printk("PSC #%d:  IFR = 0x%02X IER = 0x%02X\n",
  47                         i >> 4,
  48                         (int) psc_read_byte(pIFRbase + i),
  49                         (int) psc_read_byte(pIERbase + i));
  50         }
  51 }
  52
  53 /*
  54  * Try to kill all DMA channels on the PSC. Not sure how this his
  55  * supposed to work; this is code lifted from macmace.c and then
  56  * expanded to cover what I think are the other 7 channels.
  57  */
  58
  59 static void psc_dma_die_die_die(void)
  60 {
  61         int i;
  62
  63         printk("Killing all PSC DMA channels...");
  64         for (i = 0 ; i < 9 ; i++) {
  65                 psc_write_word(PSC_CTL_BASE + (i << 4), 0x8800);
  66                 psc_write_word(PSC_CTL_BASE + (i << 4), 0x1000);
  67                 psc_write_word(PSC_CMD_BASE + (i << 5), 0x1100);
  68                 psc_write_word(PSC_CMD_BASE + (i << 5) + 0x10, 0x1100);
  69         }
  70         printk("done!\n");
  71 }
  72
  73 /*
  74  * Initialize the PSC. For now this just involves shutting down all
  75  * interrupt sources using the IERs.
  76  */
  77
  78 void __init psc_init(void)
  79 {
  80         int i;
  81
  82         if (macintosh_config->ident != MAC_MODEL_C660
  83          && macintosh_config->ident != MAC_MODEL_Q840)
  84         {
  85                 psc = NULL;
  86                 psc_present = 0;
  87                 return;
  88         }
  89
  90         /*
  91          * The PSC is always at the same spot, but using psc
  92          * keeps things consistent with the psc_xxxx functions.
  93          */
  94
  95         psc = (void *) PSC_BASE;
  96         psc_present = 1;
  97
  98         printk("PSC detected at %p\n", psc);
  99
 100         psc_dma_die_die_die();
 101
 102 #ifdef DEBUG_PSC
 103         psc_debug_dump();
 104 #endif
 105         /*
 106          * Mask and clear all possible interrupts
 107          */
 108
 109         for (i = 0x30 ; i < 0x70 ; i += 0x10) {
 110                 psc_write_byte(pIERbase + i, 0x0F);
 111                 psc_write_byte(pIFRbase + i, 0x0F);
 112         }
 113 }
 114
 115 /*
 116  * PSC interrupt handler. It's a lot like the VIA interrupt handler.
 117  */
 118
 119 #ifdef CONFIG_GENERIC_HARDIRQS
 120 static void psc_irq(unsigned int irq, struct irq_desc *desc)
 121 {
 122         unsigned int offset = (unsigned int)irq_desc_get_handler_data(desc);
 123         int pIFR        = pIFRbase + offset;
 124         int pIER        = pIERbase + offset;
 125         int irq_num;
 126         unsigned char irq_bit, events;
 127
 128 #ifdef DEBUG_IRQS
 129         printk("psc_irq: irq %u pIFR = 0x%02X pIER = 0x%02X\n",
 130                 irq, (int) psc_read_byte(pIFR), (int) psc_read_byte(pIER));
 131 #endif
 132
 133         events = psc_read_byte(pIFR) & psc_read_byte(pIER) & 0xF;
 134         if (!events)
 135                 return;
 136
 137         irq_num = irq << 3;
 138         irq_bit = 1;
 139         do {
 140                 if (events & irq_bit) {
 141                         psc_write_byte(pIFR, irq_bit);
 142                         generic_handle_irq(irq_num);
 143                 }
 144                 irq_num++;
 145                 irq_bit <<= 1;
 146         } while (events >= irq_bit);
 147 }
 148 #else
 149 static irqreturn_t psc_irq(int irq, void *dev_id)
 150 {
 151         int pIFR        = pIFRbase + ((int) dev_id);
 152         int pIER        = pIERbase + ((int) dev_id);
 153         int irq_num;
 154         unsigned char irq_bit, events;
 155
 156 #ifdef DEBUG_IRQS
 157         printk("psc_irq: irq %d pIFR = 0x%02X pIER = 0x%02X\n",
 158                 irq, (int) psc_read_byte(pIFR), (int) psc_read_byte(pIER));
 159 #endif
 160
 161         events = psc_read_byte(pIFR) & psc_read_byte(pIER) & 0xF;
 162         if (!events)
 163                 return IRQ_NONE;
 164
 165         irq_num = irq << 3;
 166         irq_bit = 1;
 167         do {
 168                 if (events & irq_bit) {
 169                         psc_write_byte(pIFR, irq_bit);
 170                         generic_handle_irq(irq_num);
 171                 }
 172                 irq_num++;
 173                 irq_bit <<= 1;
 174         } while (events >= irq_bit);
 175         return IRQ_HANDLED;
 176 }
 177 #endif
 178
 179 /*
 180  * Register the PSC interrupt dispatchers for autovector interrupts 3-6.
 181  */
 182
 183 void __init psc_register_interrupts(void)
 184 {
 185 #ifdef CONFIG_GENERIC_HARDIRQS
 186         irq_set_chained_handler(IRQ_AUTO_3, psc_irq);
 187         irq_set_handler_data(IRQ_AUTO_3, (void *)0x30);
 188         irq_set_chained_handler(IRQ_AUTO_4, psc_irq);
 189         irq_set_handler_data(IRQ_AUTO_4, (void *)0x40);
 190         irq_set_chained_handler(IRQ_AUTO_5, psc_irq);
 191         irq_set_handler_data(IRQ_AUTO_5, (void *)0x50);
 192         irq_set_chained_handler(IRQ_AUTO_6, psc_irq);
 193         irq_set_handler_data(IRQ_AUTO_6, (void *)0x60);
 194 #else /* !CONFIG_GENERIC_HARDIRQS */
 195         if (request_irq(IRQ_AUTO_3, psc_irq, 0, "psc3", (void *) 0x30))
 196                 pr_err("Couldn't register psc%d interrupt\n", 3);
 197         if (request_irq(IRQ_AUTO_4, psc_irq, 0, "psc4", (void *) 0x40))
 198                 pr_err("Couldn't register psc%d interrupt\n", 4);
 199         if (request_irq(IRQ_AUTO_5, psc_irq, 0, "psc5", (void *) 0x50))
 200                 pr_err("Couldn't register psc%d interrupt\n", 5);
 201         if (request_irq(IRQ_AUTO_6, psc_irq, 0, "psc6", (void *) 0x60))
 202                 pr_err("Couldn't register psc%d interrupt\n", 6);
 203 #endif /* !CONFIG_GENERIC_HARDIRQS */
 204 }
 205
 206 void psc_irq_enable(int irq) {
 207         int irq_src     = IRQ_SRC(irq);
 208         int irq_idx     = IRQ_IDX(irq);
 209         int pIER        = pIERbase + (irq_src << 4);
 210
 211 #ifdef DEBUG_IRQUSE
 212         printk("psc_irq_enable(%d)\n", irq);
 213 #endif
 214         psc_write_byte(pIER, (1 << irq_idx) | 0x80);
 215 }
 216
 217 void psc_irq_disable(int irq) {
 218         int irq_src     = IRQ_SRC(irq);
 219         int irq_idx     = IRQ_IDX(irq);
 220         int pIER        = pIERbase + (irq_src << 4);
 221
 222 #ifdef DEBUG_IRQUSE
 223         printk("psc_irq_disable(%d)\n", irq);
 224 #endif
 225         psc_write_byte(pIER, 1 << irq_idx);
 226 }
 227
 228 void psc_irq_clear(int irq) {
 229         int irq_src     = IRQ_SRC(irq);
 230         int irq_idx     = IRQ_IDX(irq);
 231         int pIFR        = pIERbase + (irq_src << 4);
 232
 233         psc_write_byte(pIFR, 1 << irq_idx);
 234 }
 235
 236 int psc_irq_pending(int irq)
 237 {
 238         int irq_src     = IRQ_SRC(irq);
 239         int irq_idx     = IRQ_IDX(irq);
 240         int pIFR        = pIERbase + (irq_src << 4);
 241
 242         return psc_read_byte(pIFR) & (1 << irq_idx);
 243 }