]>
git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - arch/m68k/mm/cache.c
2 * linux/arch/m68k/mm/cache.c
4 * Instruction cache handling
6 * Copyright (C) 1995 Hamish Macdonald
9 #include <linux/module.h>
10 #include <asm/pgalloc.h>
11 #include <asm/traps.h>
14 static unsigned long virt_to_phys_slow(unsigned long vaddr
)
19 /* The PLPAR instruction causes an access error if the translation
20 * is not possible. To catch this we use the same exception mechanism
21 * as for user space accesses in <asm/uaccess.h>. */
22 asm volatile (".chip 68060\n"
26 ".section .fixup,\"ax\"\n"
31 ".section __ex_table,\"a\"\n"
38 } else if (CPU_IS_040
) {
41 asm volatile (".chip 68040\n\t"
43 "movec %%mmusr, %0\n\t"
48 if (mmusr
& MMU_R_040
)
49 return (mmusr
& PAGE_MASK
) | (vaddr
& ~PAGE_MASK
);
52 unsigned long *descaddr
;
54 asm volatile ("ptestr %3,%2@,#7,%0\n\t"
56 : "=a&" (descaddr
), "=m" (mmusr
)
57 : "a" (vaddr
), "d" (get_fs().seg
));
58 if (mmusr
& (MMU_I
|MMU_B
|MMU_L
))
60 descaddr
= phys_to_virt((unsigned long)descaddr
);
61 switch (mmusr
& MMU_NUM
) {
63 return (*descaddr
& 0xfe000000) | (vaddr
& 0x01ffffff);
65 return (*descaddr
& 0xfffc0000) | (vaddr
& 0x0003ffff);
67 return (*descaddr
& PAGE_MASK
) | (vaddr
& ~PAGE_MASK
);
73 /* Push n pages at kernel virtual address and clear the icache */
74 /* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
75 void flush_icache_range(unsigned long address
, unsigned long endaddr
)
77 if (CPU_IS_COLDFIRE
) {
78 unsigned long start
, end
;
79 start
= address
& ICACHE_SET_MASK
;
80 end
= endaddr
& ICACHE_SET_MASK
;
82 flush_cf_icache(0, end
);
83 end
= ICACHE_MAX_ADDR
;
85 flush_cf_icache(start
, end
);
86 } else if (CPU_IS_040_OR_060
) {
90 asm volatile ("nop\n\t"
92 "cpushp %%bc,(%0)\n\t"
94 : : "a" (virt_to_phys_slow(address
)));
96 } while (address
< endaddr
);
99 asm volatile ("movec %%cacr,%0\n\t"
106 EXPORT_SYMBOL(flush_icache_range
);
108 void flush_icache_user_range(struct vm_area_struct
*vma
, struct page
*page
,
109 unsigned long addr
, int len
)
111 if (CPU_IS_COLDFIRE
) {
112 unsigned long start
, end
;
113 start
= addr
& ICACHE_SET_MASK
;
114 end
= (addr
+ len
) & ICACHE_SET_MASK
;
116 flush_cf_icache(0, end
);
117 end
= ICACHE_MAX_ADDR
;
119 flush_cf_icache(start
, end
);
121 } else if (CPU_IS_040_OR_060
) {
122 asm volatile ("nop\n\t"
124 "cpushp %%bc,(%0)\n\t"
126 : : "a" (page_to_phys(page
)));
129 asm volatile ("movec %%cacr,%0\n\t"