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git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blob - arch/m68k/platform/coldfire/intc.c
2 * intc.c -- support for the old ColdFire interrupt controller
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
17 #include <asm/traps.h>
18 #include <asm/coldfire.h>
19 #include <asm/mcfsim.h>
22 * The mapping of irq number to a mask register bit is not one-to-one.
23 * The irq numbers are either based on "level" of interrupt or fixed
24 * for an autovector-able interrupt. So we keep a local data structure
25 * that maps from irq to mask register. Not all interrupts will have
28 unsigned char mcf_irq2imr
[NR_IRQS
];
31 * Define the miniumun and maximum external interrupt numbers.
32 * This is also used as the "level" interrupt numbers.
38 * In the early version 2 core ColdFire parts the IMR register was 16 bits
39 * in size. Version 3 (and later version 2) core parts have a 32 bit
40 * sized IMR register. Provide some size independent methods to access the
43 #ifdef MCFSIM_IMR_IS_16BITS
45 void mcf_setimr(int index
)
48 imr
= __raw_readw(MCF_MBAR
+ MCFSIM_IMR
);
49 __raw_writew(imr
| (0x1 << index
), MCF_MBAR
+ MCFSIM_IMR
);
52 void mcf_clrimr(int index
)
55 imr
= __raw_readw(MCF_MBAR
+ MCFSIM_IMR
);
56 __raw_writew(imr
& ~(0x1 << index
), MCF_MBAR
+ MCFSIM_IMR
);
59 void mcf_maskimr(unsigned int mask
)
62 imr
= __raw_readw(MCF_MBAR
+ MCFSIM_IMR
);
64 __raw_writew(imr
, MCF_MBAR
+ MCFSIM_IMR
);
69 void mcf_setimr(int index
)
72 imr
= __raw_readl(MCF_MBAR
+ MCFSIM_IMR
);
73 __raw_writel(imr
| (0x1 << index
), MCF_MBAR
+ MCFSIM_IMR
);
76 void mcf_clrimr(int index
)
79 imr
= __raw_readl(MCF_MBAR
+ MCFSIM_IMR
);
80 __raw_writel(imr
& ~(0x1 << index
), MCF_MBAR
+ MCFSIM_IMR
);
83 void mcf_maskimr(unsigned int mask
)
86 imr
= __raw_readl(MCF_MBAR
+ MCFSIM_IMR
);
88 __raw_writel(imr
, MCF_MBAR
+ MCFSIM_IMR
);
94 * Interrupts can be "vectored" on the ColdFire cores that support this old
95 * interrupt controller. That is, the device raising the interrupt can also
96 * supply the vector number to interrupt through. The AVR register of the
97 * interrupt controller enables or disables this for each external interrupt,
98 * so provide generic support for this. Setting this up is out-of-band for
99 * the interrupt system API's, and needs to be done by the driver that
100 * supports this device. Very few devices actually use this.
102 void mcf_autovector(int irq
)
105 if ((irq
>= EIRQ1
) && (irq
<= EIRQ7
)) {
107 avec
= __raw_readb(MCF_MBAR
+ MCFSIM_AVR
);
108 avec
|= (0x1 << (irq
- EIRQ1
+ 1));
109 __raw_writeb(avec
, MCF_MBAR
+ MCFSIM_AVR
);
114 static void intc_irq_mask(struct irq_data
*d
)
116 if (mcf_irq2imr
[d
->irq
])
117 mcf_setimr(mcf_irq2imr
[d
->irq
]);
120 static void intc_irq_unmask(struct irq_data
*d
)
122 if (mcf_irq2imr
[d
->irq
])
123 mcf_clrimr(mcf_irq2imr
[d
->irq
]);
126 static int intc_irq_set_type(struct irq_data
*d
, unsigned int type
)
131 static struct irq_chip intc_irq_chip
= {
133 .irq_mask
= intc_irq_mask
,
134 .irq_unmask
= intc_irq_unmask
,
135 .irq_set_type
= intc_irq_set_type
,
138 void __init
init_IRQ(void)
143 mcf_maskimr(0xffffffff);
145 for (irq
= 0; (irq
< NR_IRQS
); irq
++) {
146 irq_set_chip(irq
, &intc_irq_chip
);
147 irq_set_irq_type(irq
, IRQ_TYPE_LEVEL_HIGH
);
148 irq_set_handler(irq
, handle_level_irq
);