arch/metag/include/asm/barrier.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_METAG_BARRIER_H
   3 #define _ASM_METAG_BARRIER_H
   4
   5 #include <asm/metag_mem.h>
   6
   7 #define nop()           asm volatile ("NOP")
   8
   9 #ifdef CONFIG_METAG_META21
  10
  11 /* HTP and above have a system event to fence writes */
  12 static inline void wr_fence(void)
  13 {
  14         volatile int *flushptr = (volatile int *) LINSYSEVENT_WR_FENCE;
  15         barrier();
  16         *flushptr = 0;
  17         barrier();
  18 }
  19
  20 #else /* CONFIG_METAG_META21 */
  21
  22 /*
  23  * ATP doesn't have system event to fence writes, so it is necessary to flush
  24  * the processor write queues as well as possibly the write combiner (depending
  25  * on the page being written).
  26  * To ensure the write queues are flushed we do 4 writes to a system event
  27  * register (in this case write combiner flush) which will also flush the write
  28  * combiner.
  29  */
  30 static inline void wr_fence(void)
  31 {
  32         volatile int *flushptr = (volatile int *) LINSYSEVENT_WR_COMBINE_FLUSH;
  33         barrier();
  34         *flushptr = 0;
  35         *flushptr = 0;
  36         *flushptr = 0;
  37         *flushptr = 0;
  38         barrier();
  39 }
  40
  41 #endif /* !CONFIG_METAG_META21 */
  42
  43 /* flush writes through the write combiner */
  44 #define mb()            wr_fence()
  45 #define rmb()           barrier()
  46 #define wmb()           mb()
  47
  48 #ifdef CONFIG_METAG_SMP_WRITE_REORDERING
  49 /*
  50  * Write to the atomic memory unlock system event register (command 0). This is
  51  * needed before a write to shared memory in a critical section, to prevent
  52  * external reordering of writes before the fence on other threads with writes
  53  * after the fence on this thread (and to prevent the ensuing cache-memory
  54  * incoherence). It is therefore ineffective if used after and on the same
  55  * thread as a write.
  56  */
  57 static inline void metag_fence(void)
  58 {
  59         volatile int *flushptr = (volatile int *) LINSYSEVENT_WR_ATOMIC_UNLOCK;
  60         barrier();
  61         *flushptr = 0;
  62         barrier();
  63 }
  64 #define __smp_mb()      metag_fence()
  65 #define __smp_rmb()     metag_fence()
  66 #define __smp_wmb()     barrier()
  67 #else
  68 #define metag_fence()   do { } while (0)
  69 #define __smp_mb()      barrier()
  70 #define __smp_rmb()     barrier()
  71 #define __smp_wmb()     barrier()
  72 #endif
  73
  74 #ifdef CONFIG_SMP
  75 #define fence()         metag_fence()
  76 #else
  77 #define fence()         do { } while (0)
  78 #endif
  79
  80 #define __smp_mb__before_atomic()       barrier()
  81 #define __smp_mb__after_atomic()        barrier()
  82
  83 #include <asm-generic/barrier.h>
  84
  85 #endif /* _ASM_METAG_BARRIER_H */