arch/metag/kernel/cachepart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Meta cache partition manipulation.
   4  *
   5  * Copyright 2010 Imagination Technologies Ltd.
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/io.h>
  10 #include <linux/errno.h>
  11 #include <asm/processor.h>
  12 #include <asm/cachepart.h>
  13 #include <asm/metag_isa.h>
  14 #include <asm/metag_mem.h>
  15
  16 #define SYSC_DCPART(n)  (SYSC_DCPART0 + SYSC_xCPARTn_STRIDE * (n))
  17 #define SYSC_ICPART(n)  (SYSC_ICPART0 + SYSC_xCPARTn_STRIDE * (n))
  18
  19 #define CACHE_ASSOCIATIVITY 4 /* 4 way set-associative */
  20 #define ICACHE 0
  21 #define DCACHE 1
  22
  23 /* The CORE_CONFIG2 register is not available on Meta 1 */
  24 #ifdef CONFIG_METAG_META21
  25 unsigned int get_dcache_size(void)
  26 {
  27         unsigned int config2 = metag_in32(METAC_CORE_CONFIG2);
  28         unsigned int sz = 0x1000 << ((config2 & METAC_CORECFG2_DCSZ_BITS)
  29                                      >> METAC_CORECFG2_DCSZ_S);
  30         if (config2 & METAC_CORECFG2_DCSMALL_BIT)
  31                 sz >>= 6;
  32         return sz;
  33 }
  34
  35 unsigned int get_icache_size(void)
  36 {
  37         unsigned int config2 = metag_in32(METAC_CORE_CONFIG2);
  38         unsigned int sz = 0x1000 << ((config2 & METAC_CORE_C2ICSZ_BITS)
  39                                      >> METAC_CORE_C2ICSZ_S);
  40         if (config2 & METAC_CORECFG2_ICSMALL_BIT)
  41                 sz >>= 6;
  42         return sz;
  43 }
  44
  45 unsigned int get_global_dcache_size(void)
  46 {
  47         unsigned int cpart = metag_in32(SYSC_DCPART(hard_processor_id()));
  48         unsigned int temp = cpart & SYSC_xCPARTG_AND_BITS;
  49         return (get_dcache_size() * ((temp >> SYSC_xCPARTG_AND_S) + 1)) >> 4;
  50 }
  51
  52 unsigned int get_global_icache_size(void)
  53 {
  54         unsigned int cpart = metag_in32(SYSC_ICPART(hard_processor_id()));
  55         unsigned int temp = cpart & SYSC_xCPARTG_AND_BITS;
  56         return (get_icache_size() * ((temp >> SYSC_xCPARTG_AND_S) + 1)) >> 4;
  57 }
  58
  59 static int get_thread_cache_size(unsigned int cache, int thread_id)
  60 {
  61         unsigned int cache_size;
  62         unsigned int t_cache_part;
  63         unsigned int isEnabled;
  64         unsigned int offset = 0;
  65         isEnabled = (cache == DCACHE ? metag_in32(MMCU_DCACHE_CTRL_ADDR) & 0x1 :
  66                 metag_in32(MMCU_ICACHE_CTRL_ADDR) & 0x1);
  67         if (!isEnabled)
  68                 return 0;
  69 #if PAGE_OFFSET >= LINGLOBAL_BASE
  70         /* Checking for global cache */
  71         cache_size = (cache == DCACHE ? get_global_dcache_size() :
  72                 get_global_icache_size());
  73         offset = 8;
  74 #else
  75         cache_size = (cache == DCACHE ? get_dcache_size() :
  76                 get_icache_size());
  77 #endif
  78         t_cache_part = (cache == DCACHE ?
  79                 (metag_in32(SYSC_DCPART(thread_id)) >> offset) & 0xF :
  80                 (metag_in32(SYSC_ICPART(thread_id)) >> offset) & 0xF);
  81         switch (t_cache_part) {
  82         case 0xF:
  83                 return cache_size;
  84         case 0x7:
  85                 return cache_size / 2;
  86         case 0x3:
  87                 return cache_size / 4;
  88         case 0x1:
  89                 return cache_size / 8;
  90         case 0:
  91                 return cache_size / 16;
  92         }
  93         return -1;
  94 }
  95
  96 void check_for_cache_aliasing(int thread_id)
  97 {
  98         int thread_cache_size;
  99         unsigned int cache_type;
 100         for (cache_type = ICACHE; cache_type <= DCACHE; cache_type++) {
 101                 thread_cache_size =
 102                                 get_thread_cache_size(cache_type, thread_id);
 103                 if (thread_cache_size < 0)
 104                         pr_emerg("Can't read %s cache size\n",
 105                                  cache_type ? "DCACHE" : "ICACHE");
 106                 else if (thread_cache_size == 0)
 107                         /* Cache is off. No need to check for aliasing */
 108                         continue;
 109                 if (thread_cache_size / CACHE_ASSOCIATIVITY > PAGE_SIZE) {
 110                         pr_emerg("Potential cache aliasing detected in %s on Thread %d\n",
 111                                  cache_type ? "DCACHE" : "ICACHE", thread_id);
 112                         pr_warn("Total %s size: %u bytes\n",
 113                                 cache_type ? "DCACHE" : "ICACHE",
 114                                 cache_type ? get_dcache_size()
 115                                 : get_icache_size());
 116                         pr_warn("Thread %s size: %d bytes\n",
 117                                 cache_type ? "CACHE" : "ICACHE",
 118                                 thread_cache_size);
 119                         pr_warn("Page Size: %lu bytes\n", PAGE_SIZE);
 120                         panic("Potential cache aliasing detected");
 121                 }
 122         }
 123 }
 124
 125 #else
 126
 127 void check_for_cache_aliasing(int thread_id)
 128 {
 129         return;
 130 }
 131
 132 #endif