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microblaze: drop _PAGE_FILE and pte_file()-related helpers
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1 /*
2 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2008-2009 PetaLogix
4 * Copyright (C) 2006 Atmark Techno, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11 #ifndef _ASM_MICROBLAZE_PGTABLE_H
12 #define _ASM_MICROBLAZE_PGTABLE_H
13
14 #include <asm/setup.h>
15
16 #ifndef __ASSEMBLY__
17 extern int mem_init_done;
18 #endif
19
20 #ifndef CONFIG_MMU
21
22 #define pgd_present(pgd) (1) /* pages are always present on non MMU */
23 #define pgd_none(pgd) (0)
24 #define pgd_bad(pgd) (0)
25 #define pgd_clear(pgdp)
26 #define kern_addr_valid(addr) (1)
27 #define pmd_offset(a, b) ((void *) 0)
28
29 #define PAGE_NONE __pgprot(0) /* these mean nothing to non MMU */
30 #define PAGE_SHARED __pgprot(0) /* these mean nothing to non MMU */
31 #define PAGE_COPY __pgprot(0) /* these mean nothing to non MMU */
32 #define PAGE_READONLY __pgprot(0) /* these mean nothing to non MMU */
33 #define PAGE_KERNEL __pgprot(0) /* these mean nothing to non MMU */
34
35 #define pgprot_noncached(x) (x)
36
37 #define __swp_type(x) (0)
38 #define __swp_offset(x) (0)
39 #define __swp_entry(typ, off) ((swp_entry_t) { ((typ) | ((off) << 7)) })
40 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
41 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
42
43 #define ZERO_PAGE(vaddr) ({ BUG(); NULL; })
44
45 #define swapper_pg_dir ((pgd_t *) NULL)
46
47 #define pgtable_cache_init() do {} while (0)
48
49 #define arch_enter_lazy_cpu_mode() do {} while (0)
50
51 #define pgprot_noncached_wc(prot) prot
52
53 /*
54 * All 32bit addresses are effectively valid for vmalloc...
55 * Sort of meaningless for non-VM targets.
56 */
57 #define VMALLOC_START 0
58 #define VMALLOC_END 0xffffffff
59
60 #else /* CONFIG_MMU */
61
62 #include <asm-generic/4level-fixup.h>
63
64 #ifdef __KERNEL__
65 #ifndef __ASSEMBLY__
66
67 #include <linux/sched.h>
68 #include <linux/threads.h>
69 #include <asm/processor.h> /* For TASK_SIZE */
70 #include <asm/mmu.h>
71 #include <asm/page.h>
72
73 #define FIRST_USER_ADDRESS 0
74
75 extern unsigned long va_to_phys(unsigned long address);
76 extern pte_t *va_to_pte(unsigned long address);
77
78 /*
79 * The following only work if pte_present() is true.
80 * Undefined behaviour if not..
81 */
82
83 static inline int pte_special(pte_t pte) { return 0; }
84
85 static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
86
87 /* Start and end of the vmalloc area. */
88 /* Make sure to map the vmalloc area above the pinned kernel memory area
89 of 32Mb. */
90 #define VMALLOC_START (CONFIG_KERNEL_START + CONFIG_LOWMEM_SIZE)
91 #define VMALLOC_END ioremap_bot
92
93 #endif /* __ASSEMBLY__ */
94
95 /*
96 * Macro to mark a page protection value as "uncacheable".
97 */
98
99 #define _PAGE_CACHE_CTL (_PAGE_GUARDED | _PAGE_NO_CACHE | \
100 _PAGE_WRITETHRU)
101
102 #define pgprot_noncached(prot) \
103 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
104 _PAGE_NO_CACHE | _PAGE_GUARDED))
105
106 #define pgprot_noncached_wc(prot) \
107 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
108 _PAGE_NO_CACHE))
109
110 /*
111 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash
112 * table containing PTEs, together with a set of 16 segment registers, to
113 * define the virtual to physical address mapping.
114 *
115 * We use the hash table as an extended TLB, i.e. a cache of currently
116 * active mappings. We maintain a two-level page table tree, much
117 * like that used by the i386, for the sake of the Linux memory
118 * management code. Low-level assembler code in hashtable.S
119 * (procedure hash_page) is responsible for extracting ptes from the
120 * tree and putting them into the hash table when necessary, and
121 * updating the accessed and modified bits in the page table tree.
122 */
123
124 /*
125 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
126 * instruction and data sides share a unified, 64-entry, semi-associative
127 * TLB which is maintained totally under software control. In addition, the
128 * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative
129 * TLB which serves as a first level to the shared TLB. These two TLBs are
130 * known as the UTLB and ITLB, respectively (see "mmu.h" for definitions).
131 */
132
133 /*
134 * The normal case is that PTEs are 32-bits and we have a 1-page
135 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
136 *
137 */
138
139 /* PMD_SHIFT determines the size of the area mapped by the PTE pages */
140 #define PMD_SHIFT (PAGE_SHIFT + PTE_SHIFT)
141 #define PMD_SIZE (1UL << PMD_SHIFT)
142 #define PMD_MASK (~(PMD_SIZE-1))
143
144 /* PGDIR_SHIFT determines what a top-level page table entry can map */
145 #define PGDIR_SHIFT PMD_SHIFT
146 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
147 #define PGDIR_MASK (~(PGDIR_SIZE-1))
148
149 /*
150 * entries per page directory level: our page-table tree is two-level, so
151 * we don't really have any PMD directory.
152 */
153 #define PTRS_PER_PTE (1 << PTE_SHIFT)
154 #define PTRS_PER_PMD 1
155 #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
156
157 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
158 #define FIRST_USER_PGD_NR 0
159
160 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
161 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
162
163 #define pte_ERROR(e) \
164 printk(KERN_ERR "%s:%d: bad pte "PTE_FMT".\n", \
165 __FILE__, __LINE__, pte_val(e))
166 #define pmd_ERROR(e) \
167 printk(KERN_ERR "%s:%d: bad pmd %08lx.\n", \
168 __FILE__, __LINE__, pmd_val(e))
169 #define pgd_ERROR(e) \
170 printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \
171 __FILE__, __LINE__, pgd_val(e))
172
173 /*
174 * Bits in a linux-style PTE. These match the bits in the
175 * (hardware-defined) PTE as closely as possible.
176 */
177
178 /* There are several potential gotchas here. The hardware TLBLO
179 * field looks like this:
180 *
181 * 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
182 * RPN..................... 0 0 EX WR ZSEL....... W I M G
183 *
184 * Where possible we make the Linux PTE bits match up with this
185 *
186 * - bits 20 and 21 must be cleared, because we use 4k pages (4xx can
187 * support down to 1k pages), this is done in the TLBMiss exception
188 * handler.
189 * - We use only zones 0 (for kernel pages) and 1 (for user pages)
190 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
191 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
192 * zone.
193 * - PRESENT *must* be in the bottom two bits because swap cache
194 * entries use the top 30 bits. Because 4xx doesn't support SMP
195 * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
196 * is cleared in the TLB miss handler before the TLB entry is loaded.
197 * - All other bits of the PTE are loaded into TLBLO without
198 * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
199 * software PTE bits. We actually use use bits 21, 24, 25, and
200 * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
201 * PRESENT.
202 */
203
204 /* Definitions for MicroBlaze. */
205 #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
206 #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
207 #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
208 #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
209 #define _PAGE_USER 0x010 /* matches one of the zone permission bits */
210 #define _PAGE_RW 0x040 /* software: Writes permitted */
211 #define _PAGE_DIRTY 0x080 /* software: dirty page */
212 #define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
213 #define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
214 #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
215 #define _PMD_PRESENT PAGE_MASK
216
217 /*
218 * Some bits are unused...
219 */
220 #ifndef _PAGE_HASHPTE
221 #define _PAGE_HASHPTE 0
222 #endif
223 #ifndef _PTE_NONE_MASK
224 #define _PTE_NONE_MASK 0
225 #endif
226 #ifndef _PAGE_SHARED
227 #define _PAGE_SHARED 0
228 #endif
229 #ifndef _PAGE_EXEC
230 #define _PAGE_EXEC 0
231 #endif
232
233 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
234
235 /*
236 * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
237 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
238 * to have it in the Linux PTE, and in fact the bit could be reused for
239 * another purpose. -- paulus.
240 */
241 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
242 #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
243
244 #define _PAGE_KERNEL \
245 (_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | _PAGE_HWEXEC)
246
247 #define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
248
249 #define PAGE_NONE __pgprot(_PAGE_BASE)
250 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
251 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
252 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
253 #define PAGE_SHARED_X \
254 __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
255 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
256 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
257
258 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
259 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_SHARED)
260 #define PAGE_KERNEL_CI __pgprot(_PAGE_IO)
261
262 /*
263 * We consider execute permission the same as read.
264 * Also, write permissions imply read permissions.
265 */
266 #define __P000 PAGE_NONE
267 #define __P001 PAGE_READONLY_X
268 #define __P010 PAGE_COPY
269 #define __P011 PAGE_COPY_X
270 #define __P100 PAGE_READONLY
271 #define __P101 PAGE_READONLY_X
272 #define __P110 PAGE_COPY
273 #define __P111 PAGE_COPY_X
274
275 #define __S000 PAGE_NONE
276 #define __S001 PAGE_READONLY_X
277 #define __S010 PAGE_SHARED
278 #define __S011 PAGE_SHARED_X
279 #define __S100 PAGE_READONLY
280 #define __S101 PAGE_READONLY_X
281 #define __S110 PAGE_SHARED
282 #define __S111 PAGE_SHARED_X
283
284 #ifndef __ASSEMBLY__
285 /*
286 * ZERO_PAGE is a global shared page that is always zero: used
287 * for zero-mapped memory areas etc..
288 */
289 extern unsigned long empty_zero_page[1024];
290 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
291
292 #endif /* __ASSEMBLY__ */
293
294 #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
295 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
296 #define pte_clear(mm, addr, ptep) \
297 do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
298
299 #define pmd_none(pmd) (!pmd_val(pmd))
300 #define pmd_bad(pmd) ((pmd_val(pmd) & _PMD_PRESENT) == 0)
301 #define pmd_present(pmd) ((pmd_val(pmd) & _PMD_PRESENT) != 0)
302 #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
303
304 #define pte_page(x) (mem_map + (unsigned long) \
305 ((pte_val(x) - memory_start) >> PAGE_SHIFT))
306 #define PFN_SHIFT_OFFSET (PAGE_SHIFT)
307
308 #define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET)
309
310 #define pfn_pte(pfn, prot) \
311 __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) | pgprot_val(prot))
312
313 #ifndef __ASSEMBLY__
314 /*
315 * The "pgd_xxx()" functions here are trivial for a folded two-level
316 * setup: the pgd is never bad, and a pmd always exists (as it's folded
317 * into the pgd entry)
318 */
319 static inline int pgd_none(pgd_t pgd) { return 0; }
320 static inline int pgd_bad(pgd_t pgd) { return 0; }
321 static inline int pgd_present(pgd_t pgd) { return 1; }
322 #define pgd_clear(xp) do { } while (0)
323 #define pgd_page(pgd) \
324 ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
325
326 /*
327 * The following only work if pte_present() is true.
328 * Undefined behaviour if not..
329 */
330 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
331 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
332 static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
333 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
334 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
335
336 static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
337 static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
338
339 static inline pte_t pte_rdprotect(pte_t pte) \
340 { pte_val(pte) &= ~_PAGE_USER; return pte; }
341 static inline pte_t pte_wrprotect(pte_t pte) \
342 { pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
343 static inline pte_t pte_exprotect(pte_t pte) \
344 { pte_val(pte) &= ~_PAGE_EXEC; return pte; }
345 static inline pte_t pte_mkclean(pte_t pte) \
346 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
347 static inline pte_t pte_mkold(pte_t pte) \
348 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
349
350 static inline pte_t pte_mkread(pte_t pte) \
351 { pte_val(pte) |= _PAGE_USER; return pte; }
352 static inline pte_t pte_mkexec(pte_t pte) \
353 { pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
354 static inline pte_t pte_mkwrite(pte_t pte) \
355 { pte_val(pte) |= _PAGE_RW; return pte; }
356 static inline pte_t pte_mkdirty(pte_t pte) \
357 { pte_val(pte) |= _PAGE_DIRTY; return pte; }
358 static inline pte_t pte_mkyoung(pte_t pte) \
359 { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
360
361 /*
362 * Conversion functions: convert a page and protection to a page entry,
363 * and a page entry and page directory to the page they refer to.
364 */
365
366 static inline pte_t mk_pte_phys(phys_addr_t physpage, pgprot_t pgprot)
367 {
368 pte_t pte;
369 pte_val(pte) = physpage | pgprot_val(pgprot);
370 return pte;
371 }
372
373 #define mk_pte(page, pgprot) \
374 ({ \
375 pte_t pte; \
376 pte_val(pte) = (((page - mem_map) << PAGE_SHIFT) + memory_start) | \
377 pgprot_val(pgprot); \
378 pte; \
379 })
380
381 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
382 {
383 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
384 return pte;
385 }
386
387 /*
388 * Atomic PTE updates.
389 *
390 * pte_update clears and sets bit atomically, and returns
391 * the old pte value.
392 * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant
393 * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits.
394 */
395 static inline unsigned long pte_update(pte_t *p, unsigned long clr,
396 unsigned long set)
397 {
398 unsigned long flags, old, tmp;
399
400 raw_local_irq_save(flags);
401
402 __asm__ __volatile__( "lw %0, %2, r0 \n"
403 "andn %1, %0, %3 \n"
404 "or %1, %1, %4 \n"
405 "sw %1, %2, r0 \n"
406 : "=&r" (old), "=&r" (tmp)
407 : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set)
408 : "cc");
409
410 raw_local_irq_restore(flags);
411
412 return old;
413 }
414
415 /*
416 * set_pte stores a linux PTE into the linux page table.
417 */
418 static inline void set_pte(struct mm_struct *mm, unsigned long addr,
419 pte_t *ptep, pte_t pte)
420 {
421 *ptep = pte;
422 }
423
424 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
425 pte_t *ptep, pte_t pte)
426 {
427 *ptep = pte;
428 }
429
430 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
431 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
432 unsigned long address, pte_t *ptep)
433 {
434 return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0;
435 }
436
437 static inline int ptep_test_and_clear_dirty(struct mm_struct *mm,
438 unsigned long addr, pte_t *ptep)
439 {
440 return (pte_update(ptep, \
441 (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
442 }
443
444 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
445 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
446 unsigned long addr, pte_t *ptep)
447 {
448 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
449 }
450
451 /*static inline void ptep_set_wrprotect(struct mm_struct *mm,
452 unsigned long addr, pte_t *ptep)
453 {
454 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
455 }*/
456
457 static inline void ptep_mkdirty(struct mm_struct *mm,
458 unsigned long addr, pte_t *ptep)
459 {
460 pte_update(ptep, 0, _PAGE_DIRTY);
461 }
462
463 /*#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)*/
464
465 /* Convert pmd entry to page */
466 /* our pmd entry is an effective address of pte table*/
467 /* returns effective address of the pmd entry*/
468 #define pmd_page_kernel(pmd) ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
469
470 /* returns struct *page of the pmd entry*/
471 #define pmd_page(pmd) (pfn_to_page(__pa(pmd_val(pmd)) >> PAGE_SHIFT))
472
473 /* to find an entry in a kernel page-table-directory */
474 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
475
476 /* to find an entry in a page-table-directory */
477 #define pgd_index(address) ((address) >> PGDIR_SHIFT)
478 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
479
480 /* Find an entry in the second-level page table.. */
481 static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
482 {
483 return (pmd_t *) dir;
484 }
485
486 /* Find an entry in the third-level page table.. */
487 #define pte_index(address) \
488 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
489 #define pte_offset_kernel(dir, addr) \
490 ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr))
491 #define pte_offset_map(dir, addr) \
492 ((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr))
493
494 #define pte_unmap(pte) kunmap_atomic(pte)
495
496 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
497
498 /*
499 * Encode and decode a swap entry.
500 * Note that the bits we use in a PTE for representing a swap entry
501 * must not include the _PAGE_PRESENT bit, or the _PAGE_HASHPTE bit
502 * (if used). -- paulus
503 */
504 #define __swp_type(entry) ((entry).val & 0x3f)
505 #define __swp_offset(entry) ((entry).val >> 6)
506 #define __swp_entry(type, offset) \
507 ((swp_entry_t) { (type) | ((offset) << 6) })
508 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 2 })
509 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 2 })
510
511 extern unsigned long iopa(unsigned long addr);
512
513 /* Values for nocacheflag and cmode */
514 /* These are not used by the APUS kernel_map, but prevents
515 * compilation errors.
516 */
517 #define IOMAP_FULL_CACHING 0
518 #define IOMAP_NOCACHE_SER 1
519 #define IOMAP_NOCACHE_NONSER 2
520 #define IOMAP_NO_COPYBACK 3
521
522 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
523 #define kern_addr_valid(addr) (1)
524
525 /*
526 * No page table caches to initialise
527 */
528 #define pgtable_cache_init() do { } while (0)
529
530 void do_page_fault(struct pt_regs *regs, unsigned long address,
531 unsigned long error_code);
532
533 void mapin_ram(void);
534 int map_page(unsigned long va, phys_addr_t pa, int flags);
535
536 extern int mem_init_done;
537
538 asmlinkage void __init mmu_init(void);
539
540 void __init *early_get_page(void);
541
542 #endif /* __ASSEMBLY__ */
543 #endif /* __KERNEL__ */
544
545 #endif /* CONFIG_MMU */
546
547 #ifndef __ASSEMBLY__
548 #include <asm-generic/pgtable.h>
549
550 extern unsigned long ioremap_bot, ioremap_base;
551
552 void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle);
553 void consistent_free(size_t size, void *vaddr);
554 void consistent_sync(void *vaddr, size_t size, int direction);
555 void consistent_sync_page(struct page *page, unsigned long offset,
556 size_t size, int direction);
557 unsigned long consistent_virt_to_pfn(void *vaddr);
558
559 void setup_memory(void);
560 #endif /* __ASSEMBLY__ */
561
562 #endif /* _ASM_MICROBLAZE_PGTABLE_H */