arch/microblaze/kernel/intc.c

   1 /*
   2  * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
   3  * Copyright (C) 2007-2009 PetaLogix
   4  * Copyright (C) 2006 Atmark Techno, Inc.
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License. See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/irqdomain.h>
  13 #include <linux/irq.h>
  14 #include <asm/page.h>
  15 #include <linux/io.h>
  16 #include <linux/bug.h>
  17
  18 #include <asm/prom.h>
  19 #include <asm/irq.h>
  20
  21 #ifdef CONFIG_SELFMOD_INTC
  22 #include <asm/selfmod.h>
  23 #define INTC_BASE       BARRIER_BASE_ADDR
  24 #else
  25 static unsigned int intc_baseaddr;
  26 #define INTC_BASE       intc_baseaddr
  27 #endif
  28
  29 /* No one else should require these constants, so define them locally here. */
  30 #define ISR 0x00                        /* Interrupt Status Register */
  31 #define IPR 0x04                        /* Interrupt Pending Register */
  32 #define IER 0x08                        /* Interrupt Enable Register */
  33 #define IAR 0x0c                        /* Interrupt Acknowledge Register */
  34 #define SIE 0x10                        /* Set Interrupt Enable bits */
  35 #define CIE 0x14                        /* Clear Interrupt Enable bits */
  36 #define IVR 0x18                        /* Interrupt Vector Register */
  37 #define MER 0x1c                        /* Master Enable Register */
  38
  39 #define MER_ME (1<<0)
  40 #define MER_HIE (1<<1)
  41
  42 static void intc_enable_or_unmask(struct irq_data *d)
  43 {
  44         unsigned long mask = 1 << d->hwirq;
  45
  46         pr_debug("enable_or_unmask: %ld\n", d->hwirq);
  47         out_be32(INTC_BASE + SIE, mask);
  48
  49         /* ack level irqs because they can't be acked during
  50          * ack function since the handle_level_irq function
  51          * acks the irq before calling the interrupt handler
  52          */
  53         if (irqd_is_level_type(d))
  54                 out_be32(INTC_BASE + IAR, mask);
  55 }
  56
  57 static void intc_disable_or_mask(struct irq_data *d)
  58 {
  59         pr_debug("disable: %ld\n", d->hwirq);
  60         out_be32(INTC_BASE + CIE, 1 << d->hwirq);
  61 }
  62
  63 static void intc_ack(struct irq_data *d)
  64 {
  65         pr_debug("ack: %ld\n", d->hwirq);
  66         out_be32(INTC_BASE + IAR, 1 << d->hwirq);
  67 }
  68
  69 static void intc_mask_ack(struct irq_data *d)
  70 {
  71         unsigned long mask = 1 << d->hwirq;
  72
  73         pr_debug("disable_and_ack: %ld\n", d->hwirq);
  74         out_be32(INTC_BASE + CIE, mask);
  75         out_be32(INTC_BASE + IAR, mask);
  76 }
  77
  78 static struct irq_chip intc_dev = {
  79         .name = "Xilinx INTC",
  80         .irq_unmask = intc_enable_or_unmask,
  81         .irq_mask = intc_disable_or_mask,
  82         .irq_ack = intc_ack,
  83         .irq_mask_ack = intc_mask_ack,
  84 };
  85
  86 static struct irq_domain *root_domain;
  87
  88 unsigned int get_irq(void)
  89 {
  90         unsigned int hwirq, irq = -1;
  91
  92         hwirq = in_be32(INTC_BASE + IVR);
  93         if (hwirq != -1U)
  94                 irq = irq_find_mapping(root_domain, hwirq);
  95
  96         pr_debug("get_irq: hwirq=%d, irq=%d\n", hwirq, irq);
  97
  98         return irq;
  99 }
 100
 101 int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 102 {
 103         u32 intr_mask = (u32)d->host_data;
 104
 105         if (intr_mask & (1 << hw)) {
 106                 irq_set_chip_and_handler_name(irq, &intc_dev,
 107                                                 handle_edge_irq, "edge");
 108                 irq_clear_status_flags(irq, IRQ_LEVEL);
 109         } else {
 110                 irq_set_chip_and_handler_name(irq, &intc_dev,
 111                                                 handle_level_irq, "level");
 112                 irq_set_status_flags(irq, IRQ_LEVEL);
 113         }
 114         return 0;
 115 }
 116
 117 static const struct irq_domain_ops xintc_irq_domain_ops = {
 118         .xlate = irq_domain_xlate_onetwocell,
 119         .map = xintc_map,
 120 };
 121
 122 void __init init_IRQ(void)
 123 {
 124         u32 nr_irq, intr_mask;
 125         struct device_node *intc = NULL;
 126 #ifdef CONFIG_SELFMOD_INTC
 127         unsigned int intc_baseaddr = 0;
 128         static int arr_func[] = {
 129                                 (int)&get_irq,
 130                                 (int)&intc_enable_or_unmask,
 131                                 (int)&intc_disable_or_mask,
 132                                 (int)&intc_mask_ack,
 133                                 (int)&intc_ack,
 134                                 (int)&intc_end,
 135                                 0
 136                         };
 137 #endif
 138         intc = of_find_compatible_node(NULL, NULL, "xlnx,xps-intc-1.00.a");
 139         BUG_ON(!intc);
 140
 141         intc_baseaddr = be32_to_cpup(of_get_property(intc, "reg", NULL));
 142         intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE);
 143         nr_irq = be32_to_cpup(of_get_property(intc,
 144                                                 "xlnx,num-intr-inputs", NULL));
 145
 146         intr_mask =
 147                 be32_to_cpup(of_get_property(intc, "xlnx,kind-of-intr", NULL));
 148         if (intr_mask > (u32)((1ULL << nr_irq) - 1))
 149                 printk(KERN_INFO " ERROR: Mismatch in kind-of-intr param\n");
 150
 151 #ifdef CONFIG_SELFMOD_INTC
 152         selfmod_function((int *) arr_func, intc_baseaddr);
 153 #endif
 154         printk(KERN_INFO "%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
 155                 intc->name, intc_baseaddr, nr_irq, intr_mask);
 156
 157         /*
 158          * Disable all external interrupts until they are
 159          * explicity requested.
 160          */
 161         out_be32(intc_baseaddr + IER, 0);
 162
 163         /* Acknowledge any pending interrupts just in case. */
 164         out_be32(intc_baseaddr + IAR, 0xffffffff);
 165
 166         /* Turn on the Master Enable. */
 167         out_be32(intc_baseaddr + MER, MER_HIE | MER_ME);
 168
 169         /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
 170          * lazy and Michal can clean it up to something nicer when he tests
 171          * and commits this patch.  ~~gcl */
 172         root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops,
 173                                                         (void *)intr_mask);
 174 }