2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_pci.h>
34 #include <linux/export.h>
36 #include <asm/processor.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/byteorder.h>
41 static DEFINE_SPINLOCK(hose_spinlock
);
44 /* XXX kill that some day ... */
45 static int global_phb_number
; /* Global phb counter */
47 /* ISA Memory physical address */
48 resource_size_t isa_mem_base
;
50 unsigned long isa_io_base
;
51 static int pci_bus_count
;
53 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
55 struct pci_controller
*phb
;
57 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
60 spin_lock(&hose_spinlock
);
61 phb
->global_number
= global_phb_number
++;
62 list_add_tail(&phb
->list_node
, &hose_list
);
63 spin_unlock(&hose_spinlock
);
65 phb
->is_dynamic
= mem_init_done
;
69 void pcibios_free_controller(struct pci_controller
*phb
)
71 spin_lock(&hose_spinlock
);
72 list_del(&phb
->list_node
);
73 spin_unlock(&hose_spinlock
);
79 static resource_size_t
pcibios_io_size(const struct pci_controller
*hose
)
81 return resource_size(&hose
->io_resource
);
84 int pcibios_vaddr_is_ioport(void __iomem
*address
)
87 struct pci_controller
*hose
;
90 spin_lock(&hose_spinlock
);
91 list_for_each_entry(hose
, &hose_list
, list_node
) {
92 size
= pcibios_io_size(hose
);
93 if (address
>= hose
->io_base_virt
&&
94 address
< (hose
->io_base_virt
+ size
)) {
99 spin_unlock(&hose_spinlock
);
103 unsigned long pci_address_to_pio(phys_addr_t address
)
105 struct pci_controller
*hose
;
106 resource_size_t size
;
107 unsigned long ret
= ~0;
109 spin_lock(&hose_spinlock
);
110 list_for_each_entry(hose
, &hose_list
, list_node
) {
111 size
= pcibios_io_size(hose
);
112 if (address
>= hose
->io_base_phys
&&
113 address
< (hose
->io_base_phys
+ size
)) {
115 (unsigned long)hose
->io_base_virt
- _IO_BASE
;
116 ret
= base
+ (address
- hose
->io_base_phys
);
120 spin_unlock(&hose_spinlock
);
124 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
127 * Return the domain number for this bus.
129 int pci_domain_nr(struct pci_bus
*bus
)
131 struct pci_controller
*hose
= pci_bus_to_host(bus
);
133 return hose
->global_number
;
135 EXPORT_SYMBOL(pci_domain_nr
);
137 /* This routine is meant to be used early during boot, when the
138 * PCI bus numbers have not yet been assigned, and you need to
139 * issue PCI config cycles to an OF device.
140 * It could also be used to "fix" RTAS config cycles if you want
141 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
144 struct pci_controller
*pci_find_hose_for_OF_device(struct device_node
*node
)
147 struct pci_controller
*hose
, *tmp
;
148 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
149 if (hose
->dn
== node
)
156 void pcibios_set_master(struct pci_dev
*dev
)
158 /* No special bus mastering setup handling */
162 * Platform support for /proc/bus/pci/X/Y mmap()s,
163 * modelled on the sparc64 implementation by Dave Miller.
168 * Adjust vm_pgoff of VMA such that it is the physical page offset
169 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
171 * Basically, the user finds the base address for his device which he wishes
172 * to mmap. They read the 32-bit value from the config space base register,
173 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
174 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
176 * Returns negative error code on failure, zero on success.
178 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
179 resource_size_t
*offset
,
180 enum pci_mmap_state mmap_state
)
182 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
183 unsigned long io_offset
= 0;
187 return NULL
; /* should never happen */
189 /* If memory, add on the PCI bridge address offset */
190 if (mmap_state
== pci_mmap_mem
) {
191 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
192 *offset
+= hose
->pci_mem_offset
;
194 res_bit
= IORESOURCE_MEM
;
196 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
197 *offset
+= io_offset
;
198 res_bit
= IORESOURCE_IO
;
202 * Check that the offset requested corresponds to one of the
203 * resources of the device.
205 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
206 struct resource
*rp
= &dev
->resource
[i
];
207 int flags
= rp
->flags
;
209 /* treat ROM as memory (should be already) */
210 if (i
== PCI_ROM_RESOURCE
)
211 flags
|= IORESOURCE_MEM
;
213 /* Active and same type? */
214 if ((flags
& res_bit
) == 0)
217 /* In the range of this resource? */
218 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
221 /* found it! construct the final physical address */
222 if (mmap_state
== pci_mmap_io
)
223 *offset
+= hose
->io_base_phys
- io_offset
;
231 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
234 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
236 enum pci_mmap_state mmap_state
,
239 pgprot_t prot
= protection
;
241 /* Write combine is always 0 on non-memory space mappings. On
242 * memory space, if the user didn't pass 1, we check for a
243 * "prefetchable" resource. This is a bit hackish, but we use
244 * this to workaround the inability of /sysfs to provide a write
247 if (mmap_state
!= pci_mmap_mem
)
249 else if (write_combine
== 0) {
250 if (rp
->flags
& IORESOURCE_PREFETCH
)
254 return pgprot_noncached(prot
);
258 * This one is used by /dev/mem and fbdev who have no clue about the
259 * PCI device, it tries to find the PCI device first and calls the
262 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
267 struct pci_dev
*pdev
= NULL
;
268 struct resource
*found
= NULL
;
269 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
272 if (page_is_ram(pfn
))
275 prot
= pgprot_noncached(prot
);
276 for_each_pci_dev(pdev
) {
277 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
278 struct resource
*rp
= &pdev
->resource
[i
];
279 int flags
= rp
->flags
;
281 /* Active and same type? */
282 if ((flags
& IORESOURCE_MEM
) == 0)
284 /* In the range of this resource? */
285 if (offset
< (rp
->start
& PAGE_MASK
) ||
295 if (found
->flags
& IORESOURCE_PREFETCH
)
296 prot
= pgprot_noncached_wc(prot
);
300 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
301 (unsigned long long)offset
, pgprot_val(prot
));
307 * Perform the actual remap of the pages for a PCI device mapping, as
308 * appropriate for this architecture. The region in the process to map
309 * is described by vm_start and vm_end members of VMA, the base physical
310 * address is found in vm_pgoff.
311 * The pci device structure is provided so that architectures may make mapping
312 * decisions on a per-device or per-bus basis.
314 * Returns a negative error code on failure, zero on success.
316 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
317 enum pci_mmap_state mmap_state
, int write_combine
)
319 resource_size_t offset
=
320 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
324 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
328 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
329 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
331 mmap_state
, write_combine
);
333 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
334 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
339 /* This provides legacy IO read access on a bus */
340 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
342 unsigned long offset
;
343 struct pci_controller
*hose
= pci_bus_to_host(bus
);
344 struct resource
*rp
= &hose
->io_resource
;
347 /* Check if port can be supported by that bus. We only check
348 * the ranges of the PHB though, not the bus itself as the rules
349 * for forwarding legacy cycles down bridges are not our problem
350 * here. So if the host bridge supports it, we do it.
352 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
355 if (!(rp
->flags
& IORESOURCE_IO
))
357 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
359 addr
= hose
->io_base_virt
+ port
;
363 *((u8
*)val
) = in_8(addr
);
368 *((u16
*)val
) = in_le16(addr
);
373 *((u32
*)val
) = in_le32(addr
);
379 /* This provides legacy IO write access on a bus */
380 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
382 unsigned long offset
;
383 struct pci_controller
*hose
= pci_bus_to_host(bus
);
384 struct resource
*rp
= &hose
->io_resource
;
387 /* Check if port can be supported by that bus. We only check
388 * the ranges of the PHB though, not the bus itself as the rules
389 * for forwarding legacy cycles down bridges are not our problem
390 * here. So if the host bridge supports it, we do it.
392 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
395 if (!(rp
->flags
& IORESOURCE_IO
))
397 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
399 addr
= hose
->io_base_virt
+ port
;
401 /* WARNING: The generic code is idiotic. It gets passed a pointer
402 * to what can be a 1, 2 or 4 byte quantity and always reads that
403 * as a u32, which means that we have to correct the location of
404 * the data read within those 32 bits for size 1 and 2
408 out_8(addr
, val
>> 24);
413 out_le16(addr
, val
>> 16);
424 /* This provides legacy IO or memory mmap access on a bus */
425 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
426 struct vm_area_struct
*vma
,
427 enum pci_mmap_state mmap_state
)
429 struct pci_controller
*hose
= pci_bus_to_host(bus
);
430 resource_size_t offset
=
431 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
432 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
435 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
436 pci_domain_nr(bus
), bus
->number
,
437 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
438 (unsigned long long)offset
,
439 (unsigned long long)(offset
+ size
- 1));
441 if (mmap_state
== pci_mmap_mem
) {
444 * Because X is lame and can fail starting if it gets an error
445 * trying to mmap legacy_mem (instead of just moving on without
446 * legacy memory access) we fake it here by giving it anonymous
447 * memory, effectively behaving just like /dev/zero
449 if ((offset
+ size
) > hose
->isa_mem_size
) {
451 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
452 current
->comm
, current
->pid
);
453 pr_debug("legacy memory for 0%04x:%02x\n",
454 pci_domain_nr(bus
), bus
->number
);
456 if (vma
->vm_flags
& VM_SHARED
)
457 return shmem_zero_setup(vma
);
460 offset
+= hose
->isa_mem_phys
;
462 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
-
464 unsigned long roffset
= offset
+ io_offset
;
465 rp
= &hose
->io_resource
;
466 if (!(rp
->flags
& IORESOURCE_IO
))
468 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
470 offset
+= hose
->io_base_phys
;
472 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
474 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
475 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
476 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
477 vma
->vm_end
- vma
->vm_start
,
481 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
482 const struct resource
*rsrc
,
483 resource_size_t
*start
, resource_size_t
*end
)
485 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
486 resource_size_t offset
= 0;
491 if (rsrc
->flags
& IORESOURCE_IO
)
492 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
494 /* We pass a fully fixed up address to userland for MMIO instead of
495 * a BAR value because X is lame and expects to be able to use that
496 * to pass to /dev/mem !
498 * That means that we'll have potentially 64 bits values where some
499 * userland apps only expect 32 (like X itself since it thinks only
500 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
503 * Hopefully, the sysfs insterface is immune to that gunk. Once X
504 * has been fixed (and the fix spread enough), we can re-enable the
505 * 2 lines below and pass down a BAR value to userland. In that case
506 * we'll also have to re-enable the matching code in
507 * __pci_mmap_make_offset().
512 else if (rsrc
->flags
& IORESOURCE_MEM
)
513 offset
= hose
->pci_mem_offset
;
516 *start
= rsrc
->start
- offset
;
517 *end
= rsrc
->end
- offset
;
521 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
522 * @hose: newly allocated pci_controller to be setup
523 * @dev: device node of the host bridge
524 * @primary: set if primary bus (32 bits only, soon to be deprecated)
526 * This function will parse the "ranges" property of a PCI host bridge device
527 * node and setup the resource mapping of a pci controller based on its
530 * Life would be boring if it wasn't for a few issues that we have to deal
533 * - We can only cope with one IO space range and up to 3 Memory space
534 * ranges. However, some machines (thanks Apple !) tend to split their
535 * space into lots of small contiguous ranges. So we have to coalesce.
537 * - We can only cope with all memory ranges having the same offset
538 * between CPU addresses and PCI addresses. Unfortunately, some bridges
539 * are setup for a large 1:1 mapping along with a small "window" which
540 * maps PCI address 0 to some arbitrary high address of the CPU space in
541 * order to give access to the ISA memory hole.
542 * The way out of here that I've chosen for now is to always set the
543 * offset based on the first resource found, then override it if we
544 * have a different offset and the previous was set by an ISA hole.
546 * - Some busses have IO space not starting at 0, which causes trouble with
547 * the way we do our IO resource renumbering. The code somewhat deals with
548 * it for 64 bits but I would expect problems on 32 bits.
550 * - Some 32 bits platforms such as 4xx can have physical space larger than
551 * 32 bits so we need to use 64 bits values for the parsing
553 void pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
554 struct device_node
*dev
, int primary
)
556 int memno
= 0, isa_hole
= -1;
557 unsigned long long isa_mb
= 0;
558 struct resource
*res
;
559 struct of_pci_range range
;
560 struct of_pci_range_parser parser
;
562 pr_info("PCI host bridge %s %s ranges:\n",
563 dev
->full_name
, primary
? "(primary)" : "");
565 /* Check for ranges property */
566 if (of_pci_range_parser_init(&parser
, dev
))
569 pr_debug("Parsing ranges property...\n");
570 for_each_of_pci_range(&parser
, &range
) {
571 /* Read next ranges element */
572 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
573 range
.pci_space
, range
.pci_addr
);
574 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
575 range
.cpu_addr
, range
.size
);
577 /* If we failed translation or got a zero-sized region
578 * (some FW try to feed us with non sensical zero sized regions
579 * such as power3 which look like some kind of attempt
580 * at exposing the VGA memory hole)
582 if (range
.cpu_addr
== OF_BAD_ADDR
|| range
.size
== 0)
585 /* Act based on address space type */
587 switch (range
.flags
& IORESOURCE_TYPE_BITS
) {
589 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
590 range
.cpu_addr
, range
.cpu_addr
+ range
.size
- 1,
593 /* We support only one IO range */
594 if (hose
->pci_io_size
) {
595 pr_info(" \\--> Skipped (too many) !\n");
598 /* On 32 bits, limit I/O space to 16MB */
599 if (range
.size
> 0x01000000)
600 range
.size
= 0x01000000;
602 /* 32 bits needs to map IOs here */
603 hose
->io_base_virt
= ioremap(range
.cpu_addr
,
606 /* Expect trouble if pci_addr is not 0 */
609 (unsigned long)hose
->io_base_virt
;
610 /* pci_io_size and io_base_phys always represent IO
611 * space starting at 0 so we factor in pci_addr
613 hose
->pci_io_size
= range
.pci_addr
+ range
.size
;
614 hose
->io_base_phys
= range
.cpu_addr
- range
.pci_addr
;
617 res
= &hose
->io_resource
;
618 range
.cpu_addr
= range
.pci_addr
;
622 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
623 range
.cpu_addr
, range
.cpu_addr
+ range
.size
- 1,
625 (range
.pci_space
& 0x40000000) ?
628 /* We support only 3 memory ranges */
630 pr_info(" \\--> Skipped (too many) !\n");
633 /* Handles ISA memory hole space here */
634 if (range
.pci_addr
== 0) {
635 isa_mb
= range
.cpu_addr
;
637 if (primary
|| isa_mem_base
== 0)
638 isa_mem_base
= range
.cpu_addr
;
639 hose
->isa_mem_phys
= range
.cpu_addr
;
640 hose
->isa_mem_size
= range
.size
;
643 /* We get the PCI/Mem offset from the first range or
644 * the, current one if the offset came from an ISA
645 * hole. If they don't match, bugger.
648 (isa_hole
>= 0 && range
.pci_addr
!= 0 &&
649 hose
->pci_mem_offset
== isa_mb
))
650 hose
->pci_mem_offset
= range
.cpu_addr
-
652 else if (range
.pci_addr
!= 0 &&
653 hose
->pci_mem_offset
!= range
.cpu_addr
-
655 pr_info(" \\--> Skipped (offset mismatch) !\n");
660 res
= &hose
->mem_resources
[memno
++];
664 res
->name
= dev
->full_name
;
665 res
->flags
= range
.flags
;
666 res
->start
= range
.cpu_addr
;
667 res
->end
= range
.cpu_addr
+ range
.size
- 1;
668 res
->parent
= res
->child
= res
->sibling
= NULL
;
672 /* If there's an ISA hole and the pci_mem_offset is -not- matching
673 * the ISA hole offset, then we need to remove the ISA hole from
674 * the resource list for that brige
676 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
677 unsigned int next
= isa_hole
+ 1;
678 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb
);
680 memmove(&hose
->mem_resources
[isa_hole
],
681 &hose
->mem_resources
[next
],
682 sizeof(struct resource
) * (memno
- next
));
683 hose
->mem_resources
[--memno
].flags
= 0;
687 /* Decide whether to display the domain number in /proc */
688 int pci_proc_domain(struct pci_bus
*bus
)
693 /* This header fixup will do the resource fixup for all devices as they are
694 * probed, but not for bridge ranges
696 static void pcibios_fixup_resources(struct pci_dev
*dev
)
698 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
702 pr_err("No host bridge for PCI dev %s !\n",
706 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
707 struct resource
*res
= dev
->resource
+ i
;
710 if (res
->start
== 0) {
711 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
713 (unsigned long long)res
->start
,
714 (unsigned long long)res
->end
,
715 (unsigned int)res
->flags
);
716 pr_debug("is unassigned\n");
717 res
->end
-= res
->start
;
719 res
->flags
|= IORESOURCE_UNSET
;
723 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
725 (unsigned long long)res
->start
,
726 (unsigned long long)res
->end
,
727 (unsigned int)res
->flags
);
730 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
732 /* This function tries to figure out if a bridge resource has been initialized
733 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
734 * things go more smoothly when it gets it right. It should covers cases such
735 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
737 static int pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
738 struct resource
*res
)
740 struct pci_controller
*hose
= pci_bus_to_host(bus
);
741 struct pci_dev
*dev
= bus
->self
;
742 resource_size_t offset
;
746 /* Job is a bit different between memory and IO */
747 if (res
->flags
& IORESOURCE_MEM
) {
748 /* If the BAR is non-0 (res != pci_mem_offset) then it's
749 * probably been initialized by somebody
751 if (res
->start
!= hose
->pci_mem_offset
)
754 /* The BAR is 0, let's check if memory decoding is enabled on
755 * the bridge. If not, we consider it unassigned
757 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
758 if ((command
& PCI_COMMAND_MEMORY
) == 0)
761 /* Memory decoding is enabled and the BAR is 0. If any of
762 * the bridge resources covers that starting address (0 then
763 * it's good enough for us for memory
765 for (i
= 0; i
< 3; i
++) {
766 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
767 hose
->mem_resources
[i
].start
== hose
->pci_mem_offset
)
771 /* Well, it starts at 0 and we know it will collide so we may as
772 * well consider it as unassigned. That covers the Apple case.
776 /* If the BAR is non-0, then we consider it assigned */
777 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
778 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
781 /* Here, we are a bit different than memory as typically IO
782 * space starting at low addresses -is- valid. What we do
783 * instead if that we consider as unassigned anything that
784 * doesn't have IO enabled in the PCI command register,
787 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
788 if (command
& PCI_COMMAND_IO
)
791 /* It's starting at 0 and IO is disabled in the bridge, consider
798 /* Fixup resources of a PCI<->PCI bridge */
799 static void pcibios_fixup_bridge(struct pci_bus
*bus
)
801 struct resource
*res
;
804 struct pci_dev
*dev
= bus
->self
;
806 pci_bus_for_each_resource(bus
, res
, i
) {
811 if (i
>= 3 && bus
->self
->transparent
)
814 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
816 (unsigned long long)res
->start
,
817 (unsigned long long)res
->end
,
818 (unsigned int)res
->flags
);
820 /* Try to detect uninitialized P2P bridge resources,
821 * and clear them out so they get re-assigned later
823 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
825 pr_debug("PCI:%s (unassigned)\n",
828 pr_debug("PCI:%s %016llx-%016llx\n",
830 (unsigned long long)res
->start
,
831 (unsigned long long)res
->end
);
836 void pcibios_setup_bus_self(struct pci_bus
*bus
)
838 /* Fix up the bus resources for P2P bridges */
839 if (bus
->self
!= NULL
)
840 pcibios_fixup_bridge(bus
);
843 void pcibios_setup_bus_devices(struct pci_bus
*bus
)
847 pr_debug("PCI: Fixup bus devices %d (%s)\n",
848 bus
->number
, bus
->self
? pci_name(bus
->self
) : "PHB");
850 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
851 /* Setup OF node pointer in archdata */
852 dev
->dev
.of_node
= pci_device_to_OF_node(dev
);
854 /* Fixup NUMA node as it may not be setup yet by the generic
855 * code and is needed by the DMA init
857 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
859 /* Read default IRQs and fixup if necessary */
860 dev
->irq
= of_irq_parse_and_map_pci(dev
, 0, 0);
864 void pcibios_fixup_bus(struct pci_bus
*bus
)
867 pcibios_setup_bus_self(bus
);
869 /* Now fixup devices on that bus */
870 pcibios_setup_bus_devices(bus
);
872 EXPORT_SYMBOL(pcibios_fixup_bus
);
874 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
880 * We need to avoid collisions with `mirrored' VGA ports
881 * and other strange ISA hardware, so we always want the
882 * addresses to be allocated in the 0x000-0x0ff region
885 * Why? Because some silly external IO cards only decode
886 * the low 10 bits of the IO address. The 0x00-0xff region
887 * is reserved for motherboard devices that decode all 16
888 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
889 * but we want to try to avoid allocating at 0x2900-0x2bff
890 * which might have be mirrored at 0x0100-0x03ff..
892 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
893 resource_size_t size
, resource_size_t align
)
895 struct pci_dev
*dev
= data
;
896 resource_size_t start
= res
->start
;
898 if (res
->flags
& IORESOURCE_IO
) {
899 if (skip_isa_ioresource_align(dev
))
902 start
= (start
+ 0x3ff) & ~0x3ff;
907 EXPORT_SYMBOL(pcibios_align_resource
);
910 * Reparent resource children of pr that conflict with res
911 * under res, and make res replace those children.
913 static int __init
reparent_resources(struct resource
*parent
,
914 struct resource
*res
)
916 struct resource
*p
, **pp
;
917 struct resource
**firstpp
= NULL
;
919 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
920 if (p
->end
< res
->start
)
922 if (res
->end
< p
->start
)
924 if (p
->start
< res
->start
|| p
->end
> res
->end
)
925 return -1; /* not completely contained */
930 return -1; /* didn't find any conflicting entries? */
931 res
->parent
= parent
;
932 res
->child
= *firstpp
;
936 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
938 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
940 (unsigned long long)p
->start
,
941 (unsigned long long)p
->end
, res
->name
);
947 * Handle resources of PCI devices. If the world were perfect, we could
948 * just allocate all the resource regions and do nothing more. It isn't.
949 * On the other hand, we cannot just re-allocate all devices, as it would
950 * require us to know lots of host bridge internals. So we attempt to
951 * keep as much of the original configuration as possible, but tweak it
952 * when it's found to be wrong.
954 * Known BIOS problems we have to work around:
955 * - I/O or memory regions not configured
956 * - regions configured, but not enabled in the command register
957 * - bogus I/O addresses above 64K used
958 * - expansion ROMs left enabled (this may sound harmless, but given
959 * the fact the PCI specs explicitly allow address decoders to be
960 * shared between expansion ROMs and other resource regions, it's
961 * at least dangerous)
964 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
965 * This gives us fixed barriers on where we can allocate.
966 * (2) Allocate resources for all enabled devices. If there is
967 * a collision, just mark the resource as unallocated. Also
968 * disable expansion ROMs during this step.
969 * (3) Try to allocate resources for disabled devices. If the
970 * resources were assigned correctly, everything goes well,
971 * if they weren't, they won't disturb allocation of other
973 * (4) Assign new addresses to resources which were either
974 * not configured at all or misconfigured. If explicitly
975 * requested by the user, configure expansion ROM address
979 static void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
983 struct resource
*res
, *pr
;
985 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
986 pci_domain_nr(bus
), bus
->number
);
988 pci_bus_for_each_resource(bus
, res
, i
) {
989 if (!res
|| !res
->flags
990 || res
->start
> res
->end
|| res
->parent
)
992 if (bus
->parent
== NULL
)
993 pr
= (res
->flags
& IORESOURCE_IO
) ?
994 &ioport_resource
: &iomem_resource
;
996 /* Don't bother with non-root busses when
997 * re-assigning all resources. We clear the
998 * resource flags as if they were colliding
999 * and as such ensure proper re-allocation
1002 pr
= pci_find_parent_resource(bus
->self
, res
);
1004 /* this happens when the generic PCI
1005 * code (wrongly) decides that this
1006 * bridge is transparent -- paulus
1012 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
1013 bus
->self
? pci_name(bus
->self
) : "PHB",
1015 (unsigned long long)res
->start
,
1016 (unsigned long long)res
->end
);
1017 pr_debug("[0x%x], parent %p (%s)\n",
1018 (unsigned int)res
->flags
,
1019 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1021 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1022 struct pci_dev
*dev
= bus
->self
;
1024 if (request_resource(pr
, res
) == 0)
1027 * Must be a conflict with an existing entry.
1028 * Move that entry (or entries) under the
1029 * bridge resource and try again.
1031 if (reparent_resources(pr
, res
) == 0)
1034 if (dev
&& i
< PCI_BRIDGE_RESOURCE_NUM
&&
1035 pci_claim_bridge_resource(dev
,
1036 i
+ PCI_BRIDGE_RESOURCES
) == 0)
1040 pr_warn("PCI: Cannot allocate resource region ");
1041 pr_cont("%d of PCI bridge %d, will remap\n", i
, bus
->number
);
1042 res
->start
= res
->end
= 0;
1046 list_for_each_entry(b
, &bus
->children
, node
)
1047 pcibios_allocate_bus_resources(b
);
1050 static inline void alloc_resource(struct pci_dev
*dev
, int idx
)
1052 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1054 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1056 (unsigned long long)r
->start
,
1057 (unsigned long long)r
->end
,
1058 (unsigned int)r
->flags
);
1060 pr
= pci_find_parent_resource(dev
, r
);
1061 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1062 request_resource(pr
, r
) < 0) {
1063 pr_warn("PCI: Cannot allocate resource region %d ", idx
);
1064 pr_cont("of device %s, will remap\n", pci_name(dev
));
1066 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1068 (unsigned long long)pr
->start
,
1069 (unsigned long long)pr
->end
,
1070 (unsigned int)pr
->flags
);
1071 /* We'll assign a new address later */
1072 r
->flags
|= IORESOURCE_UNSET
;
1078 static void __init
pcibios_allocate_resources(int pass
)
1080 struct pci_dev
*dev
= NULL
;
1085 for_each_pci_dev(dev
) {
1086 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1087 for (idx
= 0; idx
<= PCI_ROM_RESOURCE
; idx
++) {
1088 r
= &dev
->resource
[idx
];
1089 if (r
->parent
) /* Already allocated */
1091 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1092 continue; /* Not assigned at all */
1093 /* We only allocate ROMs on pass 1 just in case they
1094 * have been screwed up by firmware
1096 if (idx
== PCI_ROM_RESOURCE
)
1098 if (r
->flags
& IORESOURCE_IO
)
1099 disabled
= !(command
& PCI_COMMAND_IO
);
1101 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1102 if (pass
== disabled
)
1103 alloc_resource(dev
, idx
);
1107 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1109 /* Turn the ROM off, leave the resource region,
1110 * but keep it unregistered.
1113 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1114 if (reg
& PCI_ROM_ADDRESS_ENABLE
) {
1115 pr_debug("PCI: Switching off ROM of %s\n",
1117 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1118 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1119 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1125 static void __init
pcibios_reserve_legacy_regions(struct pci_bus
*bus
)
1127 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1128 resource_size_t offset
;
1129 struct resource
*res
, *pres
;
1132 pr_debug("Reserving legacy ranges for domain %04x\n",
1133 pci_domain_nr(bus
));
1136 if (!(hose
->io_resource
.flags
& IORESOURCE_IO
))
1138 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1139 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1140 BUG_ON(res
== NULL
);
1141 res
->name
= "Legacy IO";
1142 res
->flags
= IORESOURCE_IO
;
1143 res
->start
= offset
;
1144 res
->end
= (offset
+ 0xfff) & 0xfffffffful
;
1145 pr_debug("Candidate legacy IO: %pR\n", res
);
1146 if (request_resource(&hose
->io_resource
, res
)) {
1147 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1148 pci_domain_nr(bus
), bus
->number
, res
);
1153 /* Check for memory */
1154 offset
= hose
->pci_mem_offset
;
1155 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset
);
1156 for (i
= 0; i
< 3; i
++) {
1157 pres
= &hose
->mem_resources
[i
];
1158 if (!(pres
->flags
& IORESOURCE_MEM
))
1160 pr_debug("hose mem res: %pR\n", pres
);
1161 if ((pres
->start
- offset
) <= 0xa0000 &&
1162 (pres
->end
- offset
) >= 0xbffff)
1167 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1168 BUG_ON(res
== NULL
);
1169 res
->name
= "Legacy VGA memory";
1170 res
->flags
= IORESOURCE_MEM
;
1171 res
->start
= 0xa0000 + offset
;
1172 res
->end
= 0xbffff + offset
;
1173 pr_debug("Candidate VGA memory: %pR\n", res
);
1174 if (request_resource(pres
, res
)) {
1175 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1176 pci_domain_nr(bus
), bus
->number
, res
);
1181 void __init
pcibios_resource_survey(void)
1185 /* Allocate and assign resources. If we re-assign everything, then
1186 * we skip the allocate phase
1188 list_for_each_entry(b
, &pci_root_buses
, node
)
1189 pcibios_allocate_bus_resources(b
);
1191 pcibios_allocate_resources(0);
1192 pcibios_allocate_resources(1);
1194 /* Before we start assigning unassigned resource, we try to reserve
1195 * the low IO area and the VGA memory area if they intersect the
1196 * bus available resources to avoid allocating things on top of them
1198 list_for_each_entry(b
, &pci_root_buses
, node
)
1199 pcibios_reserve_legacy_regions(b
);
1201 /* Now proceed to assigning things that were left unassigned */
1202 pr_debug("PCI: Assigning unassigned resources...\n");
1203 pci_assign_unassigned_resources();
1206 /* This is used by the PCI hotplug driver to allocate resource
1207 * of newly plugged busses. We can try to consolidate with the
1208 * rest of the code later, for now, keep it as-is as our main
1209 * resource allocation function doesn't deal with sub-trees yet.
1211 void pcibios_claim_one_bus(struct pci_bus
*bus
)
1213 struct pci_dev
*dev
;
1214 struct pci_bus
*child_bus
;
1216 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1219 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1220 struct resource
*r
= &dev
->resource
[i
];
1222 if (r
->parent
|| !r
->start
|| !r
->flags
)
1225 pr_debug("PCI: Claiming %s: ", pci_name(dev
));
1226 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
1227 i
, (unsigned long long)r
->start
,
1228 (unsigned long long)r
->end
,
1229 (unsigned int)r
->flags
);
1231 if (pci_claim_resource(dev
, i
) == 0)
1234 pci_claim_bridge_resource(dev
, i
);
1238 list_for_each_entry(child_bus
, &bus
->children
, node
)
1239 pcibios_claim_one_bus(child_bus
);
1241 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
1244 /* pcibios_finish_adding_to_bus
1246 * This is to be called by the hotplug code after devices have been
1247 * added to a bus, this include calling it for a PHB that is just
1250 void pcibios_finish_adding_to_bus(struct pci_bus
*bus
)
1252 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1253 pci_domain_nr(bus
), bus
->number
);
1255 /* Allocate bus and devices resources */
1256 pcibios_allocate_bus_resources(bus
);
1257 pcibios_claim_one_bus(bus
);
1259 /* Add new devices to global lists. Register in proc, sysfs. */
1260 pci_bus_add_devices(bus
);
1263 /* eeh_add_device_tree_late(bus); */
1265 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus
);
1267 static void pcibios_setup_phb_resources(struct pci_controller
*hose
,
1268 struct list_head
*resources
)
1270 unsigned long io_offset
;
1271 struct resource
*res
;
1274 /* Hookup PHB IO resource */
1275 res
= &hose
->io_resource
;
1277 /* Fixup IO space offset */
1278 io_offset
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1279 res
->start
= (res
->start
+ io_offset
) & 0xffffffffu
;
1280 res
->end
= (res
->end
+ io_offset
) & 0xffffffffu
;
1283 pr_warn("PCI: I/O resource not set for host ");
1284 pr_cont("bridge %s (domain %d)\n",
1285 hose
->dn
->full_name
, hose
->global_number
);
1286 /* Workaround for lack of IO resource only on 32-bit */
1287 res
->start
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1288 res
->end
= res
->start
+ IO_SPACE_LIMIT
;
1289 res
->flags
= IORESOURCE_IO
;
1291 pci_add_resource_offset(resources
, res
,
1292 (__force resource_size_t
)(hose
->io_base_virt
- _IO_BASE
));
1294 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1295 (unsigned long long)res
->start
,
1296 (unsigned long long)res
->end
,
1297 (unsigned long)res
->flags
);
1299 /* Hookup PHB Memory resources */
1300 for (i
= 0; i
< 3; ++i
) {
1301 res
= &hose
->mem_resources
[i
];
1305 pr_err("PCI: Memory resource 0 not set for ");
1306 pr_cont("host bridge %s (domain %d)\n",
1307 hose
->dn
->full_name
, hose
->global_number
);
1309 /* Workaround for lack of MEM resource only on 32-bit */
1310 res
->start
= hose
->pci_mem_offset
;
1311 res
->end
= (resource_size_t
)-1LL;
1312 res
->flags
= IORESOURCE_MEM
;
1315 pci_add_resource_offset(resources
, res
, hose
->pci_mem_offset
);
1317 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1318 i
, (unsigned long long)res
->start
,
1319 (unsigned long long)res
->end
,
1320 (unsigned long)res
->flags
);
1323 pr_debug("PCI: PHB MEM offset = %016llx\n",
1324 (unsigned long long)hose
->pci_mem_offset
);
1325 pr_debug("PCI: PHB IO offset = %08lx\n",
1326 (unsigned long)hose
->io_base_virt
- _IO_BASE
);
1329 struct device_node
*pcibios_get_phb_of_node(struct pci_bus
*bus
)
1331 struct pci_controller
*hose
= bus
->sysdata
;
1333 return of_node_get(hose
->dn
);
1336 static void pcibios_scan_phb(struct pci_controller
*hose
)
1338 LIST_HEAD(resources
);
1339 struct pci_bus
*bus
;
1340 struct device_node
*node
= hose
->dn
;
1342 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node
));
1344 pcibios_setup_phb_resources(hose
, &resources
);
1346 bus
= pci_scan_root_bus(hose
->parent
, hose
->first_busno
,
1347 hose
->ops
, hose
, &resources
);
1349 pr_err("Failed to create bus for PCI domain %04x\n",
1350 hose
->global_number
);
1351 pci_free_resource_list(&resources
);
1354 bus
->busn_res
.start
= hose
->first_busno
;
1357 hose
->last_busno
= bus
->busn_res
.end
;
1360 static int __init
pcibios_init(void)
1362 struct pci_controller
*hose
, *tmp
;
1365 pr_info("PCI: Probing PCI hardware\n");
1367 /* Scan all of the recorded PCI controllers. */
1368 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1369 hose
->last_busno
= 0xff;
1370 pcibios_scan_phb(hose
);
1371 if (next_busno
<= hose
->last_busno
)
1372 next_busno
= hose
->last_busno
+ 1;
1374 pci_bus_count
= next_busno
;
1376 /* Call common code to handle resource allocation */
1377 pcibios_resource_survey();
1378 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1380 pci_bus_add_devices(hose
->bus
);
1386 subsys_initcall(pcibios_init
);
1388 static struct pci_controller
*pci_bus_to_hose(int bus
)
1390 struct pci_controller
*hose
, *tmp
;
1392 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1393 if (bus
>= hose
->first_busno
&& bus
<= hose
->last_busno
)
1398 /* Provide information on locations of various I/O regions in physical
1399 * memory. Do this on a per-card basis so that we choose the right
1401 * Note that the returned IO or memory base is a physical address
1404 long sys_pciconfig_iobase(long which
, unsigned long bus
, unsigned long devfn
)
1406 struct pci_controller
*hose
;
1407 long result
= -EOPNOTSUPP
;
1409 hose
= pci_bus_to_hose(bus
);
1414 case IOBASE_BRIDGE_NUMBER
:
1415 return (long)hose
->first_busno
;
1417 return (long)hose
->pci_mem_offset
;
1419 return (long)hose
->io_base_phys
;
1421 return (long)isa_io_base
;
1422 case IOBASE_ISA_MEM
:
1423 return (long)isa_mem_base
;
1430 * Null PCI config access functions, for the case when we can't
1433 #define NULL_PCI_OP(rw, size, type) \
1435 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1437 return PCIBIOS_DEVICE_NOT_FOUND; \
1441 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1444 return PCIBIOS_DEVICE_NOT_FOUND
;
1448 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1451 return PCIBIOS_DEVICE_NOT_FOUND
;
1454 static struct pci_ops null_pci_ops
= {
1455 .read
= null_read_config
,
1456 .write
= null_write_config
,
1460 * These functions are used early on before PCI scanning is done
1461 * and all of the pci_dev and pci_bus structures have been created.
1463 static struct pci_bus
*
1464 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
1466 static struct pci_bus bus
;
1469 pr_err("Can't find hose for PCI bus %d!\n", busnr
);
1473 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
1477 #define EARLY_PCI_OP(rw, size, type) \
1478 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1479 int devfn, int offset, type value) \
1481 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1482 devfn, offset, value); \
1485 EARLY_PCI_OP(read
, byte
, u8
*)
1486 EARLY_PCI_OP(read
, word
, u16
*)
1487 EARLY_PCI_OP(read
, dword
, u32
*)
1488 EARLY_PCI_OP(write
, byte
, u8
)
1489 EARLY_PCI_OP(write
, word
, u16
)
1490 EARLY_PCI_OP(write
, dword
, u32
)
1492 int early_find_capability(struct pci_controller
*hose
, int bus
, int devfn
,
1495 return pci_bus_find_capability(fake_pci_bus(hose
, bus
), devfn
, cap
);