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MIPS: Alchemy: au1xmmc: use clk framework
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1 /*
2 * BRIEF MODULE DESCRIPTION
3 * Simple Au1xx0 clocks routines.
4 *
5 * Copyright 2001, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29 #include <linux/module.h>
30 #include <linux/spinlock.h>
31 #include <asm/time.h>
32 #include <asm/mach-au1x00/au1000.h>
33
34 /*
35 * I haven't found anyone that doesn't use a 12 MHz source clock,
36 * but just in case.....
37 */
38 #define AU1000_SRC_CLK 12000000
39
40 static unsigned int au1x00_clock; /* Hz */
41
42 /*
43 * Set the au1000_clock
44 */
45 void set_au1x00_speed(unsigned int new_freq)
46 {
47 au1x00_clock = new_freq;
48 }
49
50 unsigned int get_au1x00_speed(void)
51 {
52 return au1x00_clock;
53 }
54 EXPORT_SYMBOL(get_au1x00_speed);
55
56 /*
57 * We read the real processor speed from the PLL. This is important
58 * because it is more accurate than computing it from the 32 KHz
59 * counter, if it exists. If we don't have an accurate processor
60 * speed, all of the peripherals that derive their clocks based on
61 * this advertised speed will introduce error and sometimes not work
62 * properly. This function is further convoluted to still allow configurations
63 * to do that in case they have really, really old silicon with a
64 * write-only PLL register. -- Dan
65 */
66 unsigned long au1xxx_calc_clock(void)
67 {
68 unsigned long cpu_speed;
69
70 /*
71 * On early Au1000, sys_cpupll was write-only. Since these
72 * silicon versions of Au1000 are not sold by AMD, we don't bend
73 * over backwards trying to determine the frequency.
74 */
75 if (au1xxx_cpu_has_pll_wo())
76 cpu_speed = 396000000;
77 else
78 cpu_speed = (alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x3f) * AU1000_SRC_CLK;
79
80 /* On Alchemy CPU:counter ratio is 1:1 */
81 mips_hpt_frequency = cpu_speed;
82
83 set_au1x00_speed(cpu_speed);
84
85 return cpu_speed;
86 }