arch/mips/alchemy/devboards/db1000.c

   1 /*
   2  * DBAu1000/1500/1100 PBAu1100/1500 board support
   3  *
   4  * Copyright 2000, 2008 MontaVista Software Inc.
   5  * Author: MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21
  22 #include <linux/clk.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/gpio.h>
  25 #include <linux/gpio/machine.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/leds.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/module.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/pm.h>
  33 #include <linux/spi/spi.h>
  34 #include <linux/spi/spi_gpio.h>
  35 #include <linux/spi/ads7846.h>
  36 #include <asm/mach-au1x00/au1000.h>
  37 #include <asm/mach-au1x00/gpio-au1000.h>
  38 #include <asm/mach-au1x00/au1000_dma.h>
  39 #include <asm/mach-au1x00/au1100_mmc.h>
  40 #include <asm/mach-db1x00/bcsr.h>
  41 #include <asm/reboot.h>
  42 #include <prom.h>
  43 #include "platform.h"
  44
  45 #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
  46
  47 const char *get_system_type(void);
  48
  49 int __init db1000_board_setup(void)
  50 {
  51         /* initialize board register space */
  52         bcsr_init(DB1000_BCSR_PHYS_ADDR,
  53                   DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
  54
  55         switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
  56         case BCSR_WHOAMI_DB1000:
  57         case BCSR_WHOAMI_DB1500:
  58         case BCSR_WHOAMI_DB1100:
  59         case BCSR_WHOAMI_PB1500:
  60         case BCSR_WHOAMI_PB1500R2:
  61         case BCSR_WHOAMI_PB1100:
  62                 pr_info("AMD Alchemy %s Board\n", get_system_type());
  63                 return 0;
  64         }
  65         return -ENODEV;
  66 }
  67
  68 static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
  69 {
  70         if ((slot < 12) || (slot > 13) || pin == 0)
  71                 return -1;
  72         if (slot == 12)
  73                 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
  74         if (slot == 13) {
  75                 switch (pin) {
  76                 case 1: return AU1500_PCI_INTA;
  77                 case 2: return AU1500_PCI_INTB;
  78                 case 3: return AU1500_PCI_INTC;
  79                 case 4: return AU1500_PCI_INTD;
  80                 }
  81         }
  82         return -1;
  83 }
  84
  85 static u64 au1xxx_all_dmamask = DMA_BIT_MASK(32);
  86
  87 static struct resource alchemy_pci_host_res[] = {
  88         [0] = {
  89                 .start  = AU1500_PCI_PHYS_ADDR,
  90                 .end    = AU1500_PCI_PHYS_ADDR + 0xfff,
  91                 .flags  = IORESOURCE_MEM,
  92         },
  93 };
  94
  95 static struct alchemy_pci_platdata db1500_pci_pd = {
  96         .board_map_irq  = db1500_map_pci_irq,
  97 };
  98
  99 static struct platform_device db1500_pci_host_dev = {
 100         .dev.platform_data = &db1500_pci_pd,
 101         .name           = "alchemy-pci",
 102         .id             = 0,
 103         .num_resources  = ARRAY_SIZE(alchemy_pci_host_res),
 104         .resource       = alchemy_pci_host_res,
 105 };
 106
 107 int __init db1500_pci_setup(void)
 108 {
 109         return platform_device_register(&db1500_pci_host_dev);
 110 }
 111
 112 static struct resource au1100_lcd_resources[] = {
 113         [0] = {
 114                 .start  = AU1100_LCD_PHYS_ADDR,
 115                 .end    = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
 116                 .flags  = IORESOURCE_MEM,
 117         },
 118         [1] = {
 119                 .start  = AU1100_LCD_INT,
 120                 .end    = AU1100_LCD_INT,
 121                 .flags  = IORESOURCE_IRQ,
 122         }
 123 };
 124
 125 static struct platform_device au1100_lcd_device = {
 126         .name           = "au1100-lcd",
 127         .id             = 0,
 128         .dev = {
 129                 .dma_mask               = &au1xxx_all_dmamask,
 130                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 131         },
 132         .num_resources  = ARRAY_SIZE(au1100_lcd_resources),
 133         .resource       = au1100_lcd_resources,
 134 };
 135
 136 static struct resource alchemy_ac97c_res[] = {
 137         [0] = {
 138                 .start  = AU1000_AC97_PHYS_ADDR,
 139                 .end    = AU1000_AC97_PHYS_ADDR + 0xfff,
 140                 .flags  = IORESOURCE_MEM,
 141         },
 142         [1] = {
 143                 .start  = DMA_ID_AC97C_TX,
 144                 .end    = DMA_ID_AC97C_TX,
 145                 .flags  = IORESOURCE_DMA,
 146         },
 147         [2] = {
 148                 .start  = DMA_ID_AC97C_RX,
 149                 .end    = DMA_ID_AC97C_RX,
 150                 .flags  = IORESOURCE_DMA,
 151         },
 152 };
 153
 154 static struct platform_device alchemy_ac97c_dev = {
 155         .name           = "alchemy-ac97c",
 156         .id             = -1,
 157         .resource       = alchemy_ac97c_res,
 158         .num_resources  = ARRAY_SIZE(alchemy_ac97c_res),
 159 };
 160
 161 static struct platform_device alchemy_ac97c_dma_dev = {
 162         .name           = "alchemy-pcm-dma",
 163         .id             = 0,
 164 };
 165
 166 static struct platform_device db1x00_codec_dev = {
 167         .name           = "ac97-codec",
 168         .id             = -1,
 169 };
 170
 171 static struct platform_device db1x00_audio_dev = {
 172         .name           = "db1000-audio",
 173         .dev = {
 174                 .dma_mask               = &au1xxx_all_dmamask,
 175                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 176         },
 177 };
 178
 179 /******************************************************************************/
 180
 181 static irqreturn_t db1100_mmc_cd(int irq, void *ptr)
 182 {
 183         void (*mmc_cd)(struct mmc_host *, unsigned long);
 184         /* link against CONFIG_MMC=m */
 185         mmc_cd = symbol_get(mmc_detect_change);
 186         mmc_cd(ptr, msecs_to_jiffies(500));
 187         symbol_put(mmc_detect_change);
 188
 189         return IRQ_HANDLED;
 190 }
 191
 192 static int db1100_mmc_cd_setup(void *mmc_host, int en)
 193 {
 194         int ret = 0, irq;
 195
 196         if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
 197                 irq = AU1100_GPIO19_INT;
 198         else
 199                 irq = AU1100_GPIO14_INT;        /* PB1100 SD0 CD# */
 200
 201         if (en) {
 202                 irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
 203                 ret = request_irq(irq, db1100_mmc_cd, 0,
 204                                   "sd0_cd", mmc_host);
 205         } else
 206                 free_irq(irq, mmc_host);
 207         return ret;
 208 }
 209
 210 static int db1100_mmc1_cd_setup(void *mmc_host, int en)
 211 {
 212         int ret = 0, irq;
 213
 214         if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
 215                 irq = AU1100_GPIO20_INT;
 216         else
 217                 irq = AU1100_GPIO15_INT;        /* PB1100 SD1 CD# */
 218
 219         if (en) {
 220                 irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
 221                 ret = request_irq(irq, db1100_mmc_cd, 0,
 222                                   "sd1_cd", mmc_host);
 223         } else
 224                 free_irq(irq, mmc_host);
 225         return ret;
 226 }
 227
 228 static int db1100_mmc_card_readonly(void *mmc_host)
 229 {
 230         /* testing suggests that this bit is inverted */
 231         return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 0 : 1;
 232 }
 233
 234 static int db1100_mmc_card_inserted(void *mmc_host)
 235 {
 236         return !alchemy_gpio_get_value(19);
 237 }
 238
 239 static void db1100_mmc_set_power(void *mmc_host, int state)
 240 {
 241         int bit;
 242
 243         if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
 244                 bit = BCSR_BOARD_SD0PWR;
 245         else
 246                 bit = BCSR_BOARD_PB1100_SD0PWR;
 247
 248         if (state) {
 249                 bcsr_mod(BCSR_BOARD, 0, bit);
 250                 msleep(400);    /* stabilization time */
 251         } else
 252                 bcsr_mod(BCSR_BOARD, bit, 0);
 253 }
 254
 255 static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b)
 256 {
 257         if (b != LED_OFF)
 258                 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
 259         else
 260                 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
 261 }
 262
 263 static struct led_classdev db1100_mmc_led = {
 264         .brightness_set = db1100_mmcled_set,
 265 };
 266
 267 static int db1100_mmc1_card_readonly(void *mmc_host)
 268 {
 269         return (bcsr_read(BCSR_BOARD) & BCSR_BOARD_SD1WP) ? 1 : 0;
 270 }
 271
 272 static int db1100_mmc1_card_inserted(void *mmc_host)
 273 {
 274         return !alchemy_gpio_get_value(20);
 275 }
 276
 277 static void db1100_mmc1_set_power(void *mmc_host, int state)
 278 {
 279         int bit;
 280
 281         if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
 282                 bit = BCSR_BOARD_SD1PWR;
 283         else
 284                 bit = BCSR_BOARD_PB1100_SD1PWR;
 285
 286         if (state) {
 287                 bcsr_mod(BCSR_BOARD, 0, bit);
 288                 msleep(400);    /* stabilization time */
 289         } else
 290                 bcsr_mod(BCSR_BOARD, bit, 0);
 291 }
 292
 293 static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b)
 294 {
 295         if (b != LED_OFF)
 296                 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
 297         else
 298                 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
 299 }
 300
 301 static struct led_classdev db1100_mmc1_led = {
 302         .brightness_set = db1100_mmc1led_set,
 303 };
 304
 305 static struct au1xmmc_platform_data db1100_mmc_platdata[2] = {
 306         [0] = {
 307                 .cd_setup       = db1100_mmc_cd_setup,
 308                 .set_power      = db1100_mmc_set_power,
 309                 .card_inserted  = db1100_mmc_card_inserted,
 310                 .card_readonly  = db1100_mmc_card_readonly,
 311                 .led            = &db1100_mmc_led,
 312         },
 313         [1] = {
 314                 .cd_setup       = db1100_mmc1_cd_setup,
 315                 .set_power      = db1100_mmc1_set_power,
 316                 .card_inserted  = db1100_mmc1_card_inserted,
 317                 .card_readonly  = db1100_mmc1_card_readonly,
 318                 .led            = &db1100_mmc1_led,
 319         },
 320 };
 321
 322 static struct resource au1100_mmc0_resources[] = {
 323         [0] = {
 324                 .start  = AU1100_SD0_PHYS_ADDR,
 325                 .end    = AU1100_SD0_PHYS_ADDR + 0xfff,
 326                 .flags  = IORESOURCE_MEM,
 327         },
 328         [1] = {
 329                 .start  = AU1100_SD_INT,
 330                 .end    = AU1100_SD_INT,
 331                 .flags  = IORESOURCE_IRQ,
 332         },
 333         [2] = {
 334                 .start  = DMA_ID_SD0_TX,
 335                 .end    = DMA_ID_SD0_TX,
 336                 .flags  = IORESOURCE_DMA,
 337         },
 338         [3] = {
 339                 .start  = DMA_ID_SD0_RX,
 340                 .end    = DMA_ID_SD0_RX,
 341                 .flags  = IORESOURCE_DMA,
 342         }
 343 };
 344
 345 static struct platform_device db1100_mmc0_dev = {
 346         .name           = "au1xxx-mmc",
 347         .id             = 0,
 348         .dev = {
 349                 .dma_mask               = &au1xxx_all_dmamask,
 350                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 351                 .platform_data          = &db1100_mmc_platdata[0],
 352         },
 353         .num_resources  = ARRAY_SIZE(au1100_mmc0_resources),
 354         .resource       = au1100_mmc0_resources,
 355 };
 356
 357 static struct resource au1100_mmc1_res[] = {
 358         [0] = {
 359                 .start  = AU1100_SD1_PHYS_ADDR,
 360                 .end    = AU1100_SD1_PHYS_ADDR + 0xfff,
 361                 .flags  = IORESOURCE_MEM,
 362         },
 363         [1] = {
 364                 .start  = AU1100_SD_INT,
 365                 .end    = AU1100_SD_INT,
 366                 .flags  = IORESOURCE_IRQ,
 367         },
 368         [2] = {
 369                 .start  = DMA_ID_SD1_TX,
 370                 .end    = DMA_ID_SD1_TX,
 371                 .flags  = IORESOURCE_DMA,
 372         },
 373         [3] = {
 374                 .start  = DMA_ID_SD1_RX,
 375                 .end    = DMA_ID_SD1_RX,
 376                 .flags  = IORESOURCE_DMA,
 377         }
 378 };
 379
 380 static struct platform_device db1100_mmc1_dev = {
 381         .name           = "au1xxx-mmc",
 382         .id             = 1,
 383         .dev = {
 384                 .dma_mask               = &au1xxx_all_dmamask,
 385                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 386                 .platform_data          = &db1100_mmc_platdata[1],
 387         },
 388         .num_resources  = ARRAY_SIZE(au1100_mmc1_res),
 389         .resource       = au1100_mmc1_res,
 390 };
 391
 392 /******************************************************************************/
 393
 394 static struct ads7846_platform_data db1100_touch_pd = {
 395         .model          = 7846,
 396         .vref_mv        = 3300,
 397         .gpio_pendown   = 21,
 398 };
 399
 400 static struct spi_gpio_platform_data db1100_spictl_pd = {
 401         .num_chipselect = 1,
 402 };
 403
 404 static struct spi_board_info db1100_spi_info[] __initdata = {
 405         [0] = {
 406                 .modalias        = "ads7846",
 407                 .max_speed_hz    = 3250000,
 408                 .bus_num         = 0,
 409                 .chip_select     = 0,
 410                 .mode            = 0,
 411                 .irq             = AU1100_GPIO21_INT,
 412                 .platform_data   = &db1100_touch_pd,
 413         },
 414 };
 415
 416 static struct platform_device db1100_spi_dev = {
 417         .name           = "spi_gpio",
 418         .id             = 0,
 419         .dev            = {
 420                 .platform_data  = &db1100_spictl_pd,
 421                 .dma_mask               = &au1xxx_all_dmamask,
 422                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 423         },
 424 };
 425
 426 /*
 427  * Alchemy GPIO 2 has its base at 200 so the GPIO lines
 428  * 207 thru 210 are GPIOs at offset 7 thru 10 at this chip.
 429  */
 430 static struct gpiod_lookup_table db1100_spi_gpiod_table = {
 431         .dev_id         = "spi_gpio",
 432         .table          = {
 433                 GPIO_LOOKUP("alchemy-gpio2", 9,
 434                             "sck", GPIO_ACTIVE_HIGH),
 435                 GPIO_LOOKUP("alchemy-gpio2", 8,
 436                             "mosi", GPIO_ACTIVE_HIGH),
 437                 GPIO_LOOKUP("alchemy-gpio2", 7,
 438                             "miso", GPIO_ACTIVE_HIGH),
 439                 GPIO_LOOKUP("alchemy-gpio2", 10,
 440                             "cs", GPIO_ACTIVE_HIGH),
 441                 { },
 442         },
 443 };
 444
 445 static struct platform_device *db1x00_devs[] = {
 446         &db1x00_codec_dev,
 447         &alchemy_ac97c_dma_dev,
 448         &alchemy_ac97c_dev,
 449         &db1x00_audio_dev,
 450 };
 451
 452 static struct platform_device *db1100_devs[] = {
 453         &au1100_lcd_device,
 454         &db1100_mmc0_dev,
 455         &db1100_mmc1_dev,
 456 };
 457
 458 int __init db1000_dev_setup(void)
 459 {
 460         int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
 461         int c0, c1, d0, d1, s0, s1, flashsize = 32,  twosocks = 1;
 462         unsigned long pfc;
 463         struct clk *c, *p;
 464
 465         if (board == BCSR_WHOAMI_DB1500) {
 466                 c0 = AU1500_GPIO2_INT;
 467                 c1 = AU1500_GPIO5_INT;
 468                 d0 = 0; /* GPIO number, NOT irq! */
 469                 d1 = 3; /* GPIO number, NOT irq! */
 470                 s0 = AU1500_GPIO1_INT;
 471                 s1 = AU1500_GPIO4_INT;
 472         } else if (board == BCSR_WHOAMI_DB1100) {
 473                 c0 = AU1100_GPIO2_INT;
 474                 c1 = AU1100_GPIO5_INT;
 475                 d0 = 0; /* GPIO number, NOT irq! */
 476                 d1 = 3; /* GPIO number, NOT irq! */
 477                 s0 = AU1100_GPIO1_INT;
 478                 s1 = AU1100_GPIO4_INT;
 479
 480                 gpio_request(19, "sd0_cd");
 481                 gpio_request(20, "sd1_cd");
 482                 gpio_direction_input(19);       /* sd0 cd# */
 483                 gpio_direction_input(20);       /* sd1 cd# */
 484
 485                 /* spi_gpio on SSI0 pins */
 486                 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
 487                 pfc |= (1 << 0);        /* SSI0 pins as GPIOs */
 488                 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
 489
 490                 spi_register_board_info(db1100_spi_info,
 491                                         ARRAY_SIZE(db1100_spi_info));
 492
 493                 /* link LCD clock to AUXPLL */
 494                 p = clk_get(NULL, "auxpll_clk");
 495                 c = clk_get(NULL, "lcd_intclk");
 496                 if (!IS_ERR(c) && !IS_ERR(p)) {
 497                         clk_set_parent(c, p);
 498                         clk_set_rate(c, clk_get_rate(p));
 499                 }
 500                 if (!IS_ERR(c))
 501                         clk_put(c);
 502                 if (!IS_ERR(p))
 503                         clk_put(p);
 504
 505                 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
 506                 gpiod_add_lookup_table(&db1100_spi_gpiod_table);
 507                 platform_device_register(&db1100_spi_dev);
 508         } else if (board == BCSR_WHOAMI_DB1000) {
 509                 c0 = AU1000_GPIO2_INT;
 510                 c1 = AU1000_GPIO5_INT;
 511                 d0 = 0; /* GPIO number, NOT irq! */
 512                 d1 = 3; /* GPIO number, NOT irq! */
 513                 s0 = AU1000_GPIO1_INT;
 514                 s1 = AU1000_GPIO4_INT;
 515         } else if ((board == BCSR_WHOAMI_PB1500) ||
 516                    (board == BCSR_WHOAMI_PB1500R2)) {
 517                 c0 = AU1500_GPIO203_INT;
 518                 d0 = 1; /* GPIO number, NOT irq! */
 519                 s0 = AU1500_GPIO202_INT;
 520                 twosocks = 0;
 521                 flashsize = 64;
 522                 /* RTC and daughtercard irqs */
 523                 irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW);
 524                 irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
 525                 /* EPSON S1D13806 0x1b000000
 526                  * SRAM 1MB/2MB   0x1a000000
 527                  * DS1693 RTC     0x0c000000
 528                  */
 529         } else if (board == BCSR_WHOAMI_PB1100) {
 530                 c0 = AU1100_GPIO11_INT;
 531                 d0 = 9; /* GPIO number, NOT irq! */
 532                 s0 = AU1100_GPIO10_INT;
 533                 twosocks = 0;
 534                 flashsize = 64;
 535                 /* pendown, rtc, daughtercard irqs */
 536                 irq_set_irq_type(AU1100_GPIO8_INT, IRQ_TYPE_LEVEL_LOW);
 537                 irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW);
 538                 irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW);
 539                 /* EPSON S1D13806 0x1b000000
 540                  * SRAM 1MB/2MB   0x1a000000
 541                  * DiskOnChip     0x0d000000
 542                  * DS1693 RTC     0x0c000000
 543                  */
 544                 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
 545         } else
 546                 return 0; /* unknown board, no further dev setup to do */
 547
 548         irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW);
 549         irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW);
 550
 551         db1x_register_pcmcia_socket(
 552                 AU1000_PCMCIA_ATTR_PHYS_ADDR,
 553                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
 554                 AU1000_PCMCIA_MEM_PHYS_ADDR,
 555                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
 556                 AU1000_PCMCIA_IO_PHYS_ADDR,
 557                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
 558                 c0, d0, /*s0*/0, 0, 0);
 559
 560         if (twosocks) {
 561                 irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW);
 562                 irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW);
 563
 564                 db1x_register_pcmcia_socket(
 565                         AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
 566                         AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
 567                         AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
 568                         AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
 569                         AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
 570                         AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
 571                         c1, d1, /*s1*/0, 0, 1);
 572         }
 573
 574         platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs));
 575         db1x_register_norflash(flashsize << 20, 4 /* 32bit */, F_SWAPPED);
 576         return 0;
 577 }