arch/mips/alchemy/devboards/db1550.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Alchemy Db1550/Pb1550 board support
   4  *
   5  * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/gpio.h>
  11 #include <linux/i2c.h>
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/mtd/mtd.h>
  16 #include <linux/mtd/rawnand.h>
  17 #include <linux/mtd/partitions.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/spi/flash.h>
  22 #include <asm/bootinfo.h>
  23 #include <asm/mach-au1x00/au1000.h>
  24 #include <asm/mach-au1x00/gpio-au1000.h>
  25 #include <asm/mach-au1x00/au1xxx_eth.h>
  26 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  27 #include <asm/mach-au1x00/au1xxx_psc.h>
  28 #include <asm/mach-au1x00/au1550_spi.h>
  29 #include <asm/mach-au1x00/au1550nd.h>
  30 #include <asm/mach-db1x00/bcsr.h>
  31 #include <prom.h>
  32 #include "platform.h"
  33
  34 static void __init db1550_hw_setup(void)
  35 {
  36         void __iomem *base;
  37         unsigned long v;
  38
  39         /* complete pin setup: assign GPIO16 to PSC0_SYNC1 (SPI cs# line)
  40          * as well as PSC1_SYNC for AC97 on PB1550.
  41          */
  42         v = alchemy_rdsys(AU1000_SYS_PINFUNC);
  43         alchemy_wrsys(v | 1 | SYS_PF_PSC1_S1, AU1000_SYS_PINFUNC);
  44
  45         /* reset the AC97 codec now, the reset time in the psc-ac97 driver
  46          * is apparently too short although it's ridiculous as it is.
  47          */
  48         base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR);
  49         __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE,
  50                      base + PSC_SEL_OFFSET);
  51         __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET);
  52         wmb();
  53         __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET);
  54         wmb();
  55 }
  56
  57 int __init db1550_board_setup(void)
  58 {
  59         unsigned short whoami;
  60
  61         bcsr_init(DB1550_BCSR_PHYS_ADDR,
  62                   DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
  63
  64         whoami = bcsr_read(BCSR_WHOAMI); /* PB1550 hexled offset differs */
  65         switch (BCSR_WHOAMI_BOARD(whoami)) {
  66         case BCSR_WHOAMI_PB1550_SDR:
  67         case BCSR_WHOAMI_PB1550_DDR:
  68                 bcsr_init(PB1550_BCSR_PHYS_ADDR,
  69                           PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
  70         case BCSR_WHOAMI_DB1550:
  71                 break;
  72         default:
  73                 return -ENODEV;
  74         }
  75
  76         pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d  "       \
  77                 "Daughtercard ID %d\n", get_system_type(),
  78                 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
  79
  80         db1550_hw_setup();
  81         return 0;
  82 }
  83
  84 /*****************************************************************************/
  85
  86 static struct mtd_partition db1550_spiflash_parts[] = {
  87         {
  88                 .name   = "spi_flash",
  89                 .offset = 0,
  90                 .size   = MTDPART_SIZ_FULL,
  91         },
  92 };
  93
  94 static struct flash_platform_data db1550_spiflash_data = {
  95         .name           = "s25fl010",
  96         .parts          = db1550_spiflash_parts,
  97         .nr_parts       = ARRAY_SIZE(db1550_spiflash_parts),
  98         .type           = "m25p10",
  99 };
 100
 101 static struct spi_board_info db1550_spi_devs[] __initdata = {
 102         {
 103                 /* TI TMP121AIDBVR temp sensor */
 104                 .modalias       = "tmp121",
 105                 .max_speed_hz   = 2400000,
 106                 .bus_num        = 0,
 107                 .chip_select    = 0,
 108                 .mode           = SPI_MODE_0,
 109         },
 110         {
 111                 /* Spansion S25FL001D0FMA SPI flash */
 112                 .modalias       = "m25p80",
 113                 .max_speed_hz   = 2400000,
 114                 .bus_num        = 0,
 115                 .chip_select    = 1,
 116                 .mode           = SPI_MODE_0,
 117                 .platform_data  = &db1550_spiflash_data,
 118         },
 119 };
 120
 121 static struct i2c_board_info db1550_i2c_devs[] __initdata = {
 122         { I2C_BOARD_INFO("24c04",  0x52),}, /* AT24C04-10 I2C eeprom */
 123         { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */
 124         { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */
 125 };
 126
 127 /**********************************************************************/
 128
 129 static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 130                                  unsigned int ctrl)
 131 {
 132         struct nand_chip *this = mtd_to_nand(mtd);
 133         unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
 134
 135         ioaddr &= 0xffffff00;
 136
 137         if (ctrl & NAND_CLE) {
 138                 ioaddr += MEM_STNAND_CMD;
 139         } else if (ctrl & NAND_ALE) {
 140                 ioaddr += MEM_STNAND_ADDR;
 141         } else {
 142                 /* assume we want to r/w real data  by default */
 143                 ioaddr += MEM_STNAND_DATA;
 144         }
 145         this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
 146         if (cmd != NAND_CMD_NONE) {
 147                 __raw_writeb(cmd, this->IO_ADDR_W);
 148                 wmb();
 149         }
 150 }
 151
 152 static int au1550_nand_device_ready(struct mtd_info *mtd)
 153 {
 154         return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
 155 }
 156
 157 static struct mtd_partition db1550_nand_parts[] = {
 158         {
 159                 .name   = "NAND FS 0",
 160                 .offset = 0,
 161                 .size   = 8 * 1024 * 1024,
 162         },
 163         {
 164                 .name   = "NAND FS 1",
 165                 .offset = MTDPART_OFS_APPEND,
 166                 .size   = MTDPART_SIZ_FULL
 167         },
 168 };
 169
 170 struct platform_nand_data db1550_nand_platdata = {
 171         .chip = {
 172                 .nr_chips       = 1,
 173                 .chip_offset    = 0,
 174                 .nr_partitions  = ARRAY_SIZE(db1550_nand_parts),
 175                 .partitions     = db1550_nand_parts,
 176                 .chip_delay     = 20,
 177         },
 178         .ctrl = {
 179                 .dev_ready      = au1550_nand_device_ready,
 180                 .cmd_ctrl       = au1550_nand_cmd_ctrl,
 181         },
 182 };
 183
 184 static struct resource db1550_nand_res[] = {
 185         [0] = {
 186                 .start  = 0x20000000,
 187                 .end    = 0x200000ff,
 188                 .flags  = IORESOURCE_MEM,
 189         },
 190 };
 191
 192 static struct platform_device db1550_nand_dev = {
 193         .name           = "gen_nand",
 194         .num_resources  = ARRAY_SIZE(db1550_nand_res),
 195         .resource       = db1550_nand_res,
 196         .id             = -1,
 197         .dev            = {
 198                 .platform_data = &db1550_nand_platdata,
 199         }
 200 };
 201
 202 static struct au1550nd_platdata pb1550_nand_pd = {
 203         .parts          = db1550_nand_parts,
 204         .num_parts      = ARRAY_SIZE(db1550_nand_parts),
 205         .devwidth       = 0,    /* x8 NAND default, needs fixing up */
 206 };
 207
 208 static struct platform_device pb1550_nand_dev = {
 209         .name           = "au1550-nand",
 210         .id             = -1,
 211         .resource       = db1550_nand_res,
 212         .num_resources  = ARRAY_SIZE(db1550_nand_res),
 213         .dev            = {
 214                 .platform_data  = &pb1550_nand_pd,
 215         },
 216 };
 217
 218 static void __init pb1550_nand_setup(void)
 219 {
 220         int boot_swapboot = (alchemy_rdsmem(AU1000_MEM_STSTAT) & (0x7 << 1)) |
 221                             ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
 222
 223         gpio_direction_input(206);      /* de-assert NAND CS# */
 224         switch (boot_swapboot) {
 225         case 0: case 2: case 8: case 0xC: case 0xD:
 226                 /* x16 NAND Flash */
 227                 pb1550_nand_pd.devwidth = 1;
 228                 /* fallthrough */
 229         case 1: case 3: case 9: case 0xE: case 0xF:
 230                 /* x8 NAND, already set up */
 231                 platform_device_register(&pb1550_nand_dev);
 232         }
 233 }
 234
 235 /**********************************************************************/
 236
 237 static struct resource au1550_psc0_res[] = {
 238         [0] = {
 239                 .start  = AU1550_PSC0_PHYS_ADDR,
 240                 .end    = AU1550_PSC0_PHYS_ADDR + 0xfff,
 241                 .flags  = IORESOURCE_MEM,
 242         },
 243         [1] = {
 244                 .start  = AU1550_PSC0_INT,
 245                 .end    = AU1550_PSC0_INT,
 246                 .flags  = IORESOURCE_IRQ,
 247         },
 248         [2] = {
 249                 .start  = AU1550_DSCR_CMD0_PSC0_TX,
 250                 .end    = AU1550_DSCR_CMD0_PSC0_TX,
 251                 .flags  = IORESOURCE_DMA,
 252         },
 253         [3] = {
 254                 .start  = AU1550_DSCR_CMD0_PSC0_RX,
 255                 .end    = AU1550_DSCR_CMD0_PSC0_RX,
 256                 .flags  = IORESOURCE_DMA,
 257         },
 258 };
 259
 260 static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
 261 {
 262         if (cs)
 263                 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL);
 264         else
 265                 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0);
 266 }
 267
 268 static struct au1550_spi_info db1550_spi_platdata = {
 269         .mainclk_hz     = 48000000,     /* PSC0 clock: max. 2.4MHz SPI clk */
 270         .num_chipselect = 2,
 271         .activate_cs    = db1550_spi_cs_en,
 272 };
 273
 274 static u64 spi_dmamask = DMA_BIT_MASK(32);
 275
 276 static struct platform_device db1550_spi_dev = {
 277         .dev    = {
 278                 .dma_mask               = &spi_dmamask,
 279                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 280                 .platform_data          = &db1550_spi_platdata,
 281         },
 282         .name           = "au1550-spi",
 283         .id             = 0,    /* bus number */
 284         .num_resources  = ARRAY_SIZE(au1550_psc0_res),
 285         .resource       = au1550_psc0_res,
 286 };
 287
 288 /**********************************************************************/
 289
 290 static struct resource au1550_psc1_res[] = {
 291         [0] = {
 292                 .start  = AU1550_PSC1_PHYS_ADDR,
 293                 .end    = AU1550_PSC1_PHYS_ADDR + 0xfff,
 294                 .flags  = IORESOURCE_MEM,
 295         },
 296         [1] = {
 297                 .start  = AU1550_PSC1_INT,
 298                 .end    = AU1550_PSC1_INT,
 299                 .flags  = IORESOURCE_IRQ,
 300         },
 301         [2] = {
 302                 .start  = AU1550_DSCR_CMD0_PSC1_TX,
 303                 .end    = AU1550_DSCR_CMD0_PSC1_TX,
 304                 .flags  = IORESOURCE_DMA,
 305         },
 306         [3] = {
 307                 .start  = AU1550_DSCR_CMD0_PSC1_RX,
 308                 .end    = AU1550_DSCR_CMD0_PSC1_RX,
 309                 .flags  = IORESOURCE_DMA,
 310         },
 311 };
 312
 313 static struct platform_device db1550_ac97_dev = {
 314         .name           = "au1xpsc_ac97",
 315         .id             = 1,    /* PSC ID */
 316         .num_resources  = ARRAY_SIZE(au1550_psc1_res),
 317         .resource       = au1550_psc1_res,
 318 };
 319
 320
 321 static struct resource au1550_psc2_res[] = {
 322         [0] = {
 323                 .start  = AU1550_PSC2_PHYS_ADDR,
 324                 .end    = AU1550_PSC2_PHYS_ADDR + 0xfff,
 325                 .flags  = IORESOURCE_MEM,
 326         },
 327         [1] = {
 328                 .start  = AU1550_PSC2_INT,
 329                 .end    = AU1550_PSC2_INT,
 330                 .flags  = IORESOURCE_IRQ,
 331         },
 332         [2] = {
 333                 .start  = AU1550_DSCR_CMD0_PSC2_TX,
 334                 .end    = AU1550_DSCR_CMD0_PSC2_TX,
 335                 .flags  = IORESOURCE_DMA,
 336         },
 337         [3] = {
 338                 .start  = AU1550_DSCR_CMD0_PSC2_RX,
 339                 .end    = AU1550_DSCR_CMD0_PSC2_RX,
 340                 .flags  = IORESOURCE_DMA,
 341         },
 342 };
 343
 344 static struct platform_device db1550_i2c_dev = {
 345         .name           = "au1xpsc_smbus",
 346         .id             = 0,    /* bus number */
 347         .num_resources  = ARRAY_SIZE(au1550_psc2_res),
 348         .resource       = au1550_psc2_res,
 349 };
 350
 351 /**********************************************************************/
 352
 353 static struct resource au1550_psc3_res[] = {
 354         [0] = {
 355                 .start  = AU1550_PSC3_PHYS_ADDR,
 356                 .end    = AU1550_PSC3_PHYS_ADDR + 0xfff,
 357                 .flags  = IORESOURCE_MEM,
 358         },
 359         [1] = {
 360                 .start  = AU1550_PSC3_INT,
 361                 .end    = AU1550_PSC3_INT,
 362                 .flags  = IORESOURCE_IRQ,
 363         },
 364         [2] = {
 365                 .start  = AU1550_DSCR_CMD0_PSC3_TX,
 366                 .end    = AU1550_DSCR_CMD0_PSC3_TX,
 367                 .flags  = IORESOURCE_DMA,
 368         },
 369         [3] = {
 370                 .start  = AU1550_DSCR_CMD0_PSC3_RX,
 371                 .end    = AU1550_DSCR_CMD0_PSC3_RX,
 372                 .flags  = IORESOURCE_DMA,
 373         },
 374 };
 375
 376 static struct platform_device db1550_i2s_dev = {
 377         .name           = "au1xpsc_i2s",
 378         .id             = 3,    /* PSC ID */
 379         .num_resources  = ARRAY_SIZE(au1550_psc3_res),
 380         .resource       = au1550_psc3_res,
 381 };
 382
 383 /**********************************************************************/
 384
 385 static struct platform_device db1550_stac_dev = {
 386         .name           = "ac97-codec",
 387         .id             = 1,    /* on PSC1 */
 388 };
 389
 390 static struct platform_device db1550_ac97dma_dev = {
 391         .name           = "au1xpsc-pcm",
 392         .id             = 1,    /* on PSC3 */
 393 };
 394
 395 static struct platform_device db1550_i2sdma_dev = {
 396         .name           = "au1xpsc-pcm",
 397         .id             = 3,    /* on PSC3 */
 398 };
 399
 400 static struct platform_device db1550_sndac97_dev = {
 401         .name           = "db1550-ac97",
 402 };
 403
 404 static struct platform_device db1550_sndi2s_dev = {
 405         .name           = "db1550-i2s",
 406 };
 407
 408 /**********************************************************************/
 409
 410 static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
 411 {
 412         if ((slot < 11) || (slot > 13) || pin == 0)
 413                 return -1;
 414         if (slot == 11)
 415                 return (pin == 1) ? AU1550_PCI_INTC : 0xff;
 416         if (slot == 12) {
 417                 switch (pin) {
 418                 case 1: return AU1550_PCI_INTB;
 419                 case 2: return AU1550_PCI_INTC;
 420                 case 3: return AU1550_PCI_INTD;
 421                 case 4: return AU1550_PCI_INTA;
 422                 }
 423         }
 424         if (slot == 13) {
 425                 switch (pin) {
 426                 case 1: return AU1550_PCI_INTA;
 427                 case 2: return AU1550_PCI_INTB;
 428                 case 3: return AU1550_PCI_INTC;
 429                 case 4: return AU1550_PCI_INTD;
 430                 }
 431         }
 432         return -1;
 433 }
 434
 435 static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
 436 {
 437         if ((slot < 12) || (slot > 13) || pin == 0)
 438                 return -1;
 439         if (slot == 12) {
 440                 switch (pin) {
 441                 case 1: return AU1500_PCI_INTB;
 442                 case 2: return AU1500_PCI_INTC;
 443                 case 3: return AU1500_PCI_INTD;
 444                 case 4: return AU1500_PCI_INTA;
 445                 }
 446         }
 447         if (slot == 13) {
 448                 switch (pin) {
 449                 case 1: return AU1500_PCI_INTA;
 450                 case 2: return AU1500_PCI_INTB;
 451                 case 3: return AU1500_PCI_INTC;
 452                 case 4: return AU1500_PCI_INTD;
 453                 }
 454         }
 455         return -1;
 456 }
 457
 458 static struct resource alchemy_pci_host_res[] = {
 459         [0] = {
 460                 .start  = AU1500_PCI_PHYS_ADDR,
 461                 .end    = AU1500_PCI_PHYS_ADDR + 0xfff,
 462                 .flags  = IORESOURCE_MEM,
 463         },
 464 };
 465
 466 static struct alchemy_pci_platdata db1550_pci_pd = {
 467         .board_map_irq  = db1550_map_pci_irq,
 468 };
 469
 470 static struct platform_device db1550_pci_host_dev = {
 471         .dev.platform_data = &db1550_pci_pd,
 472         .name           = "alchemy-pci",
 473         .id             = 0,
 474         .num_resources  = ARRAY_SIZE(alchemy_pci_host_res),
 475         .resource       = alchemy_pci_host_res,
 476 };
 477
 478 /**********************************************************************/
 479
 480 static struct platform_device *db1550_devs[] __initdata = {
 481         &db1550_i2c_dev,
 482         &db1550_ac97_dev,
 483         &db1550_spi_dev,
 484         &db1550_i2s_dev,
 485         &db1550_stac_dev,
 486         &db1550_ac97dma_dev,
 487         &db1550_i2sdma_dev,
 488         &db1550_sndac97_dev,
 489         &db1550_sndi2s_dev,
 490 };
 491
 492 /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
 493 int __init db1550_pci_setup(int id)
 494 {
 495         if (id)
 496                 db1550_pci_pd.board_map_irq = pb1550_map_pci_irq;
 497         return platform_device_register(&db1550_pci_host_dev);
 498 }
 499
 500 static void __init db1550_devices(void)
 501 {
 502         alchemy_gpio_direction_output(203, 0);  /* red led on */
 503
 504         irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH);  /* CD0# */
 505         irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH);  /* CD1# */
 506         irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW);  /* CARD0# */
 507         irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW);  /* CARD1# */
 508         irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
 509         irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
 510
 511         db1x_register_pcmcia_socket(
 512                 AU1000_PCMCIA_ATTR_PHYS_ADDR,
 513                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
 514                 AU1000_PCMCIA_MEM_PHYS_ADDR,
 515                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
 516                 AU1000_PCMCIA_IO_PHYS_ADDR,
 517                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
 518                 AU1550_GPIO3_INT, 0,
 519                 /*AU1550_GPIO21_INT*/0, 0, 0);
 520
 521         db1x_register_pcmcia_socket(
 522                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
 523                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
 524                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
 525                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
 526                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
 527                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
 528                 AU1550_GPIO5_INT, 1,
 529                 /*AU1550_GPIO22_INT*/0, 0, 1);
 530
 531         platform_device_register(&db1550_nand_dev);
 532
 533         alchemy_gpio_direction_output(202, 0);  /* green led on */
 534 }
 535
 536 static void __init pb1550_devices(void)
 537 {
 538         irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_LEVEL_LOW);
 539         irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_LEVEL_LOW);
 540         irq_set_irq_type(AU1550_GPIO201_205_INT, IRQ_TYPE_LEVEL_HIGH);
 541
 542         /* enable both PCMCIA card irqs in the shared line */
 543         alchemy_gpio2_enable_int(201);  /* socket 0 card irq */
 544         alchemy_gpio2_enable_int(202);  /* socket 1 card irq */
 545
 546         /* Pb1550, like all others, also has statuschange irqs; however they're
 547         * wired up on one of the Au1550's shared GPIO201_205 line, which also
 548         * services the PCMCIA card interrupts.  So we ignore statuschange and
 549         * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
 550         * drivers are used to shared irqs and b) statuschange isn't really use-
 551         * ful anyway.
 552         */
 553         db1x_register_pcmcia_socket(
 554                 AU1000_PCMCIA_ATTR_PHYS_ADDR,
 555                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
 556                 AU1000_PCMCIA_MEM_PHYS_ADDR,
 557                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
 558                 AU1000_PCMCIA_IO_PHYS_ADDR,
 559                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
 560                 AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0);
 561
 562         db1x_register_pcmcia_socket(
 563                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
 564                 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
 565                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x008000000,
 566                 AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x008400000 - 1,
 567                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x008000000,
 568                 AU1000_PCMCIA_IO_PHYS_ADDR   + 0x008010000 - 1,
 569                 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
 570
 571         pb1550_nand_setup();
 572 }
 573
 574 int __init db1550_dev_setup(void)
 575 {
 576         int swapped, id;
 577         struct clk *c;
 578
 579         id = (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) != BCSR_WHOAMI_DB1550);
 580
 581         i2c_register_board_info(0, db1550_i2c_devs,
 582                                 ARRAY_SIZE(db1550_i2c_devs));
 583         spi_register_board_info(db1550_spi_devs,
 584                                 ARRAY_SIZE(db1550_i2c_devs));
 585
 586         c = clk_get(NULL, "psc0_intclk");
 587         if (!IS_ERR(c)) {
 588                 clk_set_rate(c, 50000000);
 589                 clk_prepare_enable(c);
 590                 clk_put(c);
 591         }
 592         c = clk_get(NULL, "psc2_intclk");
 593         if (!IS_ERR(c)) {
 594                 clk_set_rate(c, db1550_spi_platdata.mainclk_hz);
 595                 clk_prepare_enable(c);
 596                 clk_put(c);
 597         }
 598
 599         /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */
 600         __raw_writel(PSC_SEL_CLK_SERCLK,
 601             (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
 602         wmb();
 603         __raw_writel(PSC_SEL_CLK_SERCLK,
 604             (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
 605         wmb();
 606         /* SPI/I2C use internally supplied 50MHz source */
 607         __raw_writel(PSC_SEL_CLK_INTCLK,
 608             (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET);
 609         wmb();
 610         __raw_writel(PSC_SEL_CLK_INTCLK,
 611             (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
 612         wmb();
 613
 614         id ? pb1550_devices() : db1550_devices();
 615
 616         swapped = bcsr_read(BCSR_STATUS) &
 617                (id ? BCSR_STATUS_PB1550_SWAPBOOT : BCSR_STATUS_DB1000_SWAPBOOT);
 618         db1x_register_norflash(128 << 20, 4, swapped);
 619
 620         return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs));
 621 }