arch/mips/ath79/clock.c

   1 /*
   2  *  Atheros AR71XX/AR724X/AR913X common routines
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/err.h>
  18 #include <linux/clk.h>
  19 #include <linux/clkdev.h>
  20 #include <linux/clk-provider.h>
  21
  22 #include <asm/div64.h>
  23
  24 #include <asm/mach-ath79/ath79.h>
  25 #include <asm/mach-ath79/ar71xx_regs.h>
  26 #include "common.h"
  27
  28 #define AR71XX_BASE_FREQ        40000000
  29 #define AR724X_BASE_FREQ        5000000
  30 #define AR913X_BASE_FREQ        5000000
  31
  32 static struct clk *clks[3];
  33 static struct clk_onecell_data clk_data = {
  34         .clks = clks,
  35         .clk_num = ARRAY_SIZE(clks),
  36 };
  37
  38 static struct clk *__init ath79_add_sys_clkdev(
  39         const char *id, unsigned long rate)
  40 {
  41         struct clk *clk;
  42         int err;
  43
  44         clk = clk_register_fixed_rate(NULL, id, NULL, CLK_IS_ROOT, rate);
  45         if (!clk)
  46                 panic("failed to allocate %s clock structure", id);
  47
  48         err = clk_register_clkdev(clk, id, NULL);
  49         if (err)
  50                 panic("unable to register %s clock device", id);
  51
  52         return clk;
  53 }
  54
  55 static void __init ar71xx_clocks_init(void)
  56 {
  57         unsigned long ref_rate;
  58         unsigned long cpu_rate;
  59         unsigned long ddr_rate;
  60         unsigned long ahb_rate;
  61         u32 pll;
  62         u32 freq;
  63         u32 div;
  64
  65         ref_rate = AR71XX_BASE_FREQ;
  66
  67         pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
  68
  69         div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
  70         freq = div * ref_rate;
  71
  72         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
  73         cpu_rate = freq / div;
  74
  75         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
  76         ddr_rate = freq / div;
  77
  78         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
  79         ahb_rate = cpu_rate / div;
  80
  81         ath79_add_sys_clkdev("ref", ref_rate);
  82         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
  83         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
  84         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
  85
  86         clk_add_alias("wdt", NULL, "ahb", NULL);
  87         clk_add_alias("uart", NULL, "ahb", NULL);
  88 }
  89
  90 static void __init ar724x_clocks_init(void)
  91 {
  92         unsigned long ref_rate;
  93         unsigned long cpu_rate;
  94         unsigned long ddr_rate;
  95         unsigned long ahb_rate;
  96         u32 pll;
  97         u32 freq;
  98         u32 div;
  99
 100         ref_rate = AR724X_BASE_FREQ;
 101         pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
 102
 103         div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
 104         freq = div * ref_rate;
 105
 106         div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
 107         freq *= div;
 108
 109         cpu_rate = freq;
 110
 111         div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
 112         ddr_rate = freq / div;
 113
 114         div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
 115         ahb_rate = cpu_rate / div;
 116
 117         ath79_add_sys_clkdev("ref", ref_rate);
 118         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
 119         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
 120         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
 121
 122         clk_add_alias("wdt", NULL, "ahb", NULL);
 123         clk_add_alias("uart", NULL, "ahb", NULL);
 124 }
 125
 126 static void __init ar913x_clocks_init(void)
 127 {
 128         unsigned long ref_rate;
 129         unsigned long cpu_rate;
 130         unsigned long ddr_rate;
 131         unsigned long ahb_rate;
 132         u32 pll;
 133         u32 freq;
 134         u32 div;
 135
 136         ref_rate = AR913X_BASE_FREQ;
 137         pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
 138
 139         div = ((pll >> AR913X_PLL_FB_SHIFT) & AR913X_PLL_FB_MASK);
 140         freq = div * ref_rate;
 141
 142         cpu_rate = freq;
 143
 144         div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;
 145         ddr_rate = freq / div;
 146
 147         div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
 148         ahb_rate = cpu_rate / div;
 149
 150         ath79_add_sys_clkdev("ref", ref_rate);
 151         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
 152         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
 153         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
 154
 155         clk_add_alias("wdt", NULL, "ahb", NULL);
 156         clk_add_alias("uart", NULL, "ahb", NULL);
 157 }
 158
 159 static void __init ar933x_clocks_init(void)
 160 {
 161         unsigned long ref_rate;
 162         unsigned long cpu_rate;
 163         unsigned long ddr_rate;
 164         unsigned long ahb_rate;
 165         u32 clock_ctrl;
 166         u32 cpu_config;
 167         u32 freq;
 168         u32 t;
 169
 170         t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
 171         if (t & AR933X_BOOTSTRAP_REF_CLK_40)
 172                 ref_rate = (40 * 1000 * 1000);
 173         else
 174                 ref_rate = (25 * 1000 * 1000);
 175
 176         clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
 177         if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
 178                 cpu_rate = ref_rate;
 179                 ahb_rate = ref_rate;
 180                 ddr_rate = ref_rate;
 181         } else {
 182                 cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
 183
 184                 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
 185                     AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
 186                 freq = ref_rate / t;
 187
 188                 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
 189                     AR933X_PLL_CPU_CONFIG_NINT_MASK;
 190                 freq *= t;
 191
 192                 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 193                     AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
 194                 if (t == 0)
 195                         t = 1;
 196
 197                 freq >>= t;
 198
 199                 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
 200                      AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
 201                 cpu_rate = freq / t;
 202
 203                 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
 204                       AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
 205                 ddr_rate = freq / t;
 206
 207                 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
 208                      AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
 209                 ahb_rate = freq / t;
 210         }
 211
 212         ath79_add_sys_clkdev("ref", ref_rate);
 213         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
 214         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
 215         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
 216
 217         clk_add_alias("wdt", NULL, "ahb", NULL);
 218         clk_add_alias("uart", NULL, "ref", NULL);
 219 }
 220
 221 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
 222                                       u32 frac, u32 out_div)
 223 {
 224         u64 t;
 225         u32 ret;
 226
 227         t = ref;
 228         t *= nint;
 229         do_div(t, ref_div);
 230         ret = t;
 231
 232         t = ref;
 233         t *= nfrac;
 234         do_div(t, ref_div * frac);
 235         ret += t;
 236
 237         ret /= (1 << out_div);
 238         return ret;
 239 }
 240
 241 static void __init ar934x_clocks_init(void)
 242 {
 243         unsigned long ref_rate;
 244         unsigned long cpu_rate;
 245         unsigned long ddr_rate;
 246         unsigned long ahb_rate;
 247         u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
 248         u32 cpu_pll, ddr_pll;
 249         u32 bootstrap;
 250         void __iomem *dpll_base;
 251
 252         dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
 253
 254         bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
 255         if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
 256                 ref_rate = 40 * 1000 * 1000;
 257         else
 258                 ref_rate = 25 * 1000 * 1000;
 259
 260         pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
 261         if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
 262                 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
 263                           AR934X_SRIF_DPLL2_OUTDIV_MASK;
 264                 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
 265                 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
 266                        AR934X_SRIF_DPLL1_NINT_MASK;
 267                 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
 268                 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
 269                           AR934X_SRIF_DPLL1_REFDIV_MASK;
 270                 frac = 1 << 18;
 271         } else {
 272                 pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
 273                 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 274                         AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
 275                 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
 276                           AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
 277                 nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
 278                        AR934X_PLL_CPU_CONFIG_NINT_MASK;
 279                 nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
 280                         AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
 281                 frac = 1 << 6;
 282         }
 283
 284         cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
 285                                       nfrac, frac, out_div);
 286
 287         pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
 288         if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
 289                 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
 290                           AR934X_SRIF_DPLL2_OUTDIV_MASK;
 291                 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
 292                 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
 293                        AR934X_SRIF_DPLL1_NINT_MASK;
 294                 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
 295                 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
 296                           AR934X_SRIF_DPLL1_REFDIV_MASK;
 297                 frac = 1 << 18;
 298         } else {
 299                 pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
 300                 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
 301                           AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
 302                 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
 303                            AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
 304                 nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
 305                        AR934X_PLL_DDR_CONFIG_NINT_MASK;
 306                 nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
 307                         AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
 308                 frac = 1 << 10;
 309         }
 310
 311         ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
 312                                       nfrac, frac, out_div);
 313
 314         clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
 315
 316         postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
 317                   AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
 318
 319         if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
 320                 cpu_rate = ref_rate;
 321         else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
 322                 cpu_rate = cpu_pll / (postdiv + 1);
 323         else
 324                 cpu_rate = ddr_pll / (postdiv + 1);
 325
 326         postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
 327                   AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
 328
 329         if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
 330                 ddr_rate = ref_rate;
 331         else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
 332                 ddr_rate = ddr_pll / (postdiv + 1);
 333         else
 334                 ddr_rate = cpu_pll / (postdiv + 1);
 335
 336         postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 337                   AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
 338
 339         if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
 340                 ahb_rate = ref_rate;
 341         else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 342                 ahb_rate = ddr_pll / (postdiv + 1);
 343         else
 344                 ahb_rate = cpu_pll / (postdiv + 1);
 345
 346         ath79_add_sys_clkdev("ref", ref_rate);
 347         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
 348         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
 349         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
 350
 351         clk_add_alias("wdt", NULL, "ref", NULL);
 352         clk_add_alias("uart", NULL, "ref", NULL);
 353
 354         iounmap(dpll_base);
 355 }
 356
 357 static void __init qca955x_clocks_init(void)
 358 {
 359         unsigned long ref_rate;
 360         unsigned long cpu_rate;
 361         unsigned long ddr_rate;
 362         unsigned long ahb_rate;
 363         u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
 364         u32 cpu_pll, ddr_pll;
 365         u32 bootstrap;
 366
 367         bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
 368         if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
 369                 ref_rate = 40 * 1000 * 1000;
 370         else
 371                 ref_rate = 25 * 1000 * 1000;
 372
 373         pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
 374         out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 375                   QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
 376         ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
 377                   QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
 378         nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
 379                QCA955X_PLL_CPU_CONFIG_NINT_MASK;
 380         frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
 381                QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
 382
 383         cpu_pll = nint * ref_rate / ref_div;
 384         cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
 385         cpu_pll /= (1 << out_div);
 386
 387         pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
 388         out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
 389                   QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
 390         ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
 391                   QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
 392         nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
 393                QCA955X_PLL_DDR_CONFIG_NINT_MASK;
 394         frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
 395                QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
 396
 397         ddr_pll = nint * ref_rate / ref_div;
 398         ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
 399         ddr_pll /= (1 << out_div);
 400
 401         clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
 402
 403         postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
 404                   QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
 405
 406         if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
 407                 cpu_rate = ref_rate;
 408         else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
 409                 cpu_rate = ddr_pll / (postdiv + 1);
 410         else
 411                 cpu_rate = cpu_pll / (postdiv + 1);
 412
 413         postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
 414                   QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
 415
 416         if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
 417                 ddr_rate = ref_rate;
 418         else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
 419                 ddr_rate = cpu_pll / (postdiv + 1);
 420         else
 421                 ddr_rate = ddr_pll / (postdiv + 1);
 422
 423         postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 424                   QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
 425
 426         if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
 427                 ahb_rate = ref_rate;
 428         else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 429                 ahb_rate = ddr_pll / (postdiv + 1);
 430         else
 431                 ahb_rate = cpu_pll / (postdiv + 1);
 432
 433         ath79_add_sys_clkdev("ref", ref_rate);
 434         clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
 435         clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
 436         clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
 437
 438         clk_add_alias("wdt", NULL, "ref", NULL);
 439         clk_add_alias("uart", NULL, "ref", NULL);
 440 }
 441
 442 void __init ath79_clocks_init(void)
 443 {
 444         if (soc_is_ar71xx())
 445                 ar71xx_clocks_init();
 446         else if (soc_is_ar724x())
 447                 ar724x_clocks_init();
 448         else if (soc_is_ar913x())
 449                 ar913x_clocks_init();
 450         else if (soc_is_ar933x())
 451                 ar933x_clocks_init();
 452         else if (soc_is_ar934x())
 453                 ar934x_clocks_init();
 454         else if (soc_is_qca955x())
 455                 qca955x_clocks_init();
 456         else
 457                 BUG();
 458
 459         of_clk_init(NULL);
 460 }
 461
 462 unsigned long __init
 463 ath79_get_sys_clk_rate(const char *id)
 464 {
 465         struct clk *clk;
 466         unsigned long rate;
 467
 468         clk = clk_get(NULL, id);
 469         if (IS_ERR(clk))
 470                 panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
 471
 472         rate = clk_get_rate(clk);
 473         clk_put(clk);
 474
 475         return rate;
 476 }
 477
 478 #ifdef CONFIG_OF
 479 static void __init ath79_clocks_init_dt(struct device_node *np)
 480 {
 481         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 482 }
 483
 484 CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
 485 CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
 486 CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt);
 487 CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt);
 488 CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
 489 CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
 490 #endif