2 * Atheros AR71XX/AR724X/AR913X specific setup
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
18 #include <linux/memblock.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/clk-provider.h>
22 #include <linux/of_fdt.h>
23 #include <linux/irqchip.h>
25 #include <asm/bootinfo.h>
27 #include <asm/time.h> /* for mips_hpt_frequency */
28 #include <asm/reboot.h> /* for _machine_{restart,halt} */
29 #include <asm/mips_machine.h>
31 #include <asm/fw/fw.h>
33 #include <asm/mach-ath79/ath79.h>
34 #include <asm/mach-ath79/ar71xx_regs.h>
37 #define ATH79_SYS_TYPE_LEN 64
39 static char ath79_sys_type
[ATH79_SYS_TYPE_LEN
];
41 static void ath79_restart(char *command
)
44 ath79_device_reset_set(AR71XX_RESET_FULL_CHIP
);
50 static void ath79_halt(void)
56 static void __init
ath79_detect_sys_type(void)
65 id
= ath79_reset_rr(AR71XX_RESET_REG_REV_ID
);
66 major
= id
& REV_ID_MAJOR_MASK
;
69 case REV_ID_MAJOR_AR71XX
:
70 minor
= id
& AR71XX_REV_ID_MINOR_MASK
;
71 rev
= id
>> AR71XX_REV_ID_REVISION_SHIFT
;
72 rev
&= AR71XX_REV_ID_REVISION_MASK
;
74 case AR71XX_REV_ID_MINOR_AR7130
:
75 ath79_soc
= ATH79_SOC_AR7130
;
79 case AR71XX_REV_ID_MINOR_AR7141
:
80 ath79_soc
= ATH79_SOC_AR7141
;
84 case AR71XX_REV_ID_MINOR_AR7161
:
85 ath79_soc
= ATH79_SOC_AR7161
;
91 case REV_ID_MAJOR_AR7240
:
92 ath79_soc
= ATH79_SOC_AR7240
;
94 rev
= id
& AR724X_REV_ID_REVISION_MASK
;
97 case REV_ID_MAJOR_AR7241
:
98 ath79_soc
= ATH79_SOC_AR7241
;
100 rev
= id
& AR724X_REV_ID_REVISION_MASK
;
103 case REV_ID_MAJOR_AR7242
:
104 ath79_soc
= ATH79_SOC_AR7242
;
106 rev
= id
& AR724X_REV_ID_REVISION_MASK
;
109 case REV_ID_MAJOR_AR913X
:
110 minor
= id
& AR913X_REV_ID_MINOR_MASK
;
111 rev
= id
>> AR913X_REV_ID_REVISION_SHIFT
;
112 rev
&= AR913X_REV_ID_REVISION_MASK
;
114 case AR913X_REV_ID_MINOR_AR9130
:
115 ath79_soc
= ATH79_SOC_AR9130
;
119 case AR913X_REV_ID_MINOR_AR9132
:
120 ath79_soc
= ATH79_SOC_AR9132
;
126 case REV_ID_MAJOR_AR9330
:
127 ath79_soc
= ATH79_SOC_AR9330
;
129 rev
= id
& AR933X_REV_ID_REVISION_MASK
;
132 case REV_ID_MAJOR_AR9331
:
133 ath79_soc
= ATH79_SOC_AR9331
;
135 rev
= id
& AR933X_REV_ID_REVISION_MASK
;
138 case REV_ID_MAJOR_AR9341
:
139 ath79_soc
= ATH79_SOC_AR9341
;
141 rev
= id
& AR934X_REV_ID_REVISION_MASK
;
144 case REV_ID_MAJOR_AR9342
:
145 ath79_soc
= ATH79_SOC_AR9342
;
147 rev
= id
& AR934X_REV_ID_REVISION_MASK
;
150 case REV_ID_MAJOR_AR9344
:
151 ath79_soc
= ATH79_SOC_AR9344
;
153 rev
= id
& AR934X_REV_ID_REVISION_MASK
;
156 case REV_ID_MAJOR_QCA9533_V2
:
161 case REV_ID_MAJOR_QCA9533
:
162 ath79_soc
= ATH79_SOC_QCA9533
;
164 rev
= id
& QCA953X_REV_ID_REVISION_MASK
;
167 case REV_ID_MAJOR_QCA9556
:
168 ath79_soc
= ATH79_SOC_QCA9556
;
170 rev
= id
& QCA955X_REV_ID_REVISION_MASK
;
173 case REV_ID_MAJOR_QCA9558
:
174 ath79_soc
= ATH79_SOC_QCA9558
;
176 rev
= id
& QCA955X_REV_ID_REVISION_MASK
;
179 case REV_ID_MAJOR_QCA956X
:
180 ath79_soc
= ATH79_SOC_QCA956X
;
182 rev
= id
& QCA956X_REV_ID_REVISION_MASK
;
185 case REV_ID_MAJOR_TP9343
:
186 ath79_soc
= ATH79_SOC_TP9343
;
188 rev
= id
& QCA956X_REV_ID_REVISION_MASK
;
192 panic("ath79: unknown SoC, id:0x%08x", id
);
198 if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
199 sprintf(ath79_sys_type
, "Qualcomm Atheros QCA%s ver %u rev %u",
201 else if (soc_is_tp9343())
202 sprintf(ath79_sys_type
, "Qualcomm Atheros TP%s rev %u",
205 sprintf(ath79_sys_type
, "Atheros AR%s rev %u", chip
, rev
);
206 pr_info("SoC: %s\n", ath79_sys_type
);
209 const char *get_system_type(void)
211 return ath79_sys_type
;
214 unsigned int get_c0_compare_int(void)
216 return CP0_LEGACY_COMPARE_IRQ
;
219 void __init
plat_mem_setup(void)
221 unsigned long fdt_start
;
223 set_io_port_base(KSEG1
);
225 /* Get the position of the FDT passed by the bootloader */
226 fdt_start
= fw_getenvl("fdt_start");
228 __dt_setup_arch((void *)KSEG0ADDR(fdt_start
));
229 else if (fw_passed_dtb
)
230 __dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb
));
232 ath79_reset_base
= ioremap_nocache(AR71XX_RESET_BASE
,
234 ath79_pll_base
= ioremap_nocache(AR71XX_PLL_BASE
,
236 ath79_detect_sys_type();
237 ath79_ddr_ctrl_init();
239 detect_memory_region(0, ATH79_MEM_SIZE_MIN
, ATH79_MEM_SIZE_MAX
);
241 _machine_restart
= ath79_restart
;
242 _machine_halt
= ath79_halt
;
243 pm_power_off
= ath79_halt
;
246 void __init
plat_time_init(void)
248 struct device_node
*np
;
250 unsigned long cpu_clk_rate
;
254 np
= of_get_cpu_node(0, NULL
);
256 pr_err("Failed to get CPU node\n");
260 clk
= of_clk_get(np
, 0);
262 pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk
));
266 cpu_clk_rate
= clk_get_rate(clk
);
268 pr_info("CPU clock: %lu.%03lu MHz\n",
269 cpu_clk_rate
/ 1000000, (cpu_clk_rate
/ 1000) % 1000);
271 mips_hpt_frequency
= cpu_clk_rate
/ 2;
276 void __init
arch_init_irq(void)
281 void __init
device_tree_init(void)
283 unflatten_and_copy_device_tree();