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Merge git://git.infradead.org/~dwmw2/cafe-2.6
[mirror_ubuntu-zesty-kernel.git] / arch / mips / au1000 / common / irq.c
1 /*
2 * BRIEF MODULE DESCRIPTION
3 * Au1000 interrupt routines.
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/irq.h>
32 #include <linux/kernel_stat.h>
33 #include <linux/module.h>
34 #include <linux/signal.h>
35 #include <linux/sched.h>
36 #include <linux/types.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/timex.h>
40 #include <linux/slab.h>
41 #include <linux/random.h>
42 #include <linux/delay.h>
43 #include <linux/bitops.h>
44
45 #include <asm/bootinfo.h>
46 #include <asm/io.h>
47 #include <asm/mipsregs.h>
48 #include <asm/system.h>
49 #include <asm/mach-au1x00/au1000.h>
50 #ifdef CONFIG_MIPS_PB1000
51 #include <asm/mach-pb1x00/pb1000.h>
52 #endif
53
54 #undef DEBUG_IRQ
55 #ifdef DEBUG_IRQ
56 /* note: prints function name for you */
57 #define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
58 #else
59 #define DPRINTK(fmt, args...)
60 #endif
61
62 #define EXT_INTC0_REQ0 2 /* IP 2 */
63 #define EXT_INTC0_REQ1 3 /* IP 3 */
64 #define EXT_INTC1_REQ0 4 /* IP 4 */
65 #define EXT_INTC1_REQ1 5 /* IP 5 */
66 #define MIPS_TIMER_IP 7 /* IP 7 */
67
68 extern void set_debug_traps(void);
69 extern irq_cpustat_t irq_stat [NR_CPUS];
70 extern void mips_timer_interrupt(void);
71
72 static void setup_local_irq(unsigned int irq, int type, int int_req);
73 static unsigned int startup_irq(unsigned int irq);
74 static void end_irq(unsigned int irq_nr);
75 static inline void mask_and_ack_level_irq(unsigned int irq_nr);
76 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
77 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr);
78 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr);
79 inline void local_enable_irq(unsigned int irq_nr);
80 inline void local_disable_irq(unsigned int irq_nr);
81
82 void (*board_init_irq)(void);
83
84 static DEFINE_SPINLOCK(irq_lock);
85
86
87 static unsigned int startup_irq(unsigned int irq_nr)
88 {
89 local_enable_irq(irq_nr);
90 return 0;
91 }
92
93
94 static void shutdown_irq(unsigned int irq_nr)
95 {
96 local_disable_irq(irq_nr);
97 return;
98 }
99
100
101 inline void local_enable_irq(unsigned int irq_nr)
102 {
103 if (irq_nr > AU1000_LAST_INTC0_INT) {
104 au_writel(1<<(irq_nr-32), IC1_MASKSET);
105 au_writel(1<<(irq_nr-32), IC1_WAKESET);
106 }
107 else {
108 au_writel(1<<irq_nr, IC0_MASKSET);
109 au_writel(1<<irq_nr, IC0_WAKESET);
110 }
111 au_sync();
112 }
113
114
115 inline void local_disable_irq(unsigned int irq_nr)
116 {
117 if (irq_nr > AU1000_LAST_INTC0_INT) {
118 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
119 au_writel(1<<(irq_nr-32), IC1_WAKECLR);
120 }
121 else {
122 au_writel(1<<irq_nr, IC0_MASKCLR);
123 au_writel(1<<irq_nr, IC0_WAKECLR);
124 }
125 au_sync();
126 }
127
128
129 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
130 {
131 if (irq_nr > AU1000_LAST_INTC0_INT) {
132 au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
133 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
134 }
135 else {
136 au_writel(1<<irq_nr, IC0_RISINGCLR);
137 au_writel(1<<irq_nr, IC0_MASKCLR);
138 }
139 au_sync();
140 }
141
142
143 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
144 {
145 if (irq_nr > AU1000_LAST_INTC0_INT) {
146 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
147 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
148 }
149 else {
150 au_writel(1<<irq_nr, IC0_FALLINGCLR);
151 au_writel(1<<irq_nr, IC0_MASKCLR);
152 }
153 au_sync();
154 }
155
156
157 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
158 {
159 /* This may assume that we don't get interrupts from
160 * both edges at once, or if we do, that we don't care.
161 */
162 if (irq_nr > AU1000_LAST_INTC0_INT) {
163 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
164 au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
165 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
166 }
167 else {
168 au_writel(1<<irq_nr, IC0_FALLINGCLR);
169 au_writel(1<<irq_nr, IC0_RISINGCLR);
170 au_writel(1<<irq_nr, IC0_MASKCLR);
171 }
172 au_sync();
173 }
174
175
176 static inline void mask_and_ack_level_irq(unsigned int irq_nr)
177 {
178
179 local_disable_irq(irq_nr);
180 au_sync();
181 #if defined(CONFIG_MIPS_PB1000)
182 if (irq_nr == AU1000_GPIO_15) {
183 au_writel(0x8000, PB1000_MDR); /* ack int */
184 au_sync();
185 }
186 #endif
187 return;
188 }
189
190
191 static void end_irq(unsigned int irq_nr)
192 {
193 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
194 local_enable_irq(irq_nr);
195 }
196 #if defined(CONFIG_MIPS_PB1000)
197 if (irq_nr == AU1000_GPIO_15) {
198 au_writel(0x4000, PB1000_MDR); /* enable int */
199 au_sync();
200 }
201 #endif
202 }
203
204 unsigned long save_local_and_disable(int controller)
205 {
206 int i;
207 unsigned long flags, mask;
208
209 spin_lock_irqsave(&irq_lock, flags);
210 if (controller) {
211 mask = au_readl(IC1_MASKSET);
212 for (i=32; i<64; i++) {
213 local_disable_irq(i);
214 }
215 }
216 else {
217 mask = au_readl(IC0_MASKSET);
218 for (i=0; i<32; i++) {
219 local_disable_irq(i);
220 }
221 }
222 spin_unlock_irqrestore(&irq_lock, flags);
223
224 return mask;
225 }
226
227 void restore_local_and_enable(int controller, unsigned long mask)
228 {
229 int i;
230 unsigned long flags, new_mask;
231
232 spin_lock_irqsave(&irq_lock, flags);
233 for (i=0; i<32; i++) {
234 if (mask & (1<<i)) {
235 if (controller)
236 local_enable_irq(i+32);
237 else
238 local_enable_irq(i);
239 }
240 }
241 if (controller)
242 new_mask = au_readl(IC1_MASKSET);
243 else
244 new_mask = au_readl(IC0_MASKSET);
245
246 spin_unlock_irqrestore(&irq_lock, flags);
247 }
248
249
250 static struct irq_chip rise_edge_irq_type = {
251 .typename = "Au1000 Rise Edge",
252 .startup = startup_irq,
253 .shutdown = shutdown_irq,
254 .enable = local_enable_irq,
255 .disable = local_disable_irq,
256 .ack = mask_and_ack_rise_edge_irq,
257 .end = end_irq,
258 };
259
260 static struct irq_chip fall_edge_irq_type = {
261 .typename = "Au1000 Fall Edge",
262 .startup = startup_irq,
263 .shutdown = shutdown_irq,
264 .enable = local_enable_irq,
265 .disable = local_disable_irq,
266 .ack = mask_and_ack_fall_edge_irq,
267 .end = end_irq,
268 };
269
270 static struct irq_chip either_edge_irq_type = {
271 .typename = "Au1000 Rise or Fall Edge",
272 .startup = startup_irq,
273 .shutdown = shutdown_irq,
274 .enable = local_enable_irq,
275 .disable = local_disable_irq,
276 .ack = mask_and_ack_either_edge_irq,
277 .end = end_irq,
278 };
279
280 static struct irq_chip level_irq_type = {
281 .typename = "Au1000 Level",
282 .startup = startup_irq,
283 .shutdown = shutdown_irq,
284 .enable = local_enable_irq,
285 .disable = local_disable_irq,
286 .ack = mask_and_ack_level_irq,
287 .end = end_irq,
288 };
289
290 #ifdef CONFIG_PM
291 void startup_match20_interrupt(irq_handler_t handler)
292 {
293 struct irq_desc *desc = &irq_desc[AU1000_TOY_MATCH2_INT];
294
295 static struct irqaction action;
296 memset(&action, 0, sizeof(struct irqaction));
297
298 /* This is a big problem.... since we didn't use request_irq
299 * when kernel/irq.c calls probe_irq_xxx this interrupt will
300 * be probed for usage. This will end up disabling the device :(
301 * Give it a bogus "action" pointer -- this will keep it from
302 * getting auto-probed!
303 *
304 * By setting the status to match that of request_irq() we
305 * can avoid it. --cgray
306 */
307 action.dev_id = handler;
308 action.flags = IRQF_DISABLED;
309 cpus_clear(action.mask);
310 action.name = "Au1xxx TOY";
311 action.handler = handler;
312 action.next = NULL;
313
314 desc->action = &action;
315 desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS);
316
317 local_enable_irq(AU1000_TOY_MATCH2_INT);
318 }
319 #endif
320
321 static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
322 {
323 if (irq_nr > AU1000_MAX_INTR) return;
324 /* Config2[n], Config1[n], Config0[n] */
325 if (irq_nr > AU1000_LAST_INTC0_INT) {
326 switch (type) {
327 case INTC_INT_RISE_EDGE: /* 0:0:1 */
328 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
329 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
330 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
331 irq_desc[irq_nr].chip = &rise_edge_irq_type;
332 break;
333 case INTC_INT_FALL_EDGE: /* 0:1:0 */
334 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
335 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
336 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
337 irq_desc[irq_nr].chip = &fall_edge_irq_type;
338 break;
339 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
340 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
341 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
342 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
343 irq_desc[irq_nr].chip = &either_edge_irq_type;
344 break;
345 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
346 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
347 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
348 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
349 irq_desc[irq_nr].chip = &level_irq_type;
350 break;
351 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
352 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
353 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
354 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
355 irq_desc[irq_nr].chip = &level_irq_type;
356 break;
357 case INTC_INT_DISABLED: /* 0:0:0 */
358 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
359 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
360 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
361 break;
362 default: /* disable the interrupt */
363 printk("unexpected int type %d (irq %d)\n", type, irq_nr);
364 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
365 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
366 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
367 return;
368 }
369 if (int_req) /* assign to interrupt request 1 */
370 au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR);
371 else /* assign to interrupt request 0 */
372 au_writel(1<<(irq_nr-32), IC1_ASSIGNSET);
373 au_writel(1<<(irq_nr-32), IC1_SRCSET);
374 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
375 au_writel(1<<(irq_nr-32), IC1_WAKECLR);
376 }
377 else {
378 switch (type) {
379 case INTC_INT_RISE_EDGE: /* 0:0:1 */
380 au_writel(1<<irq_nr, IC0_CFG2CLR);
381 au_writel(1<<irq_nr, IC0_CFG1CLR);
382 au_writel(1<<irq_nr, IC0_CFG0SET);
383 irq_desc[irq_nr].chip = &rise_edge_irq_type;
384 break;
385 case INTC_INT_FALL_EDGE: /* 0:1:0 */
386 au_writel(1<<irq_nr, IC0_CFG2CLR);
387 au_writel(1<<irq_nr, IC0_CFG1SET);
388 au_writel(1<<irq_nr, IC0_CFG0CLR);
389 irq_desc[irq_nr].chip = &fall_edge_irq_type;
390 break;
391 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
392 au_writel(1<<irq_nr, IC0_CFG2CLR);
393 au_writel(1<<irq_nr, IC0_CFG1SET);
394 au_writel(1<<irq_nr, IC0_CFG0SET);
395 irq_desc[irq_nr].chip = &either_edge_irq_type;
396 break;
397 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
398 au_writel(1<<irq_nr, IC0_CFG2SET);
399 au_writel(1<<irq_nr, IC0_CFG1CLR);
400 au_writel(1<<irq_nr, IC0_CFG0SET);
401 irq_desc[irq_nr].chip = &level_irq_type;
402 break;
403 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
404 au_writel(1<<irq_nr, IC0_CFG2SET);
405 au_writel(1<<irq_nr, IC0_CFG1SET);
406 au_writel(1<<irq_nr, IC0_CFG0CLR);
407 irq_desc[irq_nr].chip = &level_irq_type;
408 break;
409 case INTC_INT_DISABLED: /* 0:0:0 */
410 au_writel(1<<irq_nr, IC0_CFG0CLR);
411 au_writel(1<<irq_nr, IC0_CFG1CLR);
412 au_writel(1<<irq_nr, IC0_CFG2CLR);
413 break;
414 default: /* disable the interrupt */
415 printk("unexpected int type %d (irq %d)\n", type, irq_nr);
416 au_writel(1<<irq_nr, IC0_CFG0CLR);
417 au_writel(1<<irq_nr, IC0_CFG1CLR);
418 au_writel(1<<irq_nr, IC0_CFG2CLR);
419 return;
420 }
421 if (int_req) /* assign to interrupt request 1 */
422 au_writel(1<<irq_nr, IC0_ASSIGNCLR);
423 else /* assign to interrupt request 0 */
424 au_writel(1<<irq_nr, IC0_ASSIGNSET);
425 au_writel(1<<irq_nr, IC0_SRCSET);
426 au_writel(1<<irq_nr, IC0_MASKCLR);
427 au_writel(1<<irq_nr, IC0_WAKECLR);
428 }
429 au_sync();
430 }
431
432
433 void __init arch_init_irq(void)
434 {
435 int i;
436 unsigned long cp0_status;
437 au1xxx_irq_map_t *imp;
438 extern au1xxx_irq_map_t au1xxx_irq_map[];
439 extern au1xxx_irq_map_t au1xxx_ic0_map[];
440 extern int au1xxx_nr_irqs;
441 extern int au1xxx_ic0_nr_irqs;
442
443 cp0_status = read_c0_status();
444
445 /* Initialize interrupt controllers to a safe state.
446 */
447 au_writel(0xffffffff, IC0_CFG0CLR);
448 au_writel(0xffffffff, IC0_CFG1CLR);
449 au_writel(0xffffffff, IC0_CFG2CLR);
450 au_writel(0xffffffff, IC0_MASKCLR);
451 au_writel(0xffffffff, IC0_ASSIGNSET);
452 au_writel(0xffffffff, IC0_WAKECLR);
453 au_writel(0xffffffff, IC0_SRCSET);
454 au_writel(0xffffffff, IC0_FALLINGCLR);
455 au_writel(0xffffffff, IC0_RISINGCLR);
456 au_writel(0x00000000, IC0_TESTBIT);
457
458 au_writel(0xffffffff, IC1_CFG0CLR);
459 au_writel(0xffffffff, IC1_CFG1CLR);
460 au_writel(0xffffffff, IC1_CFG2CLR);
461 au_writel(0xffffffff, IC1_MASKCLR);
462 au_writel(0xffffffff, IC1_ASSIGNSET);
463 au_writel(0xffffffff, IC1_WAKECLR);
464 au_writel(0xffffffff, IC1_SRCSET);
465 au_writel(0xffffffff, IC1_FALLINGCLR);
466 au_writel(0xffffffff, IC1_RISINGCLR);
467 au_writel(0x00000000, IC1_TESTBIT);
468
469 /* Initialize IC0, which is fixed per processor.
470 */
471 imp = au1xxx_ic0_map;
472 for (i=0; i<au1xxx_ic0_nr_irqs; i++) {
473 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
474 imp++;
475 }
476
477 /* Now set up the irq mapping for the board.
478 */
479 imp = au1xxx_irq_map;
480 for (i=0; i<au1xxx_nr_irqs; i++) {
481 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
482 imp++;
483 }
484
485 set_c0_status(ALLINTS);
486
487 /* Board specific IRQ initialization.
488 */
489 if (board_init_irq)
490 (*board_init_irq)();
491 }
492
493
494 /*
495 * Interrupts are nested. Even if an interrupt handler is registered
496 * as "fast", we might get another interrupt before we return from
497 * intcX_reqX_irqdispatch().
498 */
499
500 static void intc0_req0_irqdispatch(void)
501 {
502 int irq = 0;
503 static unsigned long intc0_req0 = 0;
504
505 intc0_req0 |= au_readl(IC0_REQ0INT);
506
507 if (!intc0_req0)
508 return;
509 #ifdef AU1000_USB_DEV_REQ_INT
510 /*
511 * Because of the tight timing of SETUP token to reply
512 * transactions, the USB devices-side packet complete
513 * interrupt needs the highest priority.
514 */
515 if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) {
516 intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT);
517 do_IRQ(AU1000_USB_DEV_REQ_INT);
518 return;
519 }
520 #endif
521 irq = au_ffs(intc0_req0) - 1;
522 intc0_req0 &= ~(1<<irq);
523 do_IRQ(irq);
524 }
525
526
527 static void intc0_req1_irqdispatch(void)
528 {
529 int irq = 0;
530 static unsigned long intc0_req1 = 0;
531
532 intc0_req1 |= au_readl(IC0_REQ1INT);
533
534 if (!intc0_req1)
535 return;
536
537 irq = au_ffs(intc0_req1) - 1;
538 intc0_req1 &= ~(1<<irq);
539 do_IRQ(irq);
540 }
541
542
543 /*
544 * Interrupt Controller 1:
545 * interrupts 32 - 63
546 */
547 static void intc1_req0_irqdispatch(void)
548 {
549 int irq = 0;
550 static unsigned long intc1_req0 = 0;
551
552 intc1_req0 |= au_readl(IC1_REQ0INT);
553
554 if (!intc1_req0)
555 return;
556
557 irq = au_ffs(intc1_req0) - 1;
558 intc1_req0 &= ~(1<<irq);
559 irq += 32;
560 do_IRQ(irq);
561 }
562
563
564 static void intc1_req1_irqdispatch(void)
565 {
566 int irq = 0;
567 static unsigned long intc1_req1 = 0;
568
569 intc1_req1 |= au_readl(IC1_REQ1INT);
570
571 if (!intc1_req1)
572 return;
573
574 irq = au_ffs(intc1_req1) - 1;
575 intc1_req1 &= ~(1<<irq);
576 irq += 32;
577 do_IRQ(irq);
578 }
579
580 #ifdef CONFIG_PM
581
582 /* Save/restore the interrupt controller state.
583 * Called from the save/restore core registers as part of the
584 * au_sleep function in power.c.....maybe I should just pm_register()
585 * them instead?
586 */
587 static unsigned int sleep_intctl_config0[2];
588 static unsigned int sleep_intctl_config1[2];
589 static unsigned int sleep_intctl_config2[2];
590 static unsigned int sleep_intctl_src[2];
591 static unsigned int sleep_intctl_assign[2];
592 static unsigned int sleep_intctl_wake[2];
593 static unsigned int sleep_intctl_mask[2];
594
595 void
596 save_au1xxx_intctl(void)
597 {
598 sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
599 sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
600 sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
601 sleep_intctl_src[0] = au_readl(IC0_SRCRD);
602 sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
603 sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
604 sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
605
606 sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
607 sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
608 sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
609 sleep_intctl_src[1] = au_readl(IC1_SRCRD);
610 sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
611 sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
612 sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
613 }
614
615 /* For most restore operations, we clear the entire register and
616 * then set the bits we found during the save.
617 */
618 void
619 restore_au1xxx_intctl(void)
620 {
621 au_writel(0xffffffff, IC0_MASKCLR); au_sync();
622
623 au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
624 au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
625 au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
626 au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
627 au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
628 au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
629 au_writel(0xffffffff, IC0_SRCCLR); au_sync();
630 au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
631 au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
632 au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
633 au_writel(0xffffffff, IC0_WAKECLR); au_sync();
634 au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
635 au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
636 au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
637 au_writel(0x00000000, IC0_TESTBIT); au_sync();
638
639 au_writel(0xffffffff, IC1_MASKCLR); au_sync();
640
641 au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
642 au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
643 au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
644 au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
645 au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
646 au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
647 au_writel(0xffffffff, IC1_SRCCLR); au_sync();
648 au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
649 au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
650 au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
651 au_writel(0xffffffff, IC1_WAKECLR); au_sync();
652 au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
653 au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
654 au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
655 au_writel(0x00000000, IC1_TESTBIT); au_sync();
656
657 au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
658
659 au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
660 }
661 #endif /* CONFIG_PM */
662
663 asmlinkage void plat_irq_dispatch(void)
664 {
665 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
666
667 if (pending & CAUSEF_IP7)
668 mips_timer_interrupt();
669 else if (pending & CAUSEF_IP2)
670 intc0_req0_irqdispatch();
671 else if (pending & CAUSEF_IP3)
672 intc0_req1_irqdispatch();
673 else if (pending & CAUSEF_IP4)
674 intc1_req0_irqdispatch();
675 else if (pending & CAUSEF_IP5)
676 intc1_req1_irqdispatch();
677 else
678 spurious_interrupt();
679 }
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