3 * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com
4 * Copied and modified Carsten Langgaard's time.c
6 * Carsten Langgaard, carstenl@mips.com
7 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
9 * ########################################################################
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 * ########################################################################
26 * Setting up the clock on the MIPS boards.
28 * Update. Always configure the kernel with CONFIG_NEW_TIME_C. This
29 * will use the user interface gettimeofday() functions from the
30 * arch/mips/kernel/time.c, and we provide the clock interrupt processing
31 * and the timer offset compute functions. If CONFIG_PM is selected,
32 * we also ensure the 32KHz timer is available. -- Dan
35 #include <linux/types.h>
36 #include <linux/config.h>
37 #include <linux/init.h>
38 #include <linux/kernel_stat.h>
39 #include <linux/sched.h>
40 #include <linux/spinlock.h>
41 #include <linux/hardirq.h>
43 #include <asm/compiler.h>
44 #include <asm/mipsregs.h>
45 #include <asm/ptrace.h>
47 #include <asm/div64.h>
48 #include <asm/mach-au1x00/au1000.h>
50 #include <linux/mc146818rtc.h>
51 #include <linux/timex.h>
53 extern void do_softirq(void);
54 extern volatile unsigned long wall_jiffies
;
55 unsigned long missed_heart_beats
= 0;
57 static unsigned long r4k_offset
; /* Amount to increment compare reg each time */
58 static unsigned long r4k_cur
; /* What counter should be at next timer irq */
60 extern int allow_au1k_wait
; /* default off for CP0 Counter */
62 /* Cycle counter value at the previous timer interrupt.. */
63 static unsigned int timerhi
= 0, timerlo
= 0;
66 #if HZ < 100 || HZ > 1000
67 #error "unsupported HZ value! Must be in [100,1000]"
69 #define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */
70 extern void startup_match20_interrupt(irqreturn_t (*handler
)(int, void *, struct pt_regs
*));
71 static unsigned long last_pc0
, last_match20
;
74 static DEFINE_SPINLOCK(time_lock
);
76 static inline void ack_r4ktimer(unsigned long newval
)
78 write_c0_compare(newval
);
82 * There are a lot of conceptually broken versions of the MIPS timer interrupt
83 * handler floating around. This one is rather different, but the algorithm
84 * is provably more robust.
87 void mips_timer_interrupt(struct pt_regs
*regs
)
93 kstat_this_cpu
.irqs
[irq
]++;
99 count
= read_c0_count();
100 timerhi
+= (count
< timerlo
); /* Wrap around */
103 kstat_this_cpu
.irqs
[irq
]++;
106 update_process_times(user_mode(regs
));
108 r4k_cur
+= r4k_offset
;
109 ack_r4ktimer(r4k_cur
);
111 } while (((unsigned long)read_c0_count()
112 - r4k_cur
) < 0x7fffffff);
122 irqreturn_t
counter0_irq(int irq
, void *dev_id
, struct pt_regs
*regs
)
126 static int jiffie_drift
= 0;
128 if (au_readl(SYS_COUNTER_CNTRL
) & SYS_CNTRL_M20
) {
129 /* should never happen! */
130 printk(KERN_WARNING
"counter 0 w status error\n");
134 pc0
= au_readl(SYS_TOYREAD
);
135 if (pc0
< last_match20
) {
136 /* counter overflowed */
137 time_elapsed
= (0xffffffff - last_match20
) + pc0
;
140 time_elapsed
= pc0
- last_match20
;
143 while (time_elapsed
> 0) {
146 update_process_times(user_mode(regs
));
148 time_elapsed
-= MATCH20_INC
;
149 last_match20
+= MATCH20_INC
;
154 au_writel(last_match20
+ MATCH20_INC
, SYS_TOYMATCH2
);
157 /* our counter ticks at 10.009765625 ms/tick, we we're running
158 * almost 10uS too slow per tick.
161 if (jiffie_drift
>= 999) {
163 do_timer(regs
); /* increment jiffies by one */
165 update_process_times(user_mode(regs
));
172 /* When we wakeup from sleep, we have to "catch up" on all of the
173 * timer ticks we have missed.
176 wakeup_counter0_adjust(void)
181 pc0
= au_readl(SYS_TOYREAD
);
182 if (pc0
< last_match20
) {
183 /* counter overflowed */
184 time_elapsed
= (0xffffffff - last_match20
) + pc0
;
187 time_elapsed
= pc0
- last_match20
;
190 while (time_elapsed
> 0) {
191 time_elapsed
-= MATCH20_INC
;
192 last_match20
+= MATCH20_INC
;
196 au_writel(last_match20
+ MATCH20_INC
, SYS_TOYMATCH2
);
201 /* This is just for debugging to set the timer for a sleep delay.
204 wakeup_counter0_set(int ticks
)
208 pc0
= au_readl(SYS_TOYREAD
);
210 au_writel(last_match20
+ (MATCH20_INC
* ticks
), SYS_TOYMATCH2
);
215 /* I haven't found anyone that doesn't use a 12 MHz source clock,
216 * but just in case.....
218 #ifdef CONFIG_AU1000_SRC_CLK
219 #define AU1000_SRC_CLK CONFIG_AU1000_SRC_CLK
221 #define AU1000_SRC_CLK 12000000
225 * We read the real processor speed from the PLL. This is important
226 * because it is more accurate than computing it from the 32KHz
227 * counter, if it exists. If we don't have an accurate processor
228 * speed, all of the peripherals that derive their clocks based on
229 * this advertised speed will introduce error and sometimes not work
230 * properly. This function is futher convoluted to still allow configurations
231 * to do that in case they have really, really old silicon with a
232 * write-only PLL register, that we need the 32KHz when power management
233 * "wait" is enabled, and we need to detect if the 32KHz isn't present
234 * but requested......got it? :-) -- Dan
236 unsigned long cal_r4koff(void)
239 unsigned long cpu_speed
;
241 unsigned long counter
;
243 spin_lock_irqsave(&time_lock
, flags
);
245 /* Power management cares if we don't have a 32KHz counter.
248 counter
= au_readl(SYS_COUNTER_CNTRL
);
249 if (counter
& SYS_CNTRL_E0
) {
250 int trim_divide
= 16;
252 au_writel(counter
| SYS_CNTRL_EN1
, SYS_COUNTER_CNTRL
);
254 while (au_readl(SYS_COUNTER_CNTRL
) & SYS_CNTRL_T1S
);
255 /* RTC now ticks at 32.768/16 kHz */
256 au_writel(trim_divide
-1, SYS_RTCTRIM
);
257 while (au_readl(SYS_COUNTER_CNTRL
) & SYS_CNTRL_T1S
);
259 while (au_readl(SYS_COUNTER_CNTRL
) & SYS_CNTRL_C1S
);
260 au_writel (0, SYS_TOYWRITE
);
261 while (au_readl(SYS_COUNTER_CNTRL
) & SYS_CNTRL_C1S
);
263 #if defined(CONFIG_AU1000_USE32K)
265 unsigned long start
, end
;
267 start
= au_readl(SYS_RTCREAD
);
269 /* wait for the beginning of a new tick
271 while (au_readl(SYS_RTCREAD
) < start
);
273 /* Start r4k counter.
279 end
= start
+ (32768 / trim_divide
)/2;
281 while (end
> au_readl(SYS_RTCREAD
));
283 count
= read_c0_count();
284 cpu_speed
= count
* 2;
287 cpu_speed
= (au_readl(SYS_CPUPLL
) & 0x0000003f) *
289 count
= cpu_speed
/ 2;
293 /* The 32KHz oscillator isn't running, so assume there
294 * isn't one and grab the processor speed from the PLL.
295 * NOTE: some old silicon doesn't allow reading the PLL.
297 cpu_speed
= (au_readl(SYS_CPUPLL
) & 0x0000003f) * AU1000_SRC_CLK
;
298 count
= cpu_speed
/ 2;
301 mips_hpt_frequency
= count
;
302 // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
303 set_au1x00_uart_baud_base(cpu_speed
/ (2 * ((int)(au_readl(SYS_POWERCTRL
)&0x03) + 2) * 16));
304 spin_unlock_irqrestore(&time_lock
, flags
);
305 return (cpu_speed
/ HZ
);
308 /* This is for machines which generate the exact clock. */
309 #define USECS_PER_JIFFY (1000000/HZ)
310 #define USECS_PER_JIFFY_FRAC (0x100000000LL*1000000/HZ&0xffffffff)
313 div64_32(unsigned long v1
, unsigned long v2
, unsigned long v3
)
316 do_div64_32(r0
, v1
, v2
, v3
);
320 static unsigned long do_fast_cp0_gettimeoffset(void)
323 unsigned long res
, tmp
;
326 /* Last jiffy when do_fast_gettimeoffset() was called. */
327 static unsigned long last_jiffies
=0;
328 unsigned long quotient
;
331 * Cached "1/(clocks per usec)*2^32" value.
332 * It has to be recalculated once each jiffy.
334 static unsigned long cached_quotient
=0;
338 quotient
= cached_quotient
;
340 if (tmp
&& last_jiffies
!= tmp
) {
342 if (last_jiffies
!= 0) {
343 r0
= div64_32(timerhi
, timerlo
, tmp
);
344 quotient
= div64_32(USECS_PER_JIFFY
, USECS_PER_JIFFY_FRAC
, r0
);
345 cached_quotient
= quotient
;
349 /* Get last timer tick in absolute kernel time */
350 count
= read_c0_count();
352 /* .. relative to previous jiffy (32 bits is enough) */
355 __asm__("multu\t%1,%2\n\t"
358 : "r" (count
), "r" (quotient
)
359 : "hi", "lo", GCC_REG_ACCUM
);
362 * Due to possible jiffies inconsistencies, we need to check
363 * the result so that we'll get a timer that is monotonic.
365 if (res
>= USECS_PER_JIFFY
)
366 res
= USECS_PER_JIFFY
-1;
372 static unsigned long do_fast_pm_gettimeoffset(void)
375 unsigned long offset
;
377 pc0
= au_readl(SYS_TOYREAD
);
379 offset
= pc0
- last_pc0
;
380 if (offset
> 2*MATCH20_INC
) {
381 printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
382 (unsigned)offset
, (unsigned)last_pc0
,
383 (unsigned)last_match20
, (unsigned)pc0
);
385 offset
= (unsigned long)((offset
* 305) / 10);
390 void au1xxx_timer_setup(struct irqaction
*irq
)
392 unsigned int est_freq
;
393 extern unsigned long (*do_gettimeoffset
)(void);
395 printk("calculating r4koff... ");
396 r4k_offset
= cal_r4koff();
397 printk("%08lx(%d)\n", r4k_offset
, (int) r4k_offset
);
399 //est_freq = 2*r4k_offset*HZ;
400 est_freq
= r4k_offset
*HZ
;
401 est_freq
+= 5000; /* round */
402 est_freq
-= est_freq
%10000;
403 printk("CPU frequency %d.%02d MHz\n", est_freq
/1000000,
404 (est_freq
%1000000)*100/1000000);
405 set_au1x00_speed(est_freq
);
406 set_au1x00_lcd_clock(); // program the LCD clock
408 r4k_cur
= (read_c0_count() + r4k_offset
);
409 write_c0_compare(r4k_cur
);
413 * setup counter 0, since it keeps ticking after a
414 * 'wait' instruction has been executed. The CP0 timer and
415 * counter 1 do NOT continue running after 'wait'
417 * It's too early to call request_irq() here, so we handle
418 * counter 0 interrupt as a special irq and it doesn't show
419 * up under /proc/interrupts.
421 * Check to ensure we really have a 32KHz oscillator before
424 if (no_au1xxx_32khz
) {
425 unsigned int c0_status
;
427 printk("WARNING: no 32KHz clock found.\n");
428 do_gettimeoffset
= do_fast_cp0_gettimeoffset
;
430 /* Ensure we get CPO_COUNTER interrupts.
432 c0_status
= read_c0_status();
433 c0_status
|= IE_IRQ5
;
434 write_c0_status(c0_status
);
437 while (au_readl(SYS_COUNTER_CNTRL
) & SYS_CNTRL_C0S
);
438 au_writel(0, SYS_TOYWRITE
);
439 while (au_readl(SYS_COUNTER_CNTRL
) & SYS_CNTRL_C0S
);
441 au_writel(au_readl(SYS_WAKEMSK
) | (1<<8), SYS_WAKEMSK
);
442 au_writel(~0, SYS_WAKESRC
);
444 while (au_readl(SYS_COUNTER_CNTRL
) & SYS_CNTRL_M20
);
446 /* setup match20 to interrupt once every HZ */
447 last_pc0
= last_match20
= au_readl(SYS_TOYREAD
);
448 au_writel(last_match20
+ MATCH20_INC
, SYS_TOYMATCH2
);
450 while (au_readl(SYS_COUNTER_CNTRL
) & SYS_CNTRL_M20
);
451 startup_match20_interrupt(counter0_irq
);
453 do_gettimeoffset
= do_fast_pm_gettimeoffset
;
455 /* We can use the real 'wait' instruction.
461 /* We have to do this here instead of in timer_init because
462 * the generic code in arch/mips/kernel/time.c will write
463 * over our function pointer.
465 do_gettimeoffset
= do_fast_cp0_gettimeoffset
;
469 void __init
au1xxx_time_init(void)