]>
git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blob - arch/mips/bcm63xx/clk.c
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
9 #include <linux/init.h>
10 #include <linux/export.h>
11 #include <linux/mutex.h>
12 #include <linux/err.h>
13 #include <linux/clk.h>
14 #include <linux/clkdev.h>
15 #include <linux/delay.h>
16 #include <bcm63xx_cpu.h>
17 #include <bcm63xx_io.h>
18 #include <bcm63xx_regs.h>
19 #include <bcm63xx_reset.h>
22 void (*set
)(struct clk
*, int);
28 static DEFINE_MUTEX(clocks_mutex
);
31 static void clk_enable_unlocked(struct clk
*clk
)
33 if (clk
->set
&& (clk
->usage
++) == 0)
37 static void clk_disable_unlocked(struct clk
*clk
)
39 if (clk
->set
&& (--clk
->usage
) == 0)
43 static void bcm_hwclock_set(u32 mask
, int enable
)
47 reg
= bcm_perf_readl(PERF_CKCTL_REG
);
52 bcm_perf_writel(reg
, PERF_CKCTL_REG
);
56 * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
58 static void enet_misc_set(struct clk
*clk
, int enable
)
63 mask
= CKCTL_6338_ENET_EN
;
64 else if (BCMCPU_IS_6345())
65 mask
= CKCTL_6345_ENET_EN
;
66 else if (BCMCPU_IS_6348())
67 mask
= CKCTL_6348_ENET_EN
;
70 mask
= CKCTL_6358_EMUSB_EN
;
71 bcm_hwclock_set(mask
, enable
);
74 static struct clk clk_enet_misc
= {
79 * Ethernet MAC clocks: only revelant on 6358, silently enable misc
82 static void enetx_set(struct clk
*clk
, int enable
)
85 clk_enable_unlocked(&clk_enet_misc
);
87 clk_disable_unlocked(&clk_enet_misc
);
89 if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
93 mask
= CKCTL_6358_ENET0_EN
;
95 mask
= CKCTL_6358_ENET1_EN
;
96 bcm_hwclock_set(mask
, enable
);
100 static struct clk clk_enet0
= {
105 static struct clk clk_enet1
= {
113 static void ephy_set(struct clk
*clk
, int enable
)
115 if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
116 bcm_hwclock_set(CKCTL_6358_EPHY_EN
, enable
);
120 static struct clk clk_ephy
= {
125 * Ethernet switch SAR clock
127 static void swpkt_sar_set(struct clk
*clk
, int enable
)
129 if (BCMCPU_IS_6368())
130 bcm_hwclock_set(CKCTL_6368_SWPKT_SAR_EN
, enable
);
135 static struct clk clk_swpkt_sar
= {
136 .set
= swpkt_sar_set
,
140 * Ethernet switch USB clock
142 static void swpkt_usb_set(struct clk
*clk
, int enable
)
144 if (BCMCPU_IS_6368())
145 bcm_hwclock_set(CKCTL_6368_SWPKT_USB_EN
, enable
);
150 static struct clk clk_swpkt_usb
= {
151 .set
= swpkt_usb_set
,
155 * Ethernet switch clock
157 static void enetsw_set(struct clk
*clk
, int enable
)
159 if (BCMCPU_IS_6328()) {
160 bcm_hwclock_set(CKCTL_6328_ROBOSW_EN
, enable
);
161 } else if (BCMCPU_IS_6362()) {
162 bcm_hwclock_set(CKCTL_6362_ROBOSW_EN
, enable
);
163 } else if (BCMCPU_IS_6368()) {
165 clk_enable_unlocked(&clk_swpkt_sar
);
166 clk_enable_unlocked(&clk_swpkt_usb
);
168 clk_disable_unlocked(&clk_swpkt_usb
);
169 clk_disable_unlocked(&clk_swpkt_sar
);
171 bcm_hwclock_set(CKCTL_6368_ROBOSW_EN
, enable
);
177 /* reset switch core afer clock change */
178 bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW
, 1);
180 bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW
, 0);
185 static struct clk clk_enetsw
= {
192 static void pcm_set(struct clk
*clk
, int enable
)
194 if (BCMCPU_IS_3368())
195 bcm_hwclock_set(CKCTL_3368_PCM_EN
, enable
);
196 if (BCMCPU_IS_6358())
197 bcm_hwclock_set(CKCTL_6358_PCM_EN
, enable
);
200 static struct clk clk_pcm
= {
207 static void usbh_set(struct clk
*clk
, int enable
)
209 if (BCMCPU_IS_6328())
210 bcm_hwclock_set(CKCTL_6328_USBH_EN
, enable
);
211 else if (BCMCPU_IS_6348())
212 bcm_hwclock_set(CKCTL_6348_USBH_EN
, enable
);
213 else if (BCMCPU_IS_6362())
214 bcm_hwclock_set(CKCTL_6362_USBH_EN
, enable
);
215 else if (BCMCPU_IS_6368())
216 bcm_hwclock_set(CKCTL_6368_USBH_EN
, enable
);
219 static struct clk clk_usbh
= {
226 static void usbd_set(struct clk
*clk
, int enable
)
228 if (BCMCPU_IS_6328())
229 bcm_hwclock_set(CKCTL_6328_USBD_EN
, enable
);
230 else if (BCMCPU_IS_6362())
231 bcm_hwclock_set(CKCTL_6362_USBD_EN
, enable
);
232 else if (BCMCPU_IS_6368())
233 bcm_hwclock_set(CKCTL_6368_USBD_EN
, enable
);
236 static struct clk clk_usbd
= {
243 static void spi_set(struct clk
*clk
, int enable
)
247 if (BCMCPU_IS_6338())
248 mask
= CKCTL_6338_SPI_EN
;
249 else if (BCMCPU_IS_6348())
250 mask
= CKCTL_6348_SPI_EN
;
251 else if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
252 mask
= CKCTL_6358_SPI_EN
;
253 else if (BCMCPU_IS_6362())
254 mask
= CKCTL_6362_SPI_EN
;
257 mask
= CKCTL_6368_SPI_EN
;
258 bcm_hwclock_set(mask
, enable
);
261 static struct clk clk_spi
= {
268 static void hsspi_set(struct clk
*clk
, int enable
)
272 if (BCMCPU_IS_6328())
273 mask
= CKCTL_6328_HSSPI_EN
;
274 else if (BCMCPU_IS_6362())
275 mask
= CKCTL_6362_HSSPI_EN
;
279 bcm_hwclock_set(mask
, enable
);
282 static struct clk clk_hsspi
= {
289 static struct clk clk_hsspi_pll
;
294 static void xtm_set(struct clk
*clk
, int enable
)
296 if (!BCMCPU_IS_6368())
300 clk_enable_unlocked(&clk_swpkt_sar
);
302 clk_disable_unlocked(&clk_swpkt_sar
);
304 bcm_hwclock_set(CKCTL_6368_SAR_EN
, enable
);
307 /* reset sar core afer clock change */
308 bcm63xx_core_set_reset(BCM63XX_RESET_SAR
, 1);
310 bcm63xx_core_set_reset(BCM63XX_RESET_SAR
, 0);
316 static struct clk clk_xtm
= {
323 static void ipsec_set(struct clk
*clk
, int enable
)
325 if (BCMCPU_IS_6362())
326 bcm_hwclock_set(CKCTL_6362_IPSEC_EN
, enable
);
327 else if (BCMCPU_IS_6368())
328 bcm_hwclock_set(CKCTL_6368_IPSEC_EN
, enable
);
331 static struct clk clk_ipsec
= {
339 static void pcie_set(struct clk
*clk
, int enable
)
341 if (BCMCPU_IS_6328())
342 bcm_hwclock_set(CKCTL_6328_PCIE_EN
, enable
);
343 else if (BCMCPU_IS_6362())
344 bcm_hwclock_set(CKCTL_6362_PCIE_EN
, enable
);
347 static struct clk clk_pcie
= {
352 * Internal peripheral clock
354 static struct clk clk_periph
= {
355 .rate
= (50 * 1000 * 1000),
360 * Linux clock API implementation
362 int clk_enable(struct clk
*clk
)
364 mutex_lock(&clocks_mutex
);
365 clk_enable_unlocked(clk
);
366 mutex_unlock(&clocks_mutex
);
370 EXPORT_SYMBOL(clk_enable
);
372 void clk_disable(struct clk
*clk
)
377 mutex_lock(&clocks_mutex
);
378 clk_disable_unlocked(clk
);
379 mutex_unlock(&clocks_mutex
);
382 EXPORT_SYMBOL(clk_disable
);
384 unsigned long clk_get_rate(struct clk
*clk
)
392 EXPORT_SYMBOL(clk_get_rate
);
394 int clk_set_rate(struct clk
*clk
, unsigned long rate
)
398 EXPORT_SYMBOL_GPL(clk_set_rate
);
400 long clk_round_rate(struct clk
*clk
, unsigned long rate
)
404 EXPORT_SYMBOL_GPL(clk_round_rate
);
406 static struct clk_lookup bcm3368_clks
[] = {
407 /* fixed rate clocks */
408 CLKDEV_INIT(NULL
, "periph", &clk_periph
),
409 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph
),
410 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph
),
412 CLKDEV_INIT(NULL
, "enet0", &clk_enet0
),
413 CLKDEV_INIT(NULL
, "enet1", &clk_enet1
),
414 CLKDEV_INIT(NULL
, "ephy", &clk_ephy
),
415 CLKDEV_INIT(NULL
, "usbh", &clk_usbh
),
416 CLKDEV_INIT(NULL
, "usbd", &clk_usbd
),
417 CLKDEV_INIT(NULL
, "spi", &clk_spi
),
418 CLKDEV_INIT(NULL
, "pcm", &clk_pcm
),
419 CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0
),
420 CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1
),
423 static struct clk_lookup bcm6328_clks
[] = {
424 /* fixed rate clocks */
425 CLKDEV_INIT(NULL
, "periph", &clk_periph
),
426 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph
),
427 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph
),
428 CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll
),
430 CLKDEV_INIT(NULL
, "enetsw", &clk_enetsw
),
431 CLKDEV_INIT(NULL
, "usbh", &clk_usbh
),
432 CLKDEV_INIT(NULL
, "usbd", &clk_usbd
),
433 CLKDEV_INIT(NULL
, "hsspi", &clk_hsspi
),
434 CLKDEV_INIT(NULL
, "pcie", &clk_pcie
),
437 static struct clk_lookup bcm6338_clks
[] = {
438 /* fixed rate clocks */
439 CLKDEV_INIT(NULL
, "periph", &clk_periph
),
440 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph
),
442 CLKDEV_INIT(NULL
, "enet0", &clk_enet0
),
443 CLKDEV_INIT(NULL
, "enet1", &clk_enet1
),
444 CLKDEV_INIT(NULL
, "ephy", &clk_ephy
),
445 CLKDEV_INIT(NULL
, "usbh", &clk_usbh
),
446 CLKDEV_INIT(NULL
, "usbd", &clk_usbd
),
447 CLKDEV_INIT(NULL
, "spi", &clk_spi
),
448 CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc
),
451 static struct clk_lookup bcm6345_clks
[] = {
452 /* fixed rate clocks */
453 CLKDEV_INIT(NULL
, "periph", &clk_periph
),
454 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph
),
456 CLKDEV_INIT(NULL
, "enet0", &clk_enet0
),
457 CLKDEV_INIT(NULL
, "enet1", &clk_enet1
),
458 CLKDEV_INIT(NULL
, "ephy", &clk_ephy
),
459 CLKDEV_INIT(NULL
, "usbh", &clk_usbh
),
460 CLKDEV_INIT(NULL
, "usbd", &clk_usbd
),
461 CLKDEV_INIT(NULL
, "spi", &clk_spi
),
462 CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc
),
465 static struct clk_lookup bcm6348_clks
[] = {
466 /* fixed rate clocks */
467 CLKDEV_INIT(NULL
, "periph", &clk_periph
),
468 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph
),
470 CLKDEV_INIT(NULL
, "enet0", &clk_enet0
),
471 CLKDEV_INIT(NULL
, "enet1", &clk_enet1
),
472 CLKDEV_INIT(NULL
, "ephy", &clk_ephy
),
473 CLKDEV_INIT(NULL
, "usbh", &clk_usbh
),
474 CLKDEV_INIT(NULL
, "usbd", &clk_usbd
),
475 CLKDEV_INIT(NULL
, "spi", &clk_spi
),
476 CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet_misc
),
477 CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet_misc
),
480 static struct clk_lookup bcm6358_clks
[] = {
481 /* fixed rate clocks */
482 CLKDEV_INIT(NULL
, "periph", &clk_periph
),
483 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph
),
484 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph
),
486 CLKDEV_INIT(NULL
, "enet0", &clk_enet0
),
487 CLKDEV_INIT(NULL
, "enet1", &clk_enet1
),
488 CLKDEV_INIT(NULL
, "ephy", &clk_ephy
),
489 CLKDEV_INIT(NULL
, "usbh", &clk_usbh
),
490 CLKDEV_INIT(NULL
, "usbd", &clk_usbd
),
491 CLKDEV_INIT(NULL
, "spi", &clk_spi
),
492 CLKDEV_INIT(NULL
, "pcm", &clk_pcm
),
493 CLKDEV_INIT(NULL
, "swpkt_sar", &clk_swpkt_sar
),
494 CLKDEV_INIT(NULL
, "swpkt_usb", &clk_swpkt_usb
),
495 CLKDEV_INIT("bcm63xx_enet.0", "enet", &clk_enet0
),
496 CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1
),
499 static struct clk_lookup bcm6362_clks
[] = {
500 /* fixed rate clocks */
501 CLKDEV_INIT(NULL
, "periph", &clk_periph
),
502 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph
),
503 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph
),
504 CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll
),
506 CLKDEV_INIT(NULL
, "enetsw", &clk_enetsw
),
507 CLKDEV_INIT(NULL
, "usbh", &clk_usbh
),
508 CLKDEV_INIT(NULL
, "usbd", &clk_usbd
),
509 CLKDEV_INIT(NULL
, "spi", &clk_spi
),
510 CLKDEV_INIT(NULL
, "hsspi", &clk_hsspi
),
511 CLKDEV_INIT(NULL
, "pcie", &clk_pcie
),
512 CLKDEV_INIT(NULL
, "ipsec", &clk_ipsec
),
515 static struct clk_lookup bcm6368_clks
[] = {
516 /* fixed rate clocks */
517 CLKDEV_INIT(NULL
, "periph", &clk_periph
),
518 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph
),
519 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph
),
521 CLKDEV_INIT(NULL
, "enetsw", &clk_enetsw
),
522 CLKDEV_INIT(NULL
, "usbh", &clk_usbh
),
523 CLKDEV_INIT(NULL
, "usbd", &clk_usbd
),
524 CLKDEV_INIT(NULL
, "spi", &clk_spi
),
525 CLKDEV_INIT(NULL
, "xtm", &clk_xtm
),
526 CLKDEV_INIT(NULL
, "ipsec", &clk_ipsec
),
529 #define HSSPI_PLL_HZ_6328 133333333
530 #define HSSPI_PLL_HZ_6362 400000000
532 static int __init
bcm63xx_clk_init(void)
534 switch (bcm63xx_get_cpu_id()) {
536 clkdev_add_table(bcm3368_clks
, ARRAY_SIZE(bcm3368_clks
));
539 clk_hsspi_pll
.rate
= HSSPI_PLL_HZ_6328
;
540 clkdev_add_table(bcm6328_clks
, ARRAY_SIZE(bcm6328_clks
));
543 clkdev_add_table(bcm6338_clks
, ARRAY_SIZE(bcm6338_clks
));
546 clkdev_add_table(bcm6345_clks
, ARRAY_SIZE(bcm6345_clks
));
549 clkdev_add_table(bcm6348_clks
, ARRAY_SIZE(bcm6348_clks
));
552 clkdev_add_table(bcm6358_clks
, ARRAY_SIZE(bcm6358_clks
));
555 clk_hsspi_pll
.rate
= HSSPI_PLL_HZ_6362
;
556 clkdev_add_table(bcm6362_clks
, ARRAY_SIZE(bcm6362_clks
));
559 clkdev_add_table(bcm6368_clks
, ARRAY_SIZE(bcm6368_clks
));
565 arch_initcall(bcm63xx_clk_init
);