4 compatible = "brcm,bcm7346";
10 mips-hpt-frequency = <163125000>;
13 compatible = "brcm,bmips5000";
19 compatible = "brcm,bmips5000";
33 compatible = "mti,cpu-interrupt-controller";
36 #interrupt-cells = <1>;
41 compatible = "fixed-clock";
43 clock-frequency = <81000000>;
51 compatible = "simple-bus";
52 ranges = <0 0x10000000 0x01000000>;
54 periph_intc: periph_intc@411400 {
55 compatible = "brcm,bcm7038-l1-intc";
56 reg = <0x411400 0x30>, <0x411600 0x30>;
59 #interrupt-cells = <1>;
61 interrupt-parent = <&cpu_intc>;
62 interrupts = <2>, <3>;
65 sun_l2_intc: sun_l2_intc@403000 {
66 compatible = "brcm,l2-intc";
67 reg = <0x403000 0x30>;
69 #interrupt-cells = <1>;
70 interrupt-parent = <&periph_intc>;
75 compatible = "brcm,bcm7400-gisb-arb";
76 reg = <0x400000 0xdc>;
78 interrupt-parent = <&sun_l2_intc>;
79 interrupts = <0>, <2>;
80 brcm,gisb-arb-master-mask = <0x673>;
81 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
86 upg_irq0_intc: upg_irq0_intc@406780 {
87 compatible = "brcm,bcm7120-l2-intc";
90 brcm,int-map-mask = <0x44>, <0xf000000>;
91 brcm,int-fwd-mask = <0x70000>;
94 #interrupt-cells = <1>;
96 interrupt-parent = <&periph_intc>;
97 interrupts = <59>, <57>;
98 interrupt-names = "upg_main", "upg_bsc";
101 upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
102 compatible = "brcm,bcm7120-l2-intc";
103 reg = <0x408b80 0x8>;
105 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
106 brcm,int-fwd-mask = <0>;
109 interrupt-controller;
110 #interrupt-cells = <1>;
112 interrupt-parent = <&periph_intc>;
113 interrupts = <60>, <58>, <62>;
114 interrupt-names = "upg_main_aon", "upg_bsc_aon",
118 sun_top_ctrl: syscon@404000 {
119 compatible = "brcm,bcm7346-sun-top-ctrl", "syscon";
120 reg = <0x404000 0x51c>;
124 compatible = "brcm,brcmstb-reboot";
125 syscon = <&sun_top_ctrl 0x304 0x308>;
128 uart0: serial@406900 {
129 compatible = "ns16550a";
130 reg = <0x406900 0x20>;
131 reg-io-width = <0x4>;
134 interrupt-parent = <&periph_intc>;
136 clocks = <&uart_clk>;
140 uart1: serial@406940 {
141 compatible = "ns16550a";
142 reg = <0x406940 0x20>;
143 reg-io-width = <0x4>;
146 interrupt-parent = <&periph_intc>;
148 clocks = <&uart_clk>;
152 uart2: serial@406980 {
153 compatible = "ns16550a";
154 reg = <0x406980 0x20>;
155 reg-io-width = <0x4>;
158 interrupt-parent = <&periph_intc>;
160 clocks = <&uart_clk>;
165 clock-frequency = <390000>;
166 compatible = "brcm,brcmstb-i2c";
167 interrupt-parent = <&upg_irq0_intc>;
168 reg = <0x406200 0x58>;
170 interrupt-names = "upg_bsca";
175 clock-frequency = <390000>;
176 compatible = "brcm,brcmstb-i2c";
177 interrupt-parent = <&upg_irq0_intc>;
178 reg = <0x406280 0x58>;
180 interrupt-names = "upg_bscb";
185 clock-frequency = <390000>;
186 compatible = "brcm,brcmstb-i2c";
187 interrupt-parent = <&upg_irq0_intc>;
188 reg = <0x406300 0x58>;
190 interrupt-names = "upg_bscc";
195 clock-frequency = <390000>;
196 compatible = "brcm,brcmstb-i2c";
197 interrupt-parent = <&upg_irq0_intc>;
198 reg = <0x406380 0x58>;
200 interrupt-names = "upg_bscd";
205 clock-frequency = <390000>;
206 compatible = "brcm,brcmstb-i2c";
207 interrupt-parent = <&upg_aon_irq0_intc>;
208 reg = <0x408980 0x58>;
210 interrupt-names = "upg_bsce";
214 enet0: ethernet@430000 {
215 phy-mode = "internal";
216 phy-handle = <&phy1>;
217 mac-address = [ 00 10 18 36 23 1a ];
218 compatible = "brcm,genet-v2";
219 #address-cells = <0x1>;
221 reg = <0x430000 0x4c8c>;
222 interrupts = <24>, <25>;
223 interrupt-parent = <&periph_intc>;
227 compatible = "brcm,genet-mdio-v2";
228 #address-cells = <0x1>;
232 phy1: ethernet-phy@1 {
235 compatible = "brcm,40nm-ephy",
236 "ethernet-phy-ieee802.3-c22";
242 compatible = "brcm,bcm7346-ehci", "generic-ehci";
243 reg = <0x480300 0x100>;
245 interrupt-parent = <&periph_intc>;
251 compatible = "brcm,bcm7346-ohci", "generic-ohci";
252 reg = <0x480400 0x100>;
255 interrupt-parent = <&periph_intc>;
261 compatible = "brcm,bcm7346-ehci", "generic-ehci";
262 reg = <0x480500 0x100>;
264 interrupt-parent = <&periph_intc>;
270 compatible = "brcm,bcm7346-ohci", "generic-ohci";
271 reg = <0x480600 0x100>;
274 interrupt-parent = <&periph_intc>;
280 compatible = "brcm,bcm7346-ehci", "generic-ehci";
281 reg = <0x490300 0x100>;
283 interrupt-parent = <&periph_intc>;
289 compatible = "brcm,bcm7346-ohci", "generic-ohci";
290 reg = <0x490400 0x100>;
293 interrupt-parent = <&periph_intc>;
299 compatible = "brcm,bcm7346-ehci", "generic-ehci";
300 reg = <0x490500 0x100>;
302 interrupt-parent = <&periph_intc>;
308 compatible = "brcm,bcm7346-ohci", "generic-ohci";
309 reg = <0x490600 0x100>;
312 interrupt-parent = <&periph_intc>;
318 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
319 reg-names = "ahci", "top-ctrl";
320 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
321 interrupt-parent = <&periph_intc>;
323 #address-cells = <1>;
340 sata_phy: sata-phy@1800000 {
341 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
342 reg = <0x180100 0x0eff>;
344 #address-cells = <1>;
348 sata_phy0: sata-phy@0 {
353 sata_phy1: sata-phy@1 {