1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/jz4740-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
8 compatible = "ingenic,jz4740";
10 cpuintc: interrupt-controller {
12 #interrupt-cells = <1>;
14 compatible = "mti,cpu-interrupt-controller";
17 intc: interrupt-controller@10001000 {
18 compatible = "ingenic,jz4740-intc";
19 reg = <0x10001000 0x14>;
22 #interrupt-cells = <1>;
24 interrupt-parent = <&cpuintc>;
29 compatible = "fixed-clock";
34 compatible = "fixed-clock";
36 clock-frequency = <32768>;
39 cgu: jz4740-cgu@10000000 {
40 compatible = "ingenic,jz4740-cgu";
41 reg = <0x10000000 0x100>;
43 clocks = <&ext>, <&rtc>;
44 clock-names = "ext", "rtc";
50 compatible = "ingenic,jz4740-tcu", "simple-mfd";
51 reg = <0x10002000 0x1000>;
54 ranges = <0x0 0x10002000 0x1000>;
58 clocks = <&cgu JZ4740_CLK_RTC
62 clock-names = "rtc", "ext", "pclk", "tcu";
65 #interrupt-cells = <1>;
67 interrupt-parent = <&intc>;
68 interrupts = <23 22 21>;
70 watchdog: watchdog@0 {
71 compatible = "ingenic,jz4740-watchdog";
74 clocks = <&tcu TCU_CLK_WDT>;
79 rtc_dev: rtc@10003000 {
80 compatible = "ingenic,jz4740-rtc";
81 reg = <0x10003000 0x40>;
83 interrupt-parent = <&intc>;
86 clocks = <&cgu JZ4740_CLK_RTC>;
90 pinctrl: pin-controller@10010000 {
91 compatible = "ingenic,jz4740-pinctrl";
92 reg = <0x10010000 0x400>;
98 compatible = "ingenic,jz4740-gpio";
102 gpio-ranges = <&pinctrl 0 0 32>;
105 interrupt-controller;
106 #interrupt-cells = <2>;
108 interrupt-parent = <&intc>;
113 compatible = "ingenic,jz4740-gpio";
117 gpio-ranges = <&pinctrl 0 32 32>;
120 interrupt-controller;
121 #interrupt-cells = <2>;
123 interrupt-parent = <&intc>;
128 compatible = "ingenic,jz4740-gpio";
132 gpio-ranges = <&pinctrl 0 64 32>;
135 interrupt-controller;
136 #interrupt-cells = <2>;
138 interrupt-parent = <&intc>;
143 compatible = "ingenic,jz4740-gpio";
147 gpio-ranges = <&pinctrl 0 96 32>;
150 interrupt-controller;
151 #interrupt-cells = <2>;
153 interrupt-parent = <&intc>;
158 aic: audio-controller@10020000 {
159 compatible = "ingenic,jz4740-i2s";
160 reg = <0x10020000 0x38>;
162 #sound-dai-cells = <0>;
164 interrupt-parent = <&intc>;
167 clocks = <&cgu JZ4740_CLK_AIC>,
168 <&cgu JZ4740_CLK_I2S>,
169 <&cgu JZ4740_CLK_EXT>,
170 <&cgu JZ4740_CLK_PLL_HALF>;
171 clock-names = "aic", "i2s", "ext", "pll half";
173 dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
174 dma-names = "rx", "tx";
177 codec: audio-codec@100200a4 {
178 compatible = "ingenic,jz4740-codec";
179 reg = <0x10020080 0x8>;
181 #sound-dai-cells = <0>;
183 clocks = <&cgu JZ4740_CLK_AIC>;
188 compatible = "ingenic,jz4740-mmc";
189 reg = <0x10021000 0x1000>;
191 clocks = <&cgu JZ4740_CLK_MMC>;
194 interrupt-parent = <&intc>;
197 dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
198 dma-names = "rx", "tx";
205 uart0: serial@10030000 {
206 compatible = "ingenic,jz4740-uart";
207 reg = <0x10030000 0x100>;
209 interrupt-parent = <&intc>;
212 clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
213 clock-names = "baud", "module";
216 uart1: serial@10031000 {
217 compatible = "ingenic,jz4740-uart";
218 reg = <0x10031000 0x100>;
220 interrupt-parent = <&intc>;
223 clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
224 clock-names = "baud", "module";
228 compatible = "ingenic,jz4740-adc";
229 reg = <0x10070000 0x30>;
230 #io-channel-cells = <1>;
232 clocks = <&cgu JZ4740_CLK_ADC>;
235 interrupt-parent = <&intc>;
239 nemc: memory-controller@13010000 {
240 compatible = "ingenic,jz4740-nemc";
241 reg = <0x13010000 0x54>;
242 #address-cells = <2>;
244 ranges = <1 0 0x18000000 0x4000000
245 2 0 0x14000000 0x4000000
246 3 0 0x0c000000 0x4000000
247 4 0 0x08000000 0x4000000>;
249 clocks = <&cgu JZ4740_CLK_MCLK>;
252 ecc: ecc-controller@13010100 {
253 compatible = "ingenic,jz4740-ecc";
254 reg = <0x13010100 0x2C>;
256 clocks = <&cgu JZ4740_CLK_MCLK>;
259 dmac: dma-controller@13020000 {
260 compatible = "ingenic,jz4740-dma";
261 reg = <0x13020000 0xbc
265 interrupt-parent = <&intc>;
268 clocks = <&cgu JZ4740_CLK_DMA>;
272 compatible = "ingenic,jz4740-ohci", "generic-ohci";
273 reg = <0x13030000 0x1000>;
275 clocks = <&cgu JZ4740_CLK_UHC>;
276 assigned-clocks = <&cgu JZ4740_CLK_UHC>;
277 assigned-clock-rates = <48000000>;
279 interrupt-parent = <&intc>;
286 compatible = "ingenic,jz4740-musb";
287 reg = <0x13040000 0x10000>;
289 interrupt-parent = <&intc>;
291 interrupt-names = "mc";
293 clocks = <&cgu JZ4740_CLK_UDC>;
297 lcd: lcd-controller@13050000 {
298 compatible = "ingenic,jz4740-lcd";
299 reg = <0x13050000 0x1000>;
301 interrupt-parent = <&intc>;
304 clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
305 clock-names = "lcd_pclk", "lcd";