arch/mips/boot/dts/mti/malta.dts

   1 /dts-v1/;
   2
   3 #include <dt-bindings/interrupt-controller/irq.h>
   4 #include <dt-bindings/interrupt-controller/mips-gic.h>
   5
   6 /memreserve/ 0x00000000 0x00001000;     /* YAMON exception vectors */
   7 /memreserve/ 0x00001000 0x000ef000;     /* YAMON */
   8 /memreserve/ 0x000f0000 0x00010000;     /* PIIX4 ISA memory */
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13         compatible = "mti,malta";
  14
  15         cpu_intc: interrupt-controller {
  16                 compatible = "mti,cpu-interrupt-controller";
  17
  18                 interrupt-controller;
  19                 #interrupt-cells = <1>;
  20         };
  21
  22         gic: interrupt-controller@1bdc0000 {
  23                 compatible = "mti,gic";
  24                 reg = <0x1bdc0000 0x20000>;
  25
  26                 interrupt-controller;
  27                 #interrupt-cells = <3>;
  28
  29                 /*
  30                  * Declare the interrupt-parent even though the mti,gic
  31                  * binding doesn't require it, such that the kernel can
  32                  * figure out that cpu_intc is the root interrupt
  33                  * controller & should be probed first.
  34                  */
  35                 interrupt-parent = <&cpu_intc>;
  36
  37                 timer {
  38                         compatible = "mti,gic-timer";
  39                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
  40                 };
  41         };
  42
  43         i8259: interrupt-controller@20 {
  44                 compatible = "intel,i8259";
  45
  46                 interrupt-controller;
  47                 #interrupt-cells = <1>;
  48
  49                 interrupt-parent = <&gic>;
  50                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
  51         };
  52
  53         flash@1e000000 {
  54                 compatible = "intel,dt28f160", "cfi-flash";
  55                 reg = <0x1e000000 0x400000>;
  56                 bank-width = <4>;
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59
  60                 partitions {
  61                         compatible = "fixed-partitions";
  62                         #address-cells = <1>;
  63                         #size-cells = <1>;
  64
  65                         yamon@0 {
  66                                 label = "YAMON";
  67                                 reg = <0x0 0x100000>;
  68                                 read-only;
  69                         };
  70
  71                         user-fs@100000 {
  72                                 label = "User FS";
  73                                 reg = <0x100000 0x2e0000>;
  74                         };
  75
  76                         board-config@3e0000 {
  77                                 label = "Board Config";
  78                                 reg = <0x3e0000 0x20000>;
  79                                 read-only;
  80                         };
  81                 };
  82         };
  83
  84         fpga_regs: system-controller@1f000000 {
  85                 compatible = "mti,malta-fpga", "syscon", "simple-mfd";
  86                 reg = <0x1f000000 0x1000>;
  87                 native-endian;
  88
  89                 reboot {
  90                         compatible = "syscon-reboot";
  91                         regmap = <&fpga_regs>;
  92                         offset = <0x500>;
  93                         mask = <0x42>;
  94                 };
  95         };
  96
  97         isa {
  98                 compatible = "isa";
  99                 #address-cells = <2>;
 100                 #size-cells = <1>;
 101                 ranges = <1 0 0 0x1000>;
 102
 103                 rtc@70 {
 104                         compatible = "motorola,mc146818";
 105                         reg = <1 0x70 0x8>;
 106
 107                         interrupt-parent = <&i8259>;
 108                         interrupts = <8>;
 109                 };
 110         };
 111 };