arch/mips/boot/dts/xilfpga/nexys4ddr.dts

   1 /dts-v1/;
   2
   3 #include "microAptiv.dtsi"
   4
   5 / {
   6         compatible = "digilent,nexys4ddr";
   7
   8         memory {
   9                 device_type = "memory";
  10                 reg = <0x0 0x08000000>;
  11         };
  12
  13         cpuintc: interrupt-controller {
  14                 #address-cells = <0>;
  15                 #interrupt-cells = <1>;
  16                 interrupt-controller;
  17                 compatible = "mti,cpu-interrupt-controller";
  18         };
  19
  20         axi_intc: interrupt-controller@10200000 {
  21                 #interrupt-cells = <1>;
  22                 compatible = "xlnx,xps-intc-1.00.a";
  23                 interrupt-controller;
  24                 reg = <0x10200000 0x10000>;
  25                 xlnx,kind-of-intr = <0x0>;
  26                 xlnx,num-intr-inputs = <0x6>;
  27
  28                 interrupt-parent = <&cpuintc>;
  29                 interrupts = <6>;
  30         };
  31
  32         axi_gpio: gpio@10600000 {
  33                 #gpio-cells = <1>;
  34                 compatible = "xlnx,xps-gpio-1.00.a";
  35                 gpio-controller;
  36                 reg = <0x10600000 0x10000>;
  37                 xlnx,all-inputs = <0x0>;
  38                 xlnx,dout-default = <0x0>;
  39                 xlnx,gpio-width = <0x16>;
  40                 xlnx,interrupt-present = <0x0>;
  41                 xlnx,is-dual = <0x0>;
  42                 xlnx,tri-default = <0xffffffff>;
  43         } ;
  44
  45         axi_ethernetlite: ethernet@10e00000 {
  46                 compatible = "xlnx,xps-ethernetlite-3.00.a";
  47                 device_type = "network";
  48                 interrupt-parent = <&axi_intc>;
  49                 interrupts = <1>;
  50                 phy-handle = <&phy0>;
  51                 reg = <0x10e00000 0x10000>;
  52                 xlnx,duplex = <0x1>;
  53                 xlnx,include-global-buffers = <0x1>;
  54                 xlnx,include-internal-loopback = <0x0>;
  55                 xlnx,include-mdio = <0x1>;
  56                 xlnx,instance = "axi_ethernetlite_inst";
  57                 xlnx,rx-ping-pong = <0x1>;
  58                 xlnx,s-axi-id-width = <0x1>;
  59                 xlnx,tx-ping-pong = <0x1>;
  60                 xlnx,use-internal = <0x0>;
  61                 mdio {
  62                         #address-cells = <1>;
  63                         #size-cells = <0>;
  64                         phy0: phy@1 {
  65                                 device_type = "ethernet-phy";
  66                                 reg = <1>;
  67                         };
  68                 };
  69         };
  70
  71         axi_uart16550: serial@10400000 {
  72                 compatible = "ns16550a";
  73                 reg = <0x10400000 0x10000>;
  74
  75                 reg-shift = <2>;
  76                 reg-offset = <0x1000>;
  77
  78                 clocks  = <&ext>;
  79
  80                 interrupt-parent = <&axi_intc>;
  81                 interrupts = <0>;
  82         };
  83
  84         axi_i2c: i2c@10A00000 {
  85             compatible = "xlnx,xps-iic-2.00.a";
  86             interrupt-parent = <&axi_intc>;
  87             interrupts = <4>;
  88             reg = < 0x10A00000 0x10000 >;
  89             clocks = <&ext>;
  90             xlnx,clk-freq = <0x5f5e100>;
  91             xlnx,family = "Artix7";
  92             xlnx,gpo-width = <0x1>;
  93             xlnx,iic-freq = <0x186a0>;
  94             xlnx,scl-inertial-delay = <0x0>;
  95             xlnx,sda-inertial-delay = <0x0>;
  96             xlnx,ten-bit-adr = <0x0>;
  97             #address-cells = <1>;
  98             #size-cells = <0>;
  99
 100             ad7420@4B {
 101                 compatible = "adi,adt7420";
 102                 reg = <0x4B>;
 103             };
 104         } ;
 105 };
 106
 107 &ext {
 108         clock-frequency = <50000000>;
 109 };