arch/mips/cobalt/setup.c

   1 /*
   2  * Setup pointers to hardware dependent routines.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org)
   9  * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
  10  *
  11  */
  12 #include <linux/config.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/pci.h>
  15 #include <linux/init.h>
  16 #include <linux/pm.h>
  17 #include <linux/serial.h>
  18 #include <linux/serial_core.h>
  19
  20 #include <asm/bootinfo.h>
  21 #include <asm/time.h>
  22 #include <asm/io.h>
  23 #include <asm/irq.h>
  24 #include <asm/processor.h>
  25 #include <asm/reboot.h>
  26 #include <asm/gt64120.h>
  27 #include <asm/serial.h>
  28
  29 #include <asm/mach-cobalt/cobalt.h>
  30
  31 extern void cobalt_machine_restart(char *command);
  32 extern void cobalt_machine_halt(void);
  33 extern void cobalt_machine_power_off(void);
  34 extern void cobalt_early_console(void);
  35
  36 int cobalt_board_id;
  37
  38 const char *get_system_type(void)
  39 {
  40         switch (cobalt_board_id) {
  41                 case COBALT_BRD_ID_QUBE1:
  42                         return "Cobalt Qube";
  43                 case COBALT_BRD_ID_RAQ1:
  44                         return "Cobalt RaQ";
  45                 case COBALT_BRD_ID_QUBE2:
  46                         return "Cobalt Qube2";
  47                 case COBALT_BRD_ID_RAQ2:
  48                         return "Cobalt RaQ2";
  49         }
  50         return "MIPS Cobalt";
  51 }
  52
  53 static void __init cobalt_timer_setup(struct irqaction *irq)
  54 {
  55         /* Load timer value for 1KHz (TCLK is 50MHz) */
  56         GALILEO_OUTL(50*1000*1000 / 1000, GT_TC0_OFS);
  57
  58         /* Enable timer */
  59         GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS);
  60
  61         /* Register interrupt */
  62         setup_irq(COBALT_GALILEO_IRQ, irq);
  63
  64         /* Enable interrupt */
  65         GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
  66 }
  67
  68 extern struct pci_ops gt64111_pci_ops;
  69
  70 static struct resource cobalt_mem_resource = {
  71         "PCI memory", GT64111_MEM_BASE, GT64111_MEM_END, IORESOURCE_MEM
  72 };
  73
  74 static struct resource cobalt_io_resource = {
  75         "PCI I/O", 0x1000, 0xffff, IORESOURCE_IO
  76 };
  77
  78 static struct resource cobalt_io_resources[] = {
  79         { "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
  80         { "timer", 0x40, 0x5f, IORESOURCE_BUSY },
  81         { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
  82         { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
  83         { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
  84 };
  85
  86 #define COBALT_IO_RESOURCES (sizeof(cobalt_io_resources)/sizeof(struct resource))
  87
  88 static struct pci_controller cobalt_pci_controller = {
  89         .pci_ops        = &gt64111_pci_ops,
  90         .mem_resource   = &cobalt_mem_resource,
  91         .mem_offset     = 0,
  92         .io_resource    = &cobalt_io_resource,
  93         .io_offset      = 0 - GT64111_IO_BASE
  94 };
  95
  96 void __init plat_setup(void)
  97 {
  98         static struct uart_port uart;
  99         unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
 100         int i;
 101
 102         _machine_restart = cobalt_machine_restart;
 103         _machine_halt = cobalt_machine_halt;
 104         pm_power_off = cobalt_machine_power_off;
 105
 106         board_timer_setup = cobalt_timer_setup;
 107
 108         set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE));
 109
 110         /* I/O port resource must include UART and LCD/buttons */
 111         ioport_resource.end = 0x0fffffff;
 112
 113         /* request I/O space for devices used on all i[345]86 PCs */
 114         for (i = 0; i < COBALT_IO_RESOURCES; i++)
 115                 request_resource(&ioport_resource, cobalt_io_resources + i);
 116
 117         /* Read the cobalt id register out of the PCI config space */
 118         PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
 119         cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS);
 120         cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
 121         cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
 122
 123         printk("Cobalt board ID: %d\n", cobalt_board_id);
 124
 125 #ifdef CONFIG_PCI
 126         register_pci_controller(&cobalt_pci_controller);
 127 #endif
 128
 129 #ifdef CONFIG_SERIAL_8250
 130         if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
 131
 132 #ifdef CONFIG_EARLY_PRINTK
 133                 cobalt_early_console();
 134 #endif
 135
 136                 uart.line       = 0;
 137                 uart.type       = PORT_UNKNOWN;
 138                 uart.uartclk    = 18432000;
 139                 uart.irq        = COBALT_SERIAL_IRQ;
 140                 uart.flags      = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 141                 uart.iobase     = 0xc800000;
 142                 uart.iotype     = UPIO_PORT;
 143
 144                 early_serial_setup(&uart);
 145         }
 146 #endif
 147 }
 148
 149 /*
 150  * Prom init. We read our one and only communication with the firmware.
 151  * Grab the amount of installed memory.
 152  * Better boot loaders (CoLo) pass a command line too :-)
 153  */
 154
 155 void __init prom_init(void)
 156 {
 157         int narg, indx, posn, nchr;
 158         unsigned long memsz;
 159         char **argv;
 160
 161         mips_machgroup = MACH_GROUP_COBALT;
 162
 163         memsz = fw_arg0 & 0x7fff0000;
 164         narg = fw_arg0 & 0x0000ffff;
 165
 166         if (narg) {
 167                 arcs_cmdline[0] = '\0';
 168                 argv = (char **) fw_arg1;
 169                 posn = 0;
 170                 for (indx = 1; indx < narg; ++indx) {
 171                         nchr = strlen(argv[indx]);
 172                         if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline))
 173                                 break;
 174                         if (posn)
 175                                 arcs_cmdline[posn++] = ' ';
 176                         strcpy(arcs_cmdline + posn, argv[indx]);
 177                         posn += nchr;
 178                 }
 179         }
 180
 181         add_memory_region(0x0, memsz, BOOT_MEM_RAM);
 182 }
 183
 184 unsigned long __init prom_free_prom_memory(void)
 185 {
 186         /* Nothing to do! */
 187         return 0;
 188 }